[STM32F3] Removed all specific F3 stuff out of common files.
This commit is contained in:
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a1321fc21f
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ebb058825f
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@ -129,33 +129,6 @@ specific memorymap.h header before including this header file.*/
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/* CRCNEXT: Transmit CRC next */
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/* CRCNEXT: Transmit CRC next */
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#define SPI_CR1_CRCNEXT (1 << 12)
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#define SPI_CR1_CRCNEXT (1 << 12)
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/* DFF: Data frame format */
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/****************************************************************************/
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/** @defgroup spi_dff SPI data frame format
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@ingroup spi_defines
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@{*/
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#if defined(STM32F3)
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#define SPI_DR8(spi_base) MMIO8(spi_base + 0x0c)
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#define SPI1_DR8 SPI_DR8(SPI1_BASE)
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#define SPI2_DR8 SPI_DR8(SPI2_I2S_BASE)
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#define SPI3_DR8 SPI_DR8(SPI3_I2S_BASE)
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#define SPI_CR1_CRCL_8BIT (0 << 11)
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#define SPI_CR1_CRCL_16BIT (1 << 11)
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/**@}*/
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#define SPI_CR1_CRCL (1 << 11)
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#elif !defined(STM32F3)
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#define SPI_CR1_DFF_8BIT (0 << 11)
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#define SPI_CR1_DFF_16BIT (1 << 11)
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/**@}*/
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#define SPI_CR1_DFF (1 << 11)
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#endif
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/* RXONLY: Receive only */
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/* RXONLY: Receive only */
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#define SPI_CR1_RXONLY (1 << 10)
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#define SPI_CR1_RXONLY (1 << 10)
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@ -235,41 +208,7 @@ specific memorymap.h header before including this header file.*/
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/* --- SPI_CR2 values ------------------------------------------------------ */
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/* --- SPI_CR2 values ------------------------------------------------------ */
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/* Bits [15:8]: Reserved. Forced to 0 by hardware. */
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/* Bits [15:8]: Reserved. Forced to 0 by hardware. Used on F3. */
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#if defined(STM32F3)
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/* LDMA_TX: Last DMA transfer for transmission */
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#define SPI_CR2_LDMA_TX (1 << 14)
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/* LDMA_RX: Last DMA transfer for reception */
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#define SPI_CR2_LDMA_RX (1 << 13)
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/* FRXTH: FIFO reception threshold */
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#define SPI_CR2_FRXTH (1 << 12)
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/* DS [3:0]: Data size */
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// 0x0 - 0x2 NOT USED
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#define SPI_CR2_DS_4BIT (0x3 << 8)
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#define SPI_CR2_DS_5BIT (0x4 << 8)
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#define SPI_CR2_DS_6BIT (0x5 << 8)
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#define SPI_CR2_DS_7BIT (0x6 << 8)
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#define SPI_CR2_DS_8BIT (0x7 << 8)
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#define SPI_CR2_DS_9BIT (0x8 << 8)
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#define SPI_CR2_DS_10BIT (0x9 << 8)
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#define SPI_CR2_DS_11BIT (0xA << 8)
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#define SPI_CR2_DS_12BIT (0xB << 8)
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#define SPI_CR2_DS_13BIT (0xC << 8)
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#define SPI_CR2_DS_14BIT (0xD << 8)
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#define SPI_CR2_DS_15BIT (0xE << 8)
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#define SPI_CR2_DS_16BIT (0xF << 8)
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#define SPI_CR2_DS_MASK (0xF << 8)
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/* NSSP: NSS pulse management */
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#define SPI_CR2_NSSP (1 << 3)
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#endif
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/* TXEIE: Tx buffer empty interrupt enable */
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/* TXEIE: Tx buffer empty interrupt enable */
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#define SPI_CR2_TXEIE (1 << 7)
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#define SPI_CR2_TXEIE (1 << 7)
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@ -294,23 +233,7 @@ specific memorymap.h header before including this header file.*/
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/* --- SPI_SR values ------------------------------------------------------- */
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/* --- SPI_SR values ------------------------------------------------------- */
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/* Bits [15:8]: Reserved. Forced to 0 by hardware. */
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/* Bits [15:8]: Reserved. Forced to 0 by hardware. Used on F3. */
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#if defined(STM32F3)
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/* FTLVL[1:0]: FIFO Transmission Level */
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#define SPI_SR_FTLVL_FIFO_EMPTY (0x0 << 11)
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#define SPI_SR_FTLVL_QUARTER_FIFO (0x1 << 11)
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#define SPI_SR_FTLVL_HALF_FIFO (0x2 << 11)
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#define SPI_SR_FTLVL_FIFO_FULL (0x3 << 11)
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/* FRLVL[1:0]: FIFO Reception Level */
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#define SPI_SR_FRLVL_FIFO_EMPTY (0x0 << 9)
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#define SPI_SR_FRLVL_QUARTER_FIFO (0x1 << 9)
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#define SPI_SR_FRLVL_HALF_FIFO (0x2 << 9)
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#define SPI_SR_FRLVL_FIFO_FULL (0x3 << 9)
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#endif
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/* BSY: Busy flag */
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/* BSY: Busy flag */
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#define SPI_SR_BSY (1 << 7)
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#define SPI_SR_BSY (1 << 7)
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@ -469,16 +392,6 @@ void spi_disable_tx_dma(uint32_t spi);
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void spi_enable_rx_dma(uint32_t spi);
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void spi_enable_rx_dma(uint32_t spi);
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void spi_disable_rx_dma(uint32_t spi);
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void spi_disable_rx_dma(uint32_t spi);
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#ifdef STM32F3
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void spi_set_data_size(uint32_t spi, uint16_t data_s);
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void spi_fifo_reception_threshold_8bit(uint32_t spi);
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void spi_fifo_reception_threshold_16bit(uint32_t spi);
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void spi_i2s_mode_spi_mode(uint32_t spi);
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void spi_send8(uint32_t spi, uint8_t data);
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uint8_t spi_read8(uint32_t spi);
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#endif
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END_DECLS
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END_DECLS
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/**@}*/
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/**@}*/
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@ -0,0 +1,65 @@
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/** @addtogroup spi_defines
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@author @htmlonly © @endhtmlonly 2011 Fergus Noble <fergusnoble@gmail.com>
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA SPI.H
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The order of header inclusion is important. spi.h includes the device
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specific memorymap.h header before including this header file.*/
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/** @cond */
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#ifdef LIBOPENCM3_SPI_H
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/** @endcond */
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#ifndef LIBOPENCM3_SPI_COMMON_F0124_H
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#define LIBOPENCM3_SPI_COMMON_F0124_H
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/**@{*/
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#include <libopencm3/stm32/common/spi_common_all.h>
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/*
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* This file extends the common STM32 version with definitions only
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* applicable to the STM32F0/1/2/4 series of devices.
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*/
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/* DFF: Data frame format */
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/****************************************************************************/
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/** @defgroup spi_dff SPI data frame format
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@ingroup spi_defines
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@{*/
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#define SPI_CR1_DFF_8BIT (0 << 11)
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#define SPI_CR1_DFF_16BIT (1 << 11)
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/**@}*/
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#define SPI_CR1_DFF (1 << 11)
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#endif
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/** @cond */
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#else
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#warning "spi_common_f24.h should not be included explicitly, only via spi.h"
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#endif
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/** @endcond */
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/**@}*/
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@ -34,7 +34,7 @@ specific memorymap.h header before including this header file.*/
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/**@{*/
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/**@{*/
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#include <libopencm3/stm32/common/spi_common_all.h>
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#include <libopencm3/stm32/common/spi_common_f0124.h>
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/*
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/*
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* This file extends the common STM32 version with definitions only
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* This file extends the common STM32 version with definitions only
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@ -32,7 +32,7 @@ LGPL License Terms @ref lgpl_license
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#define LIBOPENCM3_SPI_H
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#define LIBOPENCM3_SPI_H
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#include <libopencm3/stm32/memorymap.h>
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#include <libopencm3/stm32/memorymap.h>
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#include <libopencm3/stm32/common/spi_common_all.h>
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#include <libopencm3/stm32/common/spi_common_f0124.h>
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#endif
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#endif
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@ -32,7 +32,81 @@ LGPL License Terms @ref lgpl_license
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#define LIBOPENCM3_SPI_H
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#define LIBOPENCM3_SPI_H
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#include <libopencm3/stm32/memorymap.h>
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#include <libopencm3/stm32/memorymap.h>
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#include <libopencm3/stm32/common/spi_common_f24.h>
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#include <libopencm3/stm32/common/spi_common_all.h>
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#endif
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/* DFF: Data frame format */
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/****************************************************************************/
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/** @defgroup spi_dff SPI data frame format
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@ingroup spi_defines
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@{*/
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#define SPI_DR8(spi_base) MMIO8(spi_base + 0x0c)
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#define SPI1_DR8 SPI_DR8(SPI1_BASE)
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#define SPI2_DR8 SPI_DR8(SPI2_I2S_BASE)
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#define SPI3_DR8 SPI_DR8(SPI3_I2S_BASE)
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#define SPI_CR1_CRCL_8BIT (0 << 11)
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#define SPI_CR1_CRCL_16BIT (1 << 11)
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/**@}*/
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#define SPI_CR1_CRCL (1 << 11)
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/* --- SPI_CR2 values ------------------------------------------------------ */
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/* LDMA_TX: Last DMA transfer for transmission */
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#define SPI_CR2_LDMA_TX (1 << 14)
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/* LDMA_RX: Last DMA transfer for reception */
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#define SPI_CR2_LDMA_RX (1 << 13)
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/* FRXTH: FIFO reception threshold */
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#define SPI_CR2_FRXTH (1 << 12)
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/* DS [3:0]: Data size */
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// 0x0 - 0x2 NOT USED
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#define SPI_CR2_DS_4BIT (0x3 << 8)
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#define SPI_CR2_DS_5BIT (0x4 << 8)
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#define SPI_CR2_DS_6BIT (0x5 << 8)
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#define SPI_CR2_DS_7BIT (0x6 << 8)
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#define SPI_CR2_DS_8BIT (0x7 << 8)
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#define SPI_CR2_DS_9BIT (0x8 << 8)
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#define SPI_CR2_DS_10BIT (0x9 << 8)
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#define SPI_CR2_DS_11BIT (0xA << 8)
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#define SPI_CR2_DS_12BIT (0xB << 8)
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#define SPI_CR2_DS_13BIT (0xC << 8)
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#define SPI_CR2_DS_14BIT (0xD << 8)
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#define SPI_CR2_DS_15BIT (0xE << 8)
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#define SPI_CR2_DS_16BIT (0xF << 8)
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#define SPI_CR2_DS_MASK (0xF << 8)
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/* NSSP: NSS pulse management */
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#define SPI_CR2_NSSP (1 << 3)
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/* --- SPI_SR values ------------------------------------------------------- */
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/* FTLVL[1:0]: FIFO Transmission Level */
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#define SPI_SR_FTLVL_FIFO_EMPTY (0x0 << 11)
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#define SPI_SR_FTLVL_QUARTER_FIFO (0x1 << 11)
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#define SPI_SR_FTLVL_HALF_FIFO (0x2 << 11)
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#define SPI_SR_FTLVL_FIFO_FULL (0x3 << 11)
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/* FRLVL[1:0]: FIFO Reception Level */
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#define SPI_SR_FRLVL_FIFO_EMPTY (0x0 << 9)
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#define SPI_SR_FRLVL_QUARTER_FIFO (0x1 << 9)
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#define SPI_SR_FRLVL_HALF_FIFO (0x2 << 9)
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#define SPI_SR_FRLVL_FIFO_FULL (0x3 << 9)
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/* --- Function prototypes ------------------------------------------------- */
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BEGIN_DECLS
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void spi_set_data_size(uint32_t spi, uint16_t data_s);
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void spi_fifo_reception_threshold_8bit(uint32_t spi);
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void spi_fifo_reception_threshold_16bit(uint32_t spi);
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void spi_i2s_mode_spi_mode(uint32_t spi);
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void spi_send8(uint32_t spi, uint8_t data);
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uint8_t spi_read8(uint32_t spi);
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END_DECLS
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#endif
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@ -99,53 +99,6 @@ void spi_reset(uint32_t spi_peripheral)
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}
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}
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}
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Configure the SPI as Master.
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The SPI peripheral is configured as a master with communication parameters
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baudrate, data format 8/16 bits, frame format lsb/msb first, clock polarity
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and phase. The SPI enable, CRC enable and CRC next controls are not affected.
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These must be controlled separately.
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@todo NSS pin handling.
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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@param[in] br Unsigned int32. Baudrate @ref spi_baudrate.
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@param[in] cpol Unsigned int32. Clock polarity @ref spi_cpol.
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@param[in] cpha Unsigned int32. Clock Phase @ref spi_cpha.
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@param[in] dff Unsigned int32. Data frame format 8/16 bits @ref spi_dff.
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@param[in] lsbfirst Unsigned int32. Frame format lsb/msb first @ref
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spi_lsbfirst.
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@returns int. Error code.
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*/
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#ifndef STM32F3
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int spi_init_master(uint32_t spi, uint32_t br, uint32_t cpol, uint32_t cpha,
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uint32_t dff, uint32_t lsbfirst)
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{
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uint32_t reg32 = SPI_CR1(spi);
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/* Reset all bits omitting SPE, CRCEN and CRCNEXT bits. */
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reg32 &= SPI_CR1_SPE | SPI_CR1_CRCEN | SPI_CR1_CRCNEXT;
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reg32 |= SPI_CR1_MSTR; /* Configure SPI as master. */
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reg32 |= br; /* Set baud rate bits. */
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reg32 |= cpol; /* Set CPOL value. */
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reg32 |= cpha; /* Set CPHA value. */
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reg32 |= dff; /* Set data format (8 or 16 bits). */
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reg32 |= lsbfirst; /* Set frame format (LSB- or MSB-first). */
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/* TODO: NSS pin handling. */
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SPI_CR1(spi) = reg32;
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return 0; /* TODO */
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}
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#endif
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/* TODO: Error handling? */
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/* TODO: Error handling? */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Enable.
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/** @brief SPI Enable.
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@ -398,72 +351,6 @@ void spi_set_next_tx_from_crc(uint32_t spi)
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SPI_CR1(spi) |= SPI_CR1_CRCNEXT;
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SPI_CR1(spi) |= SPI_CR1_CRCNEXT;
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||||||
}
|
}
|
||||||
|
|
||||||
#ifdef STM32F3
|
|
||||||
|
|
||||||
void spi_send8(uint32_t spi, uint8_t data)
|
|
||||||
{
|
|
||||||
/* Wait for transfer finished. */
|
|
||||||
while (!(SPI_SR(spi) & SPI_SR_TXE));
|
|
||||||
|
|
||||||
/* Write data (8 or 16 bits, depending on DFF) into DR. */
|
|
||||||
SPI_DR8(spi) = data;
|
|
||||||
}
|
|
||||||
|
|
||||||
uint8_t spi_read8(uint32_t spi)
|
|
||||||
{
|
|
||||||
/* Wait for transfer finished. */
|
|
||||||
while (!(SPI_SR(spi) & SPI_SR_RXNE));
|
|
||||||
|
|
||||||
/* Read the data (8 or 16 bits, depending on DFF bit) from DR. */
|
|
||||||
return SPI_DR8(spi);
|
|
||||||
}
|
|
||||||
|
|
||||||
void spi_set_data_size(uint32_t spi, uint16_t data_s)
|
|
||||||
{
|
|
||||||
SPI_CR2(spi) = (SPI_CR2(spi) & ~SPI_CR2_DS_MASK) | (data_s & SPI_CR2_DS_MASK);
|
|
||||||
}
|
|
||||||
|
|
||||||
void spi_fifo_reception_threshold_8bit(uint32_t spi)
|
|
||||||
{
|
|
||||||
SPI_CR2(spi) |= SPI_CR2_FRXTH;
|
|
||||||
}
|
|
||||||
|
|
||||||
void spi_fifo_reception_threshold_16bit(uint32_t spi)
|
|
||||||
{
|
|
||||||
SPI_CR2(spi) &= ~SPI_CR2_FRXTH;
|
|
||||||
}
|
|
||||||
|
|
||||||
void spi_i2s_mode_spi_mode(uint32_t spi)
|
|
||||||
{
|
|
||||||
SPI_I2SCFGR(spi) &= ~SPI_I2SCFGR_I2SMOD;
|
|
||||||
}
|
|
||||||
|
|
||||||
#else /*STM32F3*/
|
|
||||||
|
|
||||||
/*---------------------------------------------------------------------------*/
|
|
||||||
/** @brief SPI Set Data Frame Format to 8 bits
|
|
||||||
|
|
||||||
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
|
|
||||||
*/
|
|
||||||
|
|
||||||
void spi_set_dff_8bit(uint32_t spi)
|
|
||||||
{
|
|
||||||
SPI_CR1(spi) &= ~SPI_CR1_DFF;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*---------------------------------------------------------------------------*/
|
|
||||||
/** @brief SPI Set Data Frame Format to 16 bits
|
|
||||||
|
|
||||||
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
|
|
||||||
*/
|
|
||||||
|
|
||||||
void spi_set_dff_16bit(uint32_t spi)
|
|
||||||
{
|
|
||||||
SPI_CR1(spi) |= SPI_CR1_DFF;
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
||||||
/** @brief SPI Set Full Duplex (3-wire) Mode
|
/** @brief SPI Set Full Duplex (3-wire) Mode
|
||||||
|
|
||||||
|
|
|
@ -0,0 +1,137 @@
|
||||||
|
/** @addtogroup spi_file
|
||||||
|
|
||||||
|
@author @htmlonly © @endhtmlonly 2009
|
||||||
|
Uwe Hermann <uwe@hermann-uwe.de>
|
||||||
|
@author @htmlonly © @endhtmlonly 2012
|
||||||
|
Ken Sarkies <ksarkies@internode.on.net>
|
||||||
|
|
||||||
|
Devices can have up to three SPI peripherals. The common 4-wire full-duplex
|
||||||
|
mode of operation is supported, along with 3-wire variants using unidirectional
|
||||||
|
communication modes or half-duplex bidirectional communication. A variety of
|
||||||
|
options allows many of the SPI variants to be supported. Multimaster operation
|
||||||
|
is also supported. A CRC can be generated and checked in hardware.
|
||||||
|
|
||||||
|
@note Some JTAG pins need to be remapped if SPI is to be used.
|
||||||
|
|
||||||
|
@note The I2S protocol shares the SPI hardware so the two protocols cannot be
|
||||||
|
used at the same time on the same peripheral.
|
||||||
|
|
||||||
|
Example: 1Mbps, positive clock polarity, leading edge trigger, 8-bit words,
|
||||||
|
LSB first.
|
||||||
|
@code
|
||||||
|
spi_init_master(SPI1, 1000000, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE,
|
||||||
|
SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT,
|
||||||
|
SPI_CR1_LSBFIRST);
|
||||||
|
spi_write(SPI1, 0x55); // 8-bit write
|
||||||
|
spi_write(SPI1, 0xaa88); // 16-bit write
|
||||||
|
reg8 = spi_read(SPI1); // 8-bit read
|
||||||
|
reg16 = spi_read(SPI1); // 16-bit read
|
||||||
|
@endcode
|
||||||
|
|
||||||
|
@todo need additional functions to aid ISRs in retrieving status
|
||||||
|
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* This file is part of the libopencm3 project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
|
||||||
|
*
|
||||||
|
* This library is free software: you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU Lesser General Public License as published by
|
||||||
|
* the Free Software Foundation, either version 3 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This library is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU Lesser General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU Lesser General Public License
|
||||||
|
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <libopencm3/stm32/spi.h>
|
||||||
|
#include <libopencm3/stm32/rcc.h>
|
||||||
|
|
||||||
|
/*
|
||||||
|
* SPI and I2S code.
|
||||||
|
*
|
||||||
|
* Examples:
|
||||||
|
* spi_init_master(SPI1, 1000000, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE,
|
||||||
|
* SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT,
|
||||||
|
* SPI_CR1_LSBFIRST);
|
||||||
|
* spi_write(SPI1, 0x55); // 8-bit write
|
||||||
|
* spi_write(SPI1, 0xaa88); // 16-bit write
|
||||||
|
* reg8 = spi_read(SPI1); // 8-bit read
|
||||||
|
* reg16 = spi_read(SPI1); // 16-bit read
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**@{*/
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------*/
|
||||||
|
/** @brief Configure the SPI as Master.
|
||||||
|
|
||||||
|
The SPI peripheral is configured as a master with communication parameters
|
||||||
|
baudrate, data format 8/16 bits, frame format lsb/msb first, clock polarity
|
||||||
|
and phase. The SPI enable, CRC enable and CRC next controls are not affected.
|
||||||
|
These must be controlled separately.
|
||||||
|
|
||||||
|
@todo NSS pin handling.
|
||||||
|
|
||||||
|
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
|
||||||
|
@param[in] br Unsigned int32. Baudrate @ref spi_baudrate.
|
||||||
|
@param[in] cpol Unsigned int32. Clock polarity @ref spi_cpol.
|
||||||
|
@param[in] cpha Unsigned int32. Clock Phase @ref spi_cpha.
|
||||||
|
@param[in] dff Unsigned int32. Data frame format 8/16 bits @ref spi_dff.
|
||||||
|
@param[in] lsbfirst Unsigned int32. Frame format lsb/msb first @ref
|
||||||
|
spi_lsbfirst.
|
||||||
|
@returns int. Error code.
|
||||||
|
*/
|
||||||
|
|
||||||
|
int spi_init_master(uint32_t spi, uint32_t br, uint32_t cpol, uint32_t cpha,
|
||||||
|
uint32_t dff, uint32_t lsbfirst)
|
||||||
|
{
|
||||||
|
uint32_t reg32 = SPI_CR1(spi);
|
||||||
|
|
||||||
|
/* Reset all bits omitting SPE, CRCEN and CRCNEXT bits. */
|
||||||
|
reg32 &= SPI_CR1_SPE | SPI_CR1_CRCEN | SPI_CR1_CRCNEXT;
|
||||||
|
|
||||||
|
reg32 |= SPI_CR1_MSTR; /* Configure SPI as master. */
|
||||||
|
|
||||||
|
reg32 |= br; /* Set baud rate bits. */
|
||||||
|
reg32 |= cpol; /* Set CPOL value. */
|
||||||
|
reg32 |= cpha; /* Set CPHA value. */
|
||||||
|
reg32 |= dff; /* Set data format (8 or 16 bits). */
|
||||||
|
reg32 |= lsbfirst; /* Set frame format (LSB- or MSB-first). */
|
||||||
|
|
||||||
|
/* TODO: NSS pin handling. */
|
||||||
|
|
||||||
|
SPI_CR1(spi) = reg32;
|
||||||
|
|
||||||
|
return 0; /* TODO */
|
||||||
|
}
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------*/
|
||||||
|
/** @brief SPI Set Data Frame Format to 8 bits
|
||||||
|
|
||||||
|
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
|
||||||
|
*/
|
||||||
|
|
||||||
|
void spi_set_dff_8bit(uint32_t spi)
|
||||||
|
{
|
||||||
|
SPI_CR1(spi) &= ~SPI_CR1_DFF;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------*/
|
||||||
|
/** @brief SPI Set Data Frame Format to 16 bits
|
||||||
|
|
||||||
|
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
|
||||||
|
*/
|
||||||
|
|
||||||
|
void spi_set_dff_16bit(uint32_t spi)
|
||||||
|
{
|
||||||
|
SPI_CR1(spi) |= SPI_CR1_DFF;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**@}*/
|
|
@ -38,7 +38,7 @@ OBJS = adc.o can.o desig.o exti.o ethernet.o flash.o gpio.o \
|
||||||
|
|
||||||
OBJS += crc_common_all.o dac_common_all.o dma_common_f13.o \
|
OBJS += crc_common_all.o dac_common_all.o dma_common_f13.o \
|
||||||
gpio_common_all.o i2c_common_all.o iwdg_common_all.o \
|
gpio_common_all.o i2c_common_all.o iwdg_common_all.o \
|
||||||
pwr_common_all.o spi_common_all.o \
|
pwr_common_all.o spi_common_all.o spi_common_f0124.o \
|
||||||
timer_common_all.o usart_common_all.o
|
timer_common_all.o usart_common_all.o
|
||||||
|
|
||||||
OBJS += usb.o usb_control.o usb_standard.o usb_f103.o usb_f107.o \
|
OBJS += usb.o usb_control.o usb_standard.o usb_f103.o usb_f107.o \
|
||||||
|
|
|
@ -38,9 +38,9 @@ OBJS = gpio.o exti2.o rcc.o
|
||||||
OBJS += crc_common_all.o dac_common_all.o dma_common_f24.o \
|
OBJS += crc_common_all.o dac_common_all.o dma_common_f24.o \
|
||||||
gpio_common_all.o gpio_common_f234.o i2c_common_all.o \
|
gpio_common_all.o gpio_common_f234.o i2c_common_all.o \
|
||||||
iwdg_common_all.o rtc_common_bcd.o spi_common_all.o \
|
iwdg_common_all.o rtc_common_bcd.o spi_common_all.o \
|
||||||
timer_common_all.o timer_common_f24.o usart_common_all.o \
|
spi_common_f0124.o timer_common_all.o timer_common_f24.o \
|
||||||
flash_common_f234.o flash_common_f24.o hash_common_f24.o \
|
usart_common_all.o flash_common_f234.o flash_common_f24.o \
|
||||||
crypto_common_f24.o
|
hash_common_f24.o crypto_common_f24.o
|
||||||
|
|
||||||
VPATH += ../../usb:../:../../cm3:../common
|
VPATH += ../../usb:../:../../cm3:../common
|
||||||
|
|
||||||
|
|
|
@ -34,7 +34,7 @@ CFLAGS = -Os -g \
|
||||||
# ARFLAGS = rcsv
|
# ARFLAGS = rcsv
|
||||||
ARFLAGS = rcs
|
ARFLAGS = rcs
|
||||||
|
|
||||||
OBJS = rcc.o gpio.o adc.o exti2.o i2c.o
|
OBJS = rcc.o gpio.o adc.o exti2.o i2c.o spi.o
|
||||||
|
|
||||||
OBJS += gpio_common_all.o gpio_common_f234.o \
|
OBJS += gpio_common_all.o gpio_common_f234.o \
|
||||||
dac_common_all.o usart_common_all.o crc_common_all.o\
|
dac_common_all.o usart_common_all.o crc_common_all.o\
|
||||||
|
|
|
@ -0,0 +1,60 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the libopencm3 project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
|
||||||
|
*
|
||||||
|
* This library is free software: you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU Lesser General Public License as published by
|
||||||
|
* the Free Software Foundation, either version 3 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This library is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU Lesser General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU Lesser General Public License
|
||||||
|
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <libopencm3/stm32/spi.h>
|
||||||
|
#include <libopencm3/stm32/rcc.h>
|
||||||
|
|
||||||
|
void spi_send8(uint32_t spi, uint8_t data)
|
||||||
|
{
|
||||||
|
/* Wait for transfer finished. */
|
||||||
|
while (!(SPI_SR(spi) & SPI_SR_TXE));
|
||||||
|
|
||||||
|
/* Write data (8 or 16 bits, depending on DFF) into DR. */
|
||||||
|
SPI_DR8(spi) = data;
|
||||||
|
}
|
||||||
|
|
||||||
|
uint8_t spi_read8(uint32_t spi)
|
||||||
|
{
|
||||||
|
/* Wait for transfer finished. */
|
||||||
|
while (!(SPI_SR(spi) & SPI_SR_RXNE));
|
||||||
|
|
||||||
|
/* Read the data (8 or 16 bits, depending on DFF bit) from DR. */
|
||||||
|
return SPI_DR8(spi);
|
||||||
|
}
|
||||||
|
|
||||||
|
void spi_set_data_size(uint32_t spi, uint16_t data_s)
|
||||||
|
{
|
||||||
|
SPI_CR2(spi) = (SPI_CR2(spi) & ~SPI_CR2_DS_MASK) |
|
||||||
|
(data_s & SPI_CR2_DS_MASK);
|
||||||
|
}
|
||||||
|
|
||||||
|
void spi_fifo_reception_threshold_8bit(uint32_t spi)
|
||||||
|
{
|
||||||
|
SPI_CR2(spi) |= SPI_CR2_FRXTH;
|
||||||
|
}
|
||||||
|
|
||||||
|
void spi_fifo_reception_threshold_16bit(uint32_t spi)
|
||||||
|
{
|
||||||
|
SPI_CR2(spi) &= ~SPI_CR2_FRXTH;
|
||||||
|
}
|
||||||
|
|
||||||
|
void spi_i2s_mode_spi_mode(uint32_t spi)
|
||||||
|
{
|
||||||
|
SPI_I2SCFGR(spi) &= ~SPI_I2SCFGR_I2SMOD;
|
||||||
|
}
|
|
@ -39,9 +39,9 @@ OBJS = adc.o can.o gpio.o exti2.o pwr.o rcc.o rtc.o crypto.o
|
||||||
OBJS += crc_common_all.o dac_common_all.o dma_common_f24.o \
|
OBJS += crc_common_all.o dac_common_all.o dma_common_f24.o \
|
||||||
gpio_common_all.o gpio_common_f234.o i2c_common_all.o \
|
gpio_common_all.o gpio_common_f234.o i2c_common_all.o \
|
||||||
iwdg_common_all.o pwr_common_all.o rtc_common_bcd.o \
|
iwdg_common_all.o pwr_common_all.o rtc_common_bcd.o \
|
||||||
spi_common_all.o timer_common_all.o timer_common_f24.o \
|
spi_common_all.o spi_common_f0124.o timer_common_all.o \
|
||||||
usart_common_all.o flash_common_f234.o flash_common_f24.o \
|
timer_common_f24.o usart_common_all.o flash_common_f234.o \
|
||||||
hash_common_f24.o crypto_common_f24.o
|
flash_common_f24.o hash_common_f24.o crypto_common_f24.o
|
||||||
|
|
||||||
OBJS += usb.o usb_standard.o usb_control.o usb_fx07_common.o \
|
OBJS += usb.o usb_standard.o usb_control.o usb_fx07_common.o \
|
||||||
usb_f107.o usb_f207.o
|
usb_f107.o usb_f207.o
|
||||||
|
|
|
@ -20,7 +20,8 @@
|
||||||
"settings":
|
"settings":
|
||||||
{
|
{
|
||||||
"tab_size": 8,
|
"tab_size": 8,
|
||||||
"translate_tabs_to_spaces": false
|
"translate_tabs_to_spaces": false,
|
||||||
|
"rulers": [80]
|
||||||
},
|
},
|
||||||
"build_systems":
|
"build_systems":
|
||||||
[
|
[
|
||||||
|
|
Loading…
Reference in New Issue