694 lines
20 KiB
C
694 lines
20 KiB
C
/** @addtogroup spi_file
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@author @htmlonly © @endhtmlonly 2009
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Uwe Hermann <uwe@hermann-uwe.de>
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@author @htmlonly © @endhtmlonly 2012
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Ken Sarkies <ksarkies@internode.on.net>
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Devices can have up to three SPI peripherals. The common 4-wire full-duplex
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mode of operation is supported, along with 3-wire variants using unidirectional
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communication modes or half-duplex bidirectional communication. A variety of
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options allows many of the SPI variants to be supported. Multimaster operation
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is also supported. A CRC can be generated and checked in hardware.
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@note Some JTAG pins need to be remapped if SPI is to be used.
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@note The I2S protocol shares the SPI hardware so the two protocols cannot be
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used at the same time on the same peripheral.
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Example: 1Mbps, positive clock polarity, leading edge trigger, 8-bit words,
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LSB first.
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@code
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spi_init_master(SPI1, 1000000, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE,
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SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT,
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SPI_CR1_LSBFIRST);
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spi_write(SPI1, 0x55); // 8-bit write
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spi_write(SPI1, 0xaa88); // 16-bit write
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reg8 = spi_read(SPI1); // 8-bit read
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reg16 = spi_read(SPI1); // 16-bit read
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@endcode
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@todo need additional functions to aid ISRs in retrieving status
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <libopencm3/stm32/spi.h>
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#include <libopencm3/stm32/rcc.h>
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/*
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* SPI and I2S code.
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*
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* Examples:
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* spi_init_master(SPI1, 1000000, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE,
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* SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT,
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* SPI_CR1_LSBFIRST);
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* spi_write(SPI1, 0x55); // 8-bit write
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* spi_write(SPI1, 0xaa88); // 16-bit write
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* reg8 = spi_read(SPI1); // 8-bit read
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* reg16 = spi_read(SPI1); // 16-bit read
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*/
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/**@{*/
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Reset.
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The SPI peripheral and all its associated configuration registers are placed in
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the reset condition. The reset is effected via the RCC peripheral reset system.
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@param[in] spi_peripheral Unsigned int32. SPI peripheral identifier @ref
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spi_reg_base.
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*/
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void spi_reset(uint32_t spi_peripheral)
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{
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switch (spi_peripheral) {
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case SPI1:
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rcc_peripheral_reset(&RCC_APB2RSTR, RCC_APB2RSTR_SPI1RST);
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rcc_peripheral_clear_reset(&RCC_APB2RSTR, RCC_APB2RSTR_SPI1RST);
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break;
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case SPI2:
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rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_SPI2RST);
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rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_SPI2RST);
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break;
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#if defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4)
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case SPI3:
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rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_SPI3RST);
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rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_SPI3RST);
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break;
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#endif
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}
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}
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/* TODO: Error handling? */
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Enable.
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The SPI peripheral is enabled.
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@todo Error handling?
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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*/
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void spi_enable(uint32_t spi)
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{
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SPI_CR1(spi) |= SPI_CR1_SPE; /* Enable SPI. */
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}
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/* TODO: Error handling? */
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Disable.
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The SPI peripheral is disabled.
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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*/
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void spi_disable(uint32_t spi)
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{
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uint32_t reg32;
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reg32 = SPI_CR1(spi);
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reg32 &= ~(SPI_CR1_SPE); /* Disable SPI. */
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SPI_CR1(spi) = reg32;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Clean Disable.
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Disable the SPI peripheral according to the procedure in section 23.3.8 of the
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reference manual. This prevents corruption of any ongoing transfers and
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prevents the BSY flag from becoming unreliable.
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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@returns data Unsigned int16. 8 or 16 bit data from final read.
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*/
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uint16_t spi_clean_disable(uint32_t spi)
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{
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/* Wait to receive last data */
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while (!(SPI_SR(spi) & SPI_SR_RXNE));
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uint16_t data = SPI_DR(spi);
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/* Wait to transmit last data */
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while (!(SPI_SR(spi) & SPI_SR_TXE));
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/* Wait until not busy */
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while (SPI_SR(spi) & SPI_SR_BSY);
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SPI_CR1(spi) &= ~SPI_CR1_SPE;
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return data;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Data Write.
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Data is written to the SPI interface.
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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@param[in] data Unsigned int16. 8 or 16 bit data to be written.
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*/
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void spi_write(uint32_t spi, uint16_t data)
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{
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/* Write data (8 or 16 bits, depending on DFF) into DR. */
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SPI_DR(spi) = data;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Data Write with Blocking.
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Data is written to the SPI interface after the previous write transfer has
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finished.
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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@param[in] data Unsigned int16. 8 or 16 bit data to be written.
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*/
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void spi_send(uint32_t spi, uint16_t data)
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{
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/* Wait for transfer finished. */
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while (!(SPI_SR(spi) & SPI_SR_TXE));
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/* Write data (8 or 16 bits, depending on DFF) into DR. */
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SPI_DR(spi) = data;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Data Read.
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Data is read from the SPI interface after the incoming transfer has finished.
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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@returns data Unsigned int16. 8 or 16 bit data.
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*/
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uint16_t spi_read(uint32_t spi)
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{
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/* Wait for transfer finished. */
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while (!(SPI_SR(spi) & SPI_SR_RXNE));
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/* Read the data (8 or 16 bits, depending on DFF bit) from DR. */
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return SPI_DR(spi);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Data Write and Read Exchange.
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Data is written to the SPI interface, then a read is done after the incoming
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transfer has finished.
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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@param[in] data Unsigned int16. 8 or 16 bit data to be written.
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@returns data Unsigned int16. 8 or 16 bit data.
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*/
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uint16_t spi_xfer(uint32_t spi, uint16_t data)
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{
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spi_write(spi, data);
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/* Wait for transfer finished. */
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while (!(SPI_SR(spi) & SPI_SR_RXNE));
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/* Read the data (8 or 16 bits, depending on DFF bit) from DR. */
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return SPI_DR(spi);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Set Bidirectional Simplex Mode.
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The SPI peripheral is set for bidirectional transfers in two-wire simplex mode
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(using a clock wire and a bidirectional data wire).
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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*/
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void spi_set_bidirectional_mode(uint32_t spi)
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{
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SPI_CR1(spi) |= SPI_CR1_BIDIMODE;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Set Unidirectional Mode.
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The SPI peripheral is set for unidirectional transfers. This is used in full
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duplex mode or when the SPI is placed in two-wire simplex mode that uses a
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clock wire and a unidirectional data wire.
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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*/
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void spi_set_unidirectional_mode(uint32_t spi)
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{
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SPI_CR1(spi) &= ~SPI_CR1_BIDIMODE;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Set Bidirectional Simplex Receive Only Mode.
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The SPI peripheral is set for bidirectional transfers in two-wire simplex mode
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(using a clock wire and a bidirectional data wire), and is placed in a receive
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state.
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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*/
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void spi_set_bidirectional_receive_only_mode(uint32_t spi)
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{
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SPI_CR1(spi) |= SPI_CR1_BIDIMODE;
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SPI_CR1(spi) &= ~SPI_CR1_BIDIOE;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Set Bidirectional Simplex Receive Only Mode.
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The SPI peripheral is set for bidirectional transfers in two-wire simplex mode
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(using a clock wire and a bidirectional data wire), and is placed in a transmit
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state.
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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*/
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void spi_set_bidirectional_transmit_only_mode(uint32_t spi)
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{
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SPI_CR1(spi) |= SPI_CR1_BIDIMODE;
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SPI_CR1(spi) |= SPI_CR1_BIDIOE;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Enable the CRC.
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The SPI peripheral is set to use a CRC field for transmit and receive.
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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*/
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void spi_enable_crc(uint32_t spi)
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{
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SPI_CR1(spi) |= SPI_CR1_CRCEN;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Disable the CRC.
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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*/
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void spi_disable_crc(uint32_t spi)
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{
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SPI_CR1(spi) &= ~SPI_CR1_CRCEN;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Next Transmit is a Data Word
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The next transmission to take place is a data word from the transmit buffer.
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This must be called before transmission to distinguish between sending
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of a data or CRC word.
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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*/
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void spi_set_next_tx_from_buffer(uint32_t spi)
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{
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SPI_CR1(spi) &= ~SPI_CR1_CRCNEXT;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Next Transmit is a CRC Word
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The next transmission to take place is a crc word from the hardware crc unit.
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This must be called before transmission to distinguish between sending
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of a data or CRC word.
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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*/
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void spi_set_next_tx_from_crc(uint32_t spi)
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{
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SPI_CR1(spi) |= SPI_CR1_CRCNEXT;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Set Full Duplex (3-wire) Mode
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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*/
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void spi_set_full_duplex_mode(uint32_t spi)
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{
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SPI_CR1(spi) &= ~SPI_CR1_RXONLY;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Set Receive Only Mode for Simplex (2-wire) Unidirectional
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Transfers
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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*/
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void spi_set_receive_only_mode(uint32_t spi)
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{
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SPI_CR1(spi) |= SPI_CR1_RXONLY;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Enable Slave Management by Hardware
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In slave mode the NSS hardware input is used as a select enable for the slave.
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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*/
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void spi_disable_software_slave_management(uint32_t spi)
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{
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SPI_CR1(spi) &= ~SPI_CR1_SSM;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Enable Slave Management by Software
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In slave mode the NSS hardware input is replaced by an internal software
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enable/disable of the slave (@ref spi_set_nss_high).
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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*/
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void spi_enable_software_slave_management(uint32_t spi)
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{
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SPI_CR1(spi) |= SPI_CR1_SSM;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Set the Software NSS Signal High
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In slave mode, and only when software slave management is used, this replaces
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the NSS signal with a slave select enable signal.
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@todo these should perhaps be combined with an SSM enable as it is meaningless
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otherwise
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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*/
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void spi_set_nss_high(uint32_t spi)
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{
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SPI_CR1(spi) |= SPI_CR1_SSI;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Set the Software NSS Signal Low
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In slave mode, and only when software slave management is used, this replaces
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the NSS signal with a slave select disable signal.
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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*/
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void spi_set_nss_low(uint32_t spi)
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{
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SPI_CR1(spi) &= ~SPI_CR1_SSI;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Set to Send LSB First
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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*/
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void spi_send_lsb_first(uint32_t spi)
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{
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SPI_CR1(spi) |= SPI_CR1_LSBFIRST;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Set to Send MSB First
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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*/
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void spi_send_msb_first(uint32_t spi)
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{
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SPI_CR1(spi) &= ~SPI_CR1_LSBFIRST;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Set the Baudrate Prescaler
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@todo Why is this specification different to the spi_init_master baudrate
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values?
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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@param[in] baudrate Unsigned int8. Baudrate prescale value @ref spi_br_pre.
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*/
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void spi_set_baudrate_prescaler(uint32_t spi, uint8_t baudrate)
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{
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uint32_t reg32;
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if (baudrate > 7) {
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return;
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}
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reg32 = (SPI_CR1(spi) & 0xffc7); /* Clear bits [5:3]. */
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reg32 |= (baudrate << 3);
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SPI_CR1(spi) = reg32;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Set to Master Mode
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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*/
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void spi_set_master_mode(uint32_t spi)
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{
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SPI_CR1(spi) |= SPI_CR1_MSTR;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Set to Slave Mode
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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*/
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void spi_set_slave_mode(uint32_t spi)
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{
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SPI_CR1(spi) &= ~SPI_CR1_MSTR;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Set the Clock Polarity to High when Idle
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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*/
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void spi_set_clock_polarity_1(uint32_t spi)
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{
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SPI_CR1(spi) |= SPI_CR1_CPOL;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Set the Clock Polarity to Low when Idle
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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*/
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void spi_set_clock_polarity_0(uint32_t spi)
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{
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SPI_CR1(spi) &= ~SPI_CR1_CPOL;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief SPI Set the Clock Phase to Capture on Trailing Edge
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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|
*/
|
|
|
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void spi_set_clock_phase_1(uint32_t spi)
|
|
{
|
|
SPI_CR1(spi) |= SPI_CR1_CPHA;
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/** @brief SPI Set the Clock Phase to Capture on Leading Edge
|
|
|
|
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
|
|
*/
|
|
|
|
void spi_set_clock_phase_0(uint32_t spi)
|
|
{
|
|
SPI_CR1(spi) &= ~SPI_CR1_CPHA;
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/** @brief SPI Enable the Transmit Buffer Empty Interrupt
|
|
|
|
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
|
|
*/
|
|
|
|
void spi_enable_tx_buffer_empty_interrupt(uint32_t spi)
|
|
{
|
|
SPI_CR2(spi) |= SPI_CR2_TXEIE;
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/** @brief SPI Disable the Transmit Buffer Empty Interrupt
|
|
|
|
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
|
|
*/
|
|
|
|
void spi_disable_tx_buffer_empty_interrupt(uint32_t spi)
|
|
{
|
|
SPI_CR2(spi) &= ~SPI_CR2_TXEIE;
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/** @brief SPI Enable the Receive Buffer Ready Interrupt
|
|
|
|
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
|
|
*/
|
|
|
|
void spi_enable_rx_buffer_not_empty_interrupt(uint32_t spi)
|
|
{
|
|
SPI_CR2(spi) |= SPI_CR2_RXNEIE;
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/** @brief SPI Disable the Receive Buffer Ready Interrupt
|
|
|
|
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
|
|
*/
|
|
|
|
void spi_disable_rx_buffer_not_empty_interrupt(uint32_t spi)
|
|
{
|
|
SPI_CR2(spi) &= ~SPI_CR2_RXNEIE;
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/** @brief SPI Enable the Error Interrupt
|
|
|
|
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
|
|
*/
|
|
|
|
void spi_enable_error_interrupt(uint32_t spi)
|
|
{
|
|
SPI_CR2(spi) |= SPI_CR2_ERRIE;
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/** @brief SPI Disable the Error Interrupt
|
|
|
|
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
|
|
*/
|
|
|
|
void spi_disable_error_interrupt(uint32_t spi)
|
|
{
|
|
SPI_CR2(spi) &= ~SPI_CR2_ERRIE;
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/** @brief SPI Set the NSS Pin as an Output
|
|
|
|
Normally used in master mode to allows the master to place all devices on the
|
|
SPI bus into slave mode. Multimaster mode is not possible.
|
|
|
|
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
|
|
*/
|
|
|
|
void spi_enable_ss_output(uint32_t spi)
|
|
{
|
|
SPI_CR2(spi) |= SPI_CR2_SSOE;
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/** @brief SPI Set the NSS Pin as an Input
|
|
|
|
In master mode this allows the master to sense the presence of other masters. If
|
|
NSS is then pulled low the master is placed into slave mode. In slave mode NSS
|
|
becomes a slave enable.
|
|
|
|
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
|
|
*/
|
|
|
|
void spi_disable_ss_output(uint32_t spi)
|
|
{
|
|
SPI_CR2(spi) &= ~SPI_CR2_SSOE;
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/** @brief SPI Enable Transmit Transfers via DMA
|
|
|
|
This allows transmissions to proceed unattended using DMA to move data to the
|
|
transmit buffer as it becomes available. The DMA channels provided for each
|
|
SPI peripheral are given in the Technical Manual DMA section.
|
|
|
|
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
|
|
*/
|
|
|
|
void spi_enable_tx_dma(uint32_t spi)
|
|
{
|
|
SPI_CR2(spi) |= SPI_CR2_TXDMAEN;
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/** @brief SPI Disable Transmit Transfers via DMA
|
|
|
|
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
|
|
*/
|
|
|
|
void spi_disable_tx_dma(uint32_t spi)
|
|
{
|
|
SPI_CR2(spi) &= ~SPI_CR2_TXDMAEN;
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/** @brief SPI Enable Receive Transfers via DMA
|
|
|
|
This allows received data streams to proceed unattended using DMA to move data
|
|
from the receive buffer as data becomes available. The DMA channels provided
|
|
for each SPI peripheral are given in the Technical Manual DMA section.
|
|
|
|
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
|
|
*/
|
|
|
|
void spi_enable_rx_dma(uint32_t spi)
|
|
{
|
|
SPI_CR2(spi) |= SPI_CR2_RXDMAEN;
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/** @brief SPI Disable Receive Transfers via DMA
|
|
|
|
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
|
|
*/
|
|
|
|
void spi_disable_rx_dma(uint32_t spi)
|
|
{
|
|
SPI_CR2(spi) &= ~SPI_CR2_RXDMAEN;
|
|
}
|
|
|
|
/**@}*/
|