diff --git a/include/libopencm3/stm32/common/spi_common_all.h b/include/libopencm3/stm32/common/spi_common_all.h index fdde5b6e..6fc25599 100644 --- a/include/libopencm3/stm32/common/spi_common_all.h +++ b/include/libopencm3/stm32/common/spi_common_all.h @@ -129,33 +129,6 @@ specific memorymap.h header before including this header file.*/ /* CRCNEXT: Transmit CRC next */ #define SPI_CR1_CRCNEXT (1 << 12) -/* DFF: Data frame format */ -/****************************************************************************/ -/** @defgroup spi_dff SPI data frame format -@ingroup spi_defines - -@{*/ -#if defined(STM32F3) - -#define SPI_DR8(spi_base) MMIO8(spi_base + 0x0c) -#define SPI1_DR8 SPI_DR8(SPI1_BASE) -#define SPI2_DR8 SPI_DR8(SPI2_I2S_BASE) -#define SPI3_DR8 SPI_DR8(SPI3_I2S_BASE) - -#define SPI_CR1_CRCL_8BIT (0 << 11) -#define SPI_CR1_CRCL_16BIT (1 << 11) -/**@}*/ -#define SPI_CR1_CRCL (1 << 11) - -#elif !defined(STM32F3) - -#define SPI_CR1_DFF_8BIT (0 << 11) -#define SPI_CR1_DFF_16BIT (1 << 11) -/**@}*/ -#define SPI_CR1_DFF (1 << 11) - -#endif - /* RXONLY: Receive only */ #define SPI_CR1_RXONLY (1 << 10) @@ -235,41 +208,7 @@ specific memorymap.h header before including this header file.*/ /* --- SPI_CR2 values ------------------------------------------------------ */ -/* Bits [15:8]: Reserved. Forced to 0 by hardware. */ - -#if defined(STM32F3) - -/* LDMA_TX: Last DMA transfer for transmission */ -#define SPI_CR2_LDMA_TX (1 << 14) - -/* LDMA_RX: Last DMA transfer for reception */ -#define SPI_CR2_LDMA_RX (1 << 13) - -/* FRXTH: FIFO reception threshold */ -#define SPI_CR2_FRXTH (1 << 12) - -/* DS [3:0]: Data size */ -// 0x0 - 0x2 NOT USED -#define SPI_CR2_DS_4BIT (0x3 << 8) -#define SPI_CR2_DS_5BIT (0x4 << 8) -#define SPI_CR2_DS_6BIT (0x5 << 8) -#define SPI_CR2_DS_7BIT (0x6 << 8) -#define SPI_CR2_DS_8BIT (0x7 << 8) -#define SPI_CR2_DS_9BIT (0x8 << 8) -#define SPI_CR2_DS_10BIT (0x9 << 8) -#define SPI_CR2_DS_11BIT (0xA << 8) -#define SPI_CR2_DS_12BIT (0xB << 8) -#define SPI_CR2_DS_13BIT (0xC << 8) -#define SPI_CR2_DS_14BIT (0xD << 8) -#define SPI_CR2_DS_15BIT (0xE << 8) -#define SPI_CR2_DS_16BIT (0xF << 8) -#define SPI_CR2_DS_MASK (0xF << 8) - - -/* NSSP: NSS pulse management */ -#define SPI_CR2_NSSP (1 << 3) - -#endif +/* Bits [15:8]: Reserved. Forced to 0 by hardware. Used on F3. */ /* TXEIE: Tx buffer empty interrupt enable */ #define SPI_CR2_TXEIE (1 << 7) @@ -294,23 +233,7 @@ specific memorymap.h header before including this header file.*/ /* --- SPI_SR values ------------------------------------------------------- */ -/* Bits [15:8]: Reserved. Forced to 0 by hardware. */ - -#if defined(STM32F3) - -/* FTLVL[1:0]: FIFO Transmission Level */ -#define SPI_SR_FTLVL_FIFO_EMPTY (0x0 << 11) -#define SPI_SR_FTLVL_QUARTER_FIFO (0x1 << 11) -#define SPI_SR_FTLVL_HALF_FIFO (0x2 << 11) -#define SPI_SR_FTLVL_FIFO_FULL (0x3 << 11) - -/* FRLVL[1:0]: FIFO Reception Level */ -#define SPI_SR_FRLVL_FIFO_EMPTY (0x0 << 9) -#define SPI_SR_FRLVL_QUARTER_FIFO (0x1 << 9) -#define SPI_SR_FRLVL_HALF_FIFO (0x2 << 9) -#define SPI_SR_FRLVL_FIFO_FULL (0x3 << 9) - -#endif +/* Bits [15:8]: Reserved. Forced to 0 by hardware. Used on F3. */ /* BSY: Busy flag */ #define SPI_SR_BSY (1 << 7) @@ -469,16 +392,6 @@ void spi_disable_tx_dma(uint32_t spi); void spi_enable_rx_dma(uint32_t spi); void spi_disable_rx_dma(uint32_t spi); -#ifdef STM32F3 -void spi_set_data_size(uint32_t spi, uint16_t data_s); -void spi_fifo_reception_threshold_8bit(uint32_t spi); -void spi_fifo_reception_threshold_16bit(uint32_t spi); -void spi_i2s_mode_spi_mode(uint32_t spi); -void spi_send8(uint32_t spi, uint8_t data); -uint8_t spi_read8(uint32_t spi); - -#endif - END_DECLS /**@}*/ diff --git a/include/libopencm3/stm32/common/spi_common_f0124.h b/include/libopencm3/stm32/common/spi_common_f0124.h new file mode 100644 index 00000000..6af5486d --- /dev/null +++ b/include/libopencm3/stm32/common/spi_common_f0124.h @@ -0,0 +1,65 @@ +/** @addtogroup spi_defines + +@author @htmlonly © @endhtmlonly 2011 Fergus Noble + +*/ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Fergus Noble + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA SPI.H +The order of header inclusion is important. spi.h includes the device +specific memorymap.h header before including this header file.*/ + +/** @cond */ +#ifdef LIBOPENCM3_SPI_H +/** @endcond */ +#ifndef LIBOPENCM3_SPI_COMMON_F0124_H +#define LIBOPENCM3_SPI_COMMON_F0124_H + +/**@{*/ + +#include + +/* + * This file extends the common STM32 version with definitions only + * applicable to the STM32F0/1/2/4 series of devices. + */ + +/* DFF: Data frame format */ +/****************************************************************************/ +/** @defgroup spi_dff SPI data frame format +@ingroup spi_defines + +@{*/ + +#define SPI_CR1_DFF_8BIT (0 << 11) +#define SPI_CR1_DFF_16BIT (1 << 11) + +/**@}*/ + +#define SPI_CR1_DFF (1 << 11) + +#endif +/** @cond */ +#else +#warning "spi_common_f24.h should not be included explicitly, only via spi.h" +#endif +/** @endcond */ +/**@}*/ + diff --git a/include/libopencm3/stm32/common/spi_common_f24.h b/include/libopencm3/stm32/common/spi_common_f24.h index 2fc45ed9..43613ae8 100644 --- a/include/libopencm3/stm32/common/spi_common_f24.h +++ b/include/libopencm3/stm32/common/spi_common_f24.h @@ -34,7 +34,7 @@ specific memorymap.h header before including this header file.*/ /**@{*/ -#include +#include /* * This file extends the common STM32 version with definitions only diff --git a/include/libopencm3/stm32/f1/spi.h b/include/libopencm3/stm32/f1/spi.h index d2fe7c26..24022442 100644 --- a/include/libopencm3/stm32/f1/spi.h +++ b/include/libopencm3/stm32/f1/spi.h @@ -32,7 +32,7 @@ LGPL License Terms @ref lgpl_license #define LIBOPENCM3_SPI_H #include -#include +#include #endif diff --git a/include/libopencm3/stm32/f3/spi.h b/include/libopencm3/stm32/f3/spi.h index 2581b7e2..e4bbf277 100644 --- a/include/libopencm3/stm32/f3/spi.h +++ b/include/libopencm3/stm32/f3/spi.h @@ -32,7 +32,81 @@ LGPL License Terms @ref lgpl_license #define LIBOPENCM3_SPI_H #include -#include +#include -#endif +/* DFF: Data frame format */ +/****************************************************************************/ +/** @defgroup spi_dff SPI data frame format +@ingroup spi_defines +@{*/ + +#define SPI_DR8(spi_base) MMIO8(spi_base + 0x0c) +#define SPI1_DR8 SPI_DR8(SPI1_BASE) +#define SPI2_DR8 SPI_DR8(SPI2_I2S_BASE) +#define SPI3_DR8 SPI_DR8(SPI3_I2S_BASE) + +#define SPI_CR1_CRCL_8BIT (0 << 11) +#define SPI_CR1_CRCL_16BIT (1 << 11) +/**@}*/ +#define SPI_CR1_CRCL (1 << 11) + +/* --- SPI_CR2 values ------------------------------------------------------ */ + +/* LDMA_TX: Last DMA transfer for transmission */ +#define SPI_CR2_LDMA_TX (1 << 14) + +/* LDMA_RX: Last DMA transfer for reception */ +#define SPI_CR2_LDMA_RX (1 << 13) + +/* FRXTH: FIFO reception threshold */ +#define SPI_CR2_FRXTH (1 << 12) + +/* DS [3:0]: Data size */ +// 0x0 - 0x2 NOT USED +#define SPI_CR2_DS_4BIT (0x3 << 8) +#define SPI_CR2_DS_5BIT (0x4 << 8) +#define SPI_CR2_DS_6BIT (0x5 << 8) +#define SPI_CR2_DS_7BIT (0x6 << 8) +#define SPI_CR2_DS_8BIT (0x7 << 8) +#define SPI_CR2_DS_9BIT (0x8 << 8) +#define SPI_CR2_DS_10BIT (0x9 << 8) +#define SPI_CR2_DS_11BIT (0xA << 8) +#define SPI_CR2_DS_12BIT (0xB << 8) +#define SPI_CR2_DS_13BIT (0xC << 8) +#define SPI_CR2_DS_14BIT (0xD << 8) +#define SPI_CR2_DS_15BIT (0xE << 8) +#define SPI_CR2_DS_16BIT (0xF << 8) +#define SPI_CR2_DS_MASK (0xF << 8) + +/* NSSP: NSS pulse management */ +#define SPI_CR2_NSSP (1 << 3) + +/* --- SPI_SR values ------------------------------------------------------- */ + +/* FTLVL[1:0]: FIFO Transmission Level */ +#define SPI_SR_FTLVL_FIFO_EMPTY (0x0 << 11) +#define SPI_SR_FTLVL_QUARTER_FIFO (0x1 << 11) +#define SPI_SR_FTLVL_HALF_FIFO (0x2 << 11) +#define SPI_SR_FTLVL_FIFO_FULL (0x3 << 11) + +/* FRLVL[1:0]: FIFO Reception Level */ +#define SPI_SR_FRLVL_FIFO_EMPTY (0x0 << 9) +#define SPI_SR_FRLVL_QUARTER_FIFO (0x1 << 9) +#define SPI_SR_FRLVL_HALF_FIFO (0x2 << 9) +#define SPI_SR_FRLVL_FIFO_FULL (0x3 << 9) + +/* --- Function prototypes ------------------------------------------------- */ + +BEGIN_DECLS + +void spi_set_data_size(uint32_t spi, uint16_t data_s); +void spi_fifo_reception_threshold_8bit(uint32_t spi); +void spi_fifo_reception_threshold_16bit(uint32_t spi); +void spi_i2s_mode_spi_mode(uint32_t spi); +void spi_send8(uint32_t spi, uint8_t data); +uint8_t spi_read8(uint32_t spi); + +END_DECLS + +#endif \ No newline at end of file diff --git a/lib/stm32/common/spi_common_all.c b/lib/stm32/common/spi_common_all.c index a3abb78a..762558c3 100644 --- a/lib/stm32/common/spi_common_all.c +++ b/lib/stm32/common/spi_common_all.c @@ -99,53 +99,6 @@ void spi_reset(uint32_t spi_peripheral) } } -/*---------------------------------------------------------------------------*/ -/** @brief Configure the SPI as Master. - -The SPI peripheral is configured as a master with communication parameters -baudrate, data format 8/16 bits, frame format lsb/msb first, clock polarity -and phase. The SPI enable, CRC enable and CRC next controls are not affected. -These must be controlled separately. - -@todo NSS pin handling. - -@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. -@param[in] br Unsigned int32. Baudrate @ref spi_baudrate. -@param[in] cpol Unsigned int32. Clock polarity @ref spi_cpol. -@param[in] cpha Unsigned int32. Clock Phase @ref spi_cpha. -@param[in] dff Unsigned int32. Data frame format 8/16 bits @ref spi_dff. -@param[in] lsbfirst Unsigned int32. Frame format lsb/msb first @ref -spi_lsbfirst. -@returns int. Error code. -*/ - -#ifndef STM32F3 - -int spi_init_master(uint32_t spi, uint32_t br, uint32_t cpol, uint32_t cpha, - uint32_t dff, uint32_t lsbfirst) -{ - uint32_t reg32 = SPI_CR1(spi); - - /* Reset all bits omitting SPE, CRCEN and CRCNEXT bits. */ - reg32 &= SPI_CR1_SPE | SPI_CR1_CRCEN | SPI_CR1_CRCNEXT; - - reg32 |= SPI_CR1_MSTR; /* Configure SPI as master. */ - - reg32 |= br; /* Set baud rate bits. */ - reg32 |= cpol; /* Set CPOL value. */ - reg32 |= cpha; /* Set CPHA value. */ - reg32 |= dff; /* Set data format (8 or 16 bits). */ - reg32 |= lsbfirst; /* Set frame format (LSB- or MSB-first). */ - - /* TODO: NSS pin handling. */ - - SPI_CR1(spi) = reg32; - - return 0; /* TODO */ -} - -#endif - /* TODO: Error handling? */ /*---------------------------------------------------------------------------*/ /** @brief SPI Enable. @@ -398,72 +351,6 @@ void spi_set_next_tx_from_crc(uint32_t spi) SPI_CR1(spi) |= SPI_CR1_CRCNEXT; } -#ifdef STM32F3 - -void spi_send8(uint32_t spi, uint8_t data) -{ - /* Wait for transfer finished. */ - while (!(SPI_SR(spi) & SPI_SR_TXE)); - - /* Write data (8 or 16 bits, depending on DFF) into DR. */ - SPI_DR8(spi) = data; -} - -uint8_t spi_read8(uint32_t spi) -{ - /* Wait for transfer finished. */ - while (!(SPI_SR(spi) & SPI_SR_RXNE)); - - /* Read the data (8 or 16 bits, depending on DFF bit) from DR. */ - return SPI_DR8(spi); -} - -void spi_set_data_size(uint32_t spi, uint16_t data_s) -{ - SPI_CR2(spi) = (SPI_CR2(spi) & ~SPI_CR2_DS_MASK) | (data_s & SPI_CR2_DS_MASK); -} - -void spi_fifo_reception_threshold_8bit(uint32_t spi) -{ - SPI_CR2(spi) |= SPI_CR2_FRXTH; -} - -void spi_fifo_reception_threshold_16bit(uint32_t spi) -{ - SPI_CR2(spi) &= ~SPI_CR2_FRXTH; -} - -void spi_i2s_mode_spi_mode(uint32_t spi) -{ - SPI_I2SCFGR(spi) &= ~SPI_I2SCFGR_I2SMOD; -} - -#else /*STM32F3*/ - -/*---------------------------------------------------------------------------*/ -/** @brief SPI Set Data Frame Format to 8 bits - -@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. -*/ - -void spi_set_dff_8bit(uint32_t spi) -{ - SPI_CR1(spi) &= ~SPI_CR1_DFF; -} - -/*---------------------------------------------------------------------------*/ -/** @brief SPI Set Data Frame Format to 16 bits - -@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. -*/ - -void spi_set_dff_16bit(uint32_t spi) -{ - SPI_CR1(spi) |= SPI_CR1_DFF; -} - -#endif - /*---------------------------------------------------------------------------*/ /** @brief SPI Set Full Duplex (3-wire) Mode diff --git a/lib/stm32/common/spi_common_f0124.c b/lib/stm32/common/spi_common_f0124.c new file mode 100644 index 00000000..6345350f --- /dev/null +++ b/lib/stm32/common/spi_common_f0124.c @@ -0,0 +1,137 @@ +/** @addtogroup spi_file + +@author @htmlonly © @endhtmlonly 2009 +Uwe Hermann +@author @htmlonly © @endhtmlonly 2012 +Ken Sarkies + +Devices can have up to three SPI peripherals. The common 4-wire full-duplex +mode of operation is supported, along with 3-wire variants using unidirectional +communication modes or half-duplex bidirectional communication. A variety of +options allows many of the SPI variants to be supported. Multimaster operation +is also supported. A CRC can be generated and checked in hardware. + +@note Some JTAG pins need to be remapped if SPI is to be used. + +@note The I2S protocol shares the SPI hardware so the two protocols cannot be +used at the same time on the same peripheral. + +Example: 1Mbps, positive clock polarity, leading edge trigger, 8-bit words, +LSB first. +@code + spi_init_master(SPI1, 1000000, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE, + SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT, + SPI_CR1_LSBFIRST); + spi_write(SPI1, 0x55); // 8-bit write + spi_write(SPI1, 0xaa88); // 16-bit write + reg8 = spi_read(SPI1); // 8-bit read + reg16 = spi_read(SPI1); // 16-bit read +@endcode + +@todo need additional functions to aid ISRs in retrieving status + +*/ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + +/* + * SPI and I2S code. + * + * Examples: + * spi_init_master(SPI1, 1000000, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE, + * SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT, + * SPI_CR1_LSBFIRST); + * spi_write(SPI1, 0x55); // 8-bit write + * spi_write(SPI1, 0xaa88); // 16-bit write + * reg8 = spi_read(SPI1); // 8-bit read + * reg16 = spi_read(SPI1); // 16-bit read + */ + +/**@{*/ + +/*---------------------------------------------------------------------------*/ +/** @brief Configure the SPI as Master. + +The SPI peripheral is configured as a master with communication parameters +baudrate, data format 8/16 bits, frame format lsb/msb first, clock polarity +and phase. The SPI enable, CRC enable and CRC next controls are not affected. +These must be controlled separately. + +@todo NSS pin handling. + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +@param[in] br Unsigned int32. Baudrate @ref spi_baudrate. +@param[in] cpol Unsigned int32. Clock polarity @ref spi_cpol. +@param[in] cpha Unsigned int32. Clock Phase @ref spi_cpha. +@param[in] dff Unsigned int32. Data frame format 8/16 bits @ref spi_dff. +@param[in] lsbfirst Unsigned int32. Frame format lsb/msb first @ref +spi_lsbfirst. +@returns int. Error code. +*/ + +int spi_init_master(uint32_t spi, uint32_t br, uint32_t cpol, uint32_t cpha, + uint32_t dff, uint32_t lsbfirst) +{ + uint32_t reg32 = SPI_CR1(spi); + + /* Reset all bits omitting SPE, CRCEN and CRCNEXT bits. */ + reg32 &= SPI_CR1_SPE | SPI_CR1_CRCEN | SPI_CR1_CRCNEXT; + + reg32 |= SPI_CR1_MSTR; /* Configure SPI as master. */ + + reg32 |= br; /* Set baud rate bits. */ + reg32 |= cpol; /* Set CPOL value. */ + reg32 |= cpha; /* Set CPHA value. */ + reg32 |= dff; /* Set data format (8 or 16 bits). */ + reg32 |= lsbfirst; /* Set frame format (LSB- or MSB-first). */ + + /* TODO: NSS pin handling. */ + + SPI_CR1(spi) = reg32; + + return 0; /* TODO */ +} + +/*---------------------------------------------------------------------------*/ +/** @brief SPI Set Data Frame Format to 8 bits + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + +void spi_set_dff_8bit(uint32_t spi) +{ + SPI_CR1(spi) &= ~SPI_CR1_DFF; +} + +/*---------------------------------------------------------------------------*/ +/** @brief SPI Set Data Frame Format to 16 bits + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + +void spi_set_dff_16bit(uint32_t spi) +{ + SPI_CR1(spi) |= SPI_CR1_DFF; +} + +/**@}*/ diff --git a/lib/stm32/f1/Makefile b/lib/stm32/f1/Makefile index f71ab8dc..b98082c2 100644 --- a/lib/stm32/f1/Makefile +++ b/lib/stm32/f1/Makefile @@ -38,7 +38,7 @@ OBJS = adc.o can.o desig.o exti.o ethernet.o flash.o gpio.o \ OBJS += crc_common_all.o dac_common_all.o dma_common_f13.o \ gpio_common_all.o i2c_common_all.o iwdg_common_all.o \ - pwr_common_all.o spi_common_all.o \ + pwr_common_all.o spi_common_all.o spi_common_f0124.o \ timer_common_all.o usart_common_all.o OBJS += usb.o usb_control.o usb_standard.o usb_f103.o usb_f107.o \ diff --git a/lib/stm32/f2/Makefile b/lib/stm32/f2/Makefile index 725b9427..8b6de07b 100644 --- a/lib/stm32/f2/Makefile +++ b/lib/stm32/f2/Makefile @@ -38,9 +38,9 @@ OBJS = gpio.o exti2.o rcc.o OBJS += crc_common_all.o dac_common_all.o dma_common_f24.o \ gpio_common_all.o gpio_common_f234.o i2c_common_all.o \ iwdg_common_all.o rtc_common_bcd.o spi_common_all.o \ - timer_common_all.o timer_common_f24.o usart_common_all.o \ - flash_common_f234.o flash_common_f24.o hash_common_f24.o \ - crypto_common_f24.o + spi_common_f0124.o timer_common_all.o timer_common_f24.o \ + usart_common_all.o flash_common_f234.o flash_common_f24.o \ + hash_common_f24.o crypto_common_f24.o VPATH += ../../usb:../:../../cm3:../common diff --git a/lib/stm32/f3/Makefile b/lib/stm32/f3/Makefile index e0f85a58..72117820 100644 --- a/lib/stm32/f3/Makefile +++ b/lib/stm32/f3/Makefile @@ -34,7 +34,7 @@ CFLAGS = -Os -g \ # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = rcc.o gpio.o adc.o exti2.o i2c.o +OBJS = rcc.o gpio.o adc.o exti2.o i2c.o spi.o OBJS += gpio_common_all.o gpio_common_f234.o \ dac_common_all.o usart_common_all.o crc_common_all.o\ diff --git a/lib/stm32/f3/spi.c b/lib/stm32/f3/spi.c new file mode 100644 index 00000000..8207592b --- /dev/null +++ b/lib/stm32/f3/spi.c @@ -0,0 +1,60 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + +void spi_send8(uint32_t spi, uint8_t data) +{ + /* Wait for transfer finished. */ + while (!(SPI_SR(spi) & SPI_SR_TXE)); + + /* Write data (8 or 16 bits, depending on DFF) into DR. */ + SPI_DR8(spi) = data; +} + +uint8_t spi_read8(uint32_t spi) +{ + /* Wait for transfer finished. */ + while (!(SPI_SR(spi) & SPI_SR_RXNE)); + + /* Read the data (8 or 16 bits, depending on DFF bit) from DR. */ + return SPI_DR8(spi); +} + +void spi_set_data_size(uint32_t spi, uint16_t data_s) +{ + SPI_CR2(spi) = (SPI_CR2(spi) & ~SPI_CR2_DS_MASK) | + (data_s & SPI_CR2_DS_MASK); +} + +void spi_fifo_reception_threshold_8bit(uint32_t spi) +{ + SPI_CR2(spi) |= SPI_CR2_FRXTH; +} + +void spi_fifo_reception_threshold_16bit(uint32_t spi) +{ + SPI_CR2(spi) &= ~SPI_CR2_FRXTH; +} + +void spi_i2s_mode_spi_mode(uint32_t spi) +{ + SPI_I2SCFGR(spi) &= ~SPI_I2SCFGR_I2SMOD; +} \ No newline at end of file diff --git a/lib/stm32/f4/Makefile b/lib/stm32/f4/Makefile index f47c2c8c..936b0bb2 100644 --- a/lib/stm32/f4/Makefile +++ b/lib/stm32/f4/Makefile @@ -39,9 +39,9 @@ OBJS = adc.o can.o gpio.o exti2.o pwr.o rcc.o rtc.o crypto.o OBJS += crc_common_all.o dac_common_all.o dma_common_f24.o \ gpio_common_all.o gpio_common_f234.o i2c_common_all.o \ iwdg_common_all.o pwr_common_all.o rtc_common_bcd.o \ - spi_common_all.o timer_common_all.o timer_common_f24.o \ - usart_common_all.o flash_common_f234.o flash_common_f24.o \ - hash_common_f24.o crypto_common_f24.o + spi_common_all.o spi_common_f0124.o timer_common_all.o \ + timer_common_f24.o usart_common_all.o flash_common_f234.o \ + flash_common_f24.o hash_common_f24.o crypto_common_f24.o OBJS += usb.o usb_standard.o usb_control.o usb_fx07_common.o \ usb_f107.o usb_f207.o diff --git a/locm3.sublime-project b/locm3.sublime-project index 865f7db1..19e61279 100644 --- a/locm3.sublime-project +++ b/locm3.sublime-project @@ -20,7 +20,8 @@ "settings": { "tab_size": 8, - "translate_tabs_to_spaces": false + "translate_tabs_to_spaces": false, + "rulers": [80] }, "build_systems": [