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cm3: extract Coresight LSR/LAR definitions 

Use a single point of definition for the offset, and add it where it was
missing.
This commit is contained in:
Karl Palsson 2019-10-18 22:29:13 +00:00
parent d8579dde95
commit 3ebd71b464
6 changed files with 30 additions and 12 deletions
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6
include/libopencm3/cm3/dwt.h
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@ -52,6 +52,12 @@
#define DWT_MASK(n) MMIO32(DWT_BASE + 0x24 + (n) * 16) #define DWT_MASK(n) MMIO32(DWT_BASE + 0x24 + (n) * 16)
#define DWT_FUNCTION(n) MMIO32(DWT_BASE + 0x28 + (n) * 16) #define DWT_FUNCTION(n) MMIO32(DWT_BASE + 0x28 + (n) * 16)
/* CoreSight Lock Status Register for this peripheral */
#define DWT_LSR MMIO32(DWT_BASE + CORESIGHT_LSR_OFFSET)
/* CoreSight Lock Access Register for this peripheral */
#define DWT_LAR MMIO32(DWT_BASE + CORESIGHT_LAR_OFFSET)
/*****************************************************************************/ /*****************************************************************************/
/* Register values */ /* Register values */
/*****************************************************************************/ /*****************************************************************************/

4
include/libopencm3/cm3/fpb.h
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@ -45,9 +45,9 @@
#define FPB_COMP (&MMIO32(FPB_BASE + 8)) #define FPB_COMP (&MMIO32(FPB_BASE + 8))
/* CoreSight Lock Status Register for this peripheral */ /* CoreSight Lock Status Register for this peripheral */
#define FPB_LSR MMIO32(FPB_BASE + 0xFB4) #define FPB_LSR MMIO32(FPB_BASE + CORESIGHT_LSR_OFFSET)
/* CoreSight Lock Access Register for this peripheral */ /* CoreSight Lock Access Register for this peripheral */
#define FPB_LAR MMIO32(FPB_BASE + 0xFB0) #define FPB_LAR MMIO32(FPB_BASE + CORESIGHT_LAR_OFFSET)
/* TODO: PID, CID */ /* TODO: PID, CID */

4
include/libopencm3/cm3/itm.h
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@ -48,9 +48,9 @@
#define ITM_TCR MMIO32(ITM_BASE + 0xE80) #define ITM_TCR MMIO32(ITM_BASE + 0xE80)
/* CoreSight Lock Status Register for this peripheral */ /* CoreSight Lock Status Register for this peripheral */
#define ITM_LSR MMIO32(ITM_BASE + 0xFB4) #define ITM_LSR MMIO32(ITM_BASE + CORESIGHT_LSR_OFFSET)
/* CoreSight Lock Access Register for this peripheral */ /* CoreSight Lock Access Register for this peripheral */
#define ITM_LAR MMIO32(ITM_BASE + 0xFB0) #define ITM_LAR MMIO32(ITM_BASE + CORESIGHT_LAR_OFFSET)
/* TODO: PID, CID */ /* TODO: PID, CID */

18
include/libopencm3/cm3/memorymap.h
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@ -82,4 +82,22 @@
#define ID_BASE (SCS_BASE + 0x0FD0) #define ID_BASE (SCS_BASE + 0x0FD0)
#endif #endif
/**
* @defgroup coresight_registers Coresight Registers
* @{
* CoreSight Lock Status Registers and Lock Access Registers are
* documented for the DWT, ITM, FPB and TPIU peripherals
*/
#define CORESIGHT_LSR_OFFSET 0xfb4
#define CORESIGHT_LAR_OFFSET 0xfb0
/** CoreSight Lock Status Register lock status bit */
#define CORESIGHT_LSR_SLK (1<<1)
/** CoreSight Lock Status Register lock availability bit */
#define CORESIGHT_LSR_SLI (1<<0)
/** CoreSight Lock Access key, common for all */
#define CORESIGHT_LAR_KEY 0xC5ACCE55
/**@}*/
#endif #endif

6
include/libopencm3/cm3/scs.h
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@ -334,12 +334,6 @@
*/ */
#define SCS_DWT_CTRL_CYCCNTENA (BIT0) #define SCS_DWT_CTRL_CYCCNTENA (BIT0)
/* CoreSight Lock Status Register lock status bit */
#define SCS_LSR_SLK (1<<1)
/* CoreSight Lock Status Register lock availability bit */
#define SCS_LSR_SLI (1<<0)
/* CoreSight Lock Access key, common for all */
#define SCS_LAR_KEY 0xC5ACCE55
/**@}*/ /**@}*/
#endif #endif

4
include/libopencm3/cm3/tpiu.h
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@ -55,9 +55,9 @@
#define TPIU_DEVID MMIO32(TPIU_BASE + 0xFC8) #define TPIU_DEVID MMIO32(TPIU_BASE + 0xFC8)
/* CoreSight Lock Status Register for this peripheral */ /* CoreSight Lock Status Register for this peripheral */
#define TPIU_LSR MMIO32(TPIU_BASE + 0xFB4) #define TPIU_LSR MMIO32(TPIU_BASE + CORESIGHT_LSR_OFFSET)
/* CoreSight Lock Access Register for this peripheral */ /* CoreSight Lock Access Register for this peripheral */
#define TPIU_LAR MMIO32(TPIU_BASE + 0xFB0) #define TPIU_LAR MMIO32(TPIU_BASE + CORESIGHT_LAR_OFFSET)
/* TODO: PID, CID */ /* TODO: PID, CID */