diff --git a/include/libopencm3/cm3/dwt.h b/include/libopencm3/cm3/dwt.h
index 73b5291e..2718afa7 100644
--- a/include/libopencm3/cm3/dwt.h
+++ b/include/libopencm3/cm3/dwt.h
@@ -52,6 +52,12 @@
 #define DWT_MASK(n)			MMIO32(DWT_BASE + 0x24 + (n) * 16)
 #define DWT_FUNCTION(n)			MMIO32(DWT_BASE + 0x28 + (n) * 16)
 
+/* CoreSight Lock Status Register for this peripheral */
+#define DWT_LSR			MMIO32(DWT_BASE + CORESIGHT_LSR_OFFSET)
+/* CoreSight Lock Access Register for this peripheral */
+#define DWT_LAR			MMIO32(DWT_BASE + CORESIGHT_LAR_OFFSET)
+
+
 /*****************************************************************************/
 /* Register values                                                           */
 /*****************************************************************************/
diff --git a/include/libopencm3/cm3/fpb.h b/include/libopencm3/cm3/fpb.h
index e7527fcc..d2f65055 100644
--- a/include/libopencm3/cm3/fpb.h
+++ b/include/libopencm3/cm3/fpb.h
@@ -45,9 +45,9 @@
 #define FPB_COMP			(&MMIO32(FPB_BASE + 8))
 
 /* CoreSight Lock Status Register for this peripheral */
-#define FPB_LSR				MMIO32(FPB_BASE + 0xFB4)
+#define FPB_LSR				MMIO32(FPB_BASE + CORESIGHT_LSR_OFFSET)
 /* CoreSight Lock Access Register for this peripheral */
-#define FPB_LAR				MMIO32(FPB_BASE + 0xFB0)
+#define FPB_LAR				MMIO32(FPB_BASE + CORESIGHT_LAR_OFFSET)
 
 
 /* TODO: PID, CID */
diff --git a/include/libopencm3/cm3/itm.h b/include/libopencm3/cm3/itm.h
index ac5dbbd9..dc711a0e 100644
--- a/include/libopencm3/cm3/itm.h
+++ b/include/libopencm3/cm3/itm.h
@@ -48,9 +48,9 @@
 #define ITM_TCR				MMIO32(ITM_BASE + 0xE80)
 
 /* CoreSight Lock Status Register for this peripheral */
-#define ITM_LSR			MMIO32(ITM_BASE + 0xFB4)
+#define ITM_LSR			MMIO32(ITM_BASE + CORESIGHT_LSR_OFFSET)
 /* CoreSight Lock Access Register for this peripheral */
-#define ITM_LAR			MMIO32(ITM_BASE + 0xFB0)
+#define ITM_LAR			MMIO32(ITM_BASE + CORESIGHT_LAR_OFFSET)
 
 /* TODO: PID, CID */
 
diff --git a/include/libopencm3/cm3/memorymap.h b/include/libopencm3/cm3/memorymap.h
index 55cec86a..954328ab 100644
--- a/include/libopencm3/cm3/memorymap.h
+++ b/include/libopencm3/cm3/memorymap.h
@@ -82,4 +82,22 @@
 #define ID_BASE                         (SCS_BASE + 0x0FD0)
 #endif
 
+/**
+ * @defgroup coresight_registers Coresight Registers
+ * @{
+ * CoreSight Lock Status Registers and Lock Access Registers are
+ * documented for the DWT, ITM, FPB and TPIU peripherals
+ */
+#define CORESIGHT_LSR_OFFSET	0xfb4
+#define CORESIGHT_LAR_OFFSET	0xfb0
+
+/** CoreSight Lock Status Register lock status bit */
+#define CORESIGHT_LSR_SLK		(1<<1)
+/** CoreSight Lock Status Register lock availability bit */
+#define CORESIGHT_LSR_SLI		(1<<0)
+/** CoreSight Lock Access key, common for all */
+#define CORESIGHT_LAR_KEY		0xC5ACCE55
+
+/**@}*/
+
 #endif
diff --git a/include/libopencm3/cm3/scs.h b/include/libopencm3/cm3/scs.h
index cb0a6ddb..82b7bee3 100644
--- a/include/libopencm3/cm3/scs.h
+++ b/include/libopencm3/cm3/scs.h
@@ -334,12 +334,6 @@
  */
 #define SCS_DWT_CTRL_CYCCNTENA	(BIT0)
 
-/* CoreSight Lock Status Register lock status bit */
-#define SCS_LSR_SLK		(1<<1)
-/* CoreSight Lock Status Register lock availability bit */
-#define SCS_LSR_SLI		(1<<0)
-/* CoreSight Lock Access key, common for all */
-#define SCS_LAR_KEY		0xC5ACCE55
 
 /**@}*/
 #endif
diff --git a/include/libopencm3/cm3/tpiu.h b/include/libopencm3/cm3/tpiu.h
index 74428ba3..7b77af14 100644
--- a/include/libopencm3/cm3/tpiu.h
+++ b/include/libopencm3/cm3/tpiu.h
@@ -55,9 +55,9 @@
 #define TPIU_DEVID			MMIO32(TPIU_BASE + 0xFC8)
 
 /* CoreSight Lock Status Register for this peripheral */
-#define TPIU_LSR			MMIO32(TPIU_BASE + 0xFB4)
+#define TPIU_LSR			MMIO32(TPIU_BASE + CORESIGHT_LSR_OFFSET)
 /* CoreSight Lock Access Register for this peripheral */
-#define TPIU_LAR			MMIO32(TPIU_BASE + 0xFB0)
+#define TPIU_LAR			MMIO32(TPIU_BASE + CORESIGHT_LAR_OFFSET)
 
 /* TODO: PID, CID */