Move inband-signaling-usb documentation to UserManual
Change-Id: I4d6ef1f54f3d6c5a73ce00dc4640bd698f96842b
This commit is contained in:
parent
68a78099a0
commit
7758542087
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@ -1,314 +0,0 @@
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This file specifies the format of USB packets used for in-band data
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transmission and signaling on the USRP. All packets are 512-byte long,
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and are transfered using USB "bulk" transfers.
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IN packets are sent towards the host.
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OUT packets are sent away from the host.
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The layout is 32-bits wide. All data is transmitted in little-endian
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format across the USB.
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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|O|U|D|S|E| RSSI | Chan | mbz | Tag | Payload Len |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Timestamp |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| |
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+ +
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| Payload |
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. .
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. .
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. .
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| |
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+ +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| ... | .
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+-+-+-+-+-+-+-+ .
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. .
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. Padding .
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. .
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| |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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mbz Must be Zero: these bits must be zero in both IN and OUT packets.
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O Overrun Flag: set in an IN packet if an overrun condition was
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detected. Must be zero in OUT packets. Overrun occurs when
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the FPGA has data to transmit to the host and there is no
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buffer space available. This generally indicates a problem on
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the host. Either it is not keeping up, or it has configured
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the FPGA to transmit data at a higher rate than the transport
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(USB) can support.
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U Underrun Flag: set in an IN packet if an underrun condition
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was detected. Must be zero in OUT packets. Underrun occurs
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when the FPGA runs out of samples, and it's not between
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bursts. See the "End of Burst flag" below.
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D Dropped Packet Flag: Set in an IN packet if the FPGA
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discarded an OUT packet because its timestamp had already
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passed.
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S Start of Burst Flag: Set in an OUT packet if the data is the
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first segment of what is logically a continuous burst of data.
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Must be zero in IN packets.
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E End of Burst Flag: Set in an OUT packet if the data is the
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last segment of what is logically a continuous burst of data.
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Must be zero in IN packets. Underruns are not reported
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when the FPGA runs out of samples between bursts.
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RSSI 6-bit Received Strength Signal Indicator: Must be zero in OUT
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packets. In IN packets, indicates RSSI as reported by front end.
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FIXME The format and interpretation are to be determined.
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Chan 5-bit logical channel number. Channel number 0x1f is reserved
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for control information. See "Control Channel" below. Other
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channels are "data channels." Each data channel is logically
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independent of the others. A data channel payload field
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contains a sequence of homogeneous samples. The format of the
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samples is determined by the configuration associated with the
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given channel. It is often the case that the payload field
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contains 32-bit complex samples, each containing 16-bit real
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and imaginary components.
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Tag 4-bit tag for matching IN packets with OUT packets.
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[FIXME, write more...]
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Payload Len: 9-bit field that specifies the length of the payload
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field in bytes. Must be in the range 0 to 504 inclusive.
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Timestamp: 32-bit timestamp.
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On IN packets, the timestamp indicates the time at which the
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first sample of the packet was produced by the A/D converter(s)
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for that channel. On OUT packets, the timestamp specifies the
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time at which the first sample in the packet should go out the
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D/A converter(s) for that channel. If a packet reaches the
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head of the transmit queue, and the current time is later than
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the timestamp, an error is assumed to have occurred and the
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packet is discarded. As a special case, the timestamp
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0xffffffff is interpreted as "Now".
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The time base is a free running 32-bit counter that is
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incremented by the A/D sample-clock.
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Payload: Variable length field. Length is specified by the
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Payload Len field.
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Padding: This field is 504 - Payload Len bytes long, and its content
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is unspecified. This field pads the packet out to a constant
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512 bytes.
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"Data Channel" payload format:
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-------------------------------
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If Chan != 0x1f, the packet is a "data packet" and the payload is a
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sequence of homogeneous samples. The format of the samples is
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determined by the configuration associated with the given channel.
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It is often the case that the payload field contains 32-bit complex
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samples, each containing 16-bit real and imaginary components.
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"Control Channel" payload format:
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---------------------------------
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If Chan == 0x1f, the packet is a "control packet". The control channel
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payload consists of a sequence of 0 or more sub-packets.
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Each sub-packet starts on a 32-bit boundary, and consists of an 8-bit
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Opcode field, an 8-bit Length field, Length bytes of arguments, and 0,
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1, 2 or 3 bytes of padding to align the tail of the sub-packet to
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a 32-bit boundary.
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Control channel packets shall be processed at the head of the queue,
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and shall observe the timestamp semantics described above.
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General sub-packet format:
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--------------------------
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-//-+-+-+-+-+-+-+-+
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| Opcode | Length | <length bytes> ... |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-//-+-+-+-+-+-+-+-+
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Specific sub-packet formats:
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----------------------------
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RID: 6-bit Request-ID. Copied from request sub-packet into corresponding
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reply sub-packet. RID allows the host to match requests and replies.
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Reg Number: 10-bit Register Number.
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Ping Fixed Length:
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Opcode: OP_PING_FIXED
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Opcode | 2 | RID | Ping Value |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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Ping Fixed Length Reply:
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Opcode: OP_PING_FIXED_REPLY
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Opcode | 2 | RID | Ping Value |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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Write Register:
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Opcode: OP_WRITE_REG
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Opcode | 6 | mbz | Reg Number |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Register Value |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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Write Register Masked:
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Opcode: OP_WRITE_REG_MASKED
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REG[Num] = (REG[Num] & ~Mask) | (Value & Mask)
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That is, only the register bits that correspond to 1's in the
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mask are written with the new value.
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Opcode | 10 | mbz | Reg Number |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Register Value |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Mask Value |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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Read Register:
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Opcode: OP_READ_REG
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Opcode | 2 | RID | Reg Number |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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Read Register Reply:
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Opcode: OP_READ_REG_REPLY
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Opcode | 6 | RID | Reg Number |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Register Value |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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I2C Write:
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Opcode: OP_I2C_WRITE
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I2C Addr: 7-bit I2C address
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Data: The bytes to write to the I2C bus
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Length: Length of Data + 2
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Opcode | Length | mbz | I2C Addr |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Data ... .
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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I2C Read:
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Opcode: OP_I2C_READ
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I2C Addr: 7-bit I2C address
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Nbytes: Number of bytes to read from I2C bus
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Opcode | 3 | RID | mbz | I2C Addr |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Nbytes | unspecified padding |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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I2C Read Reply:
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Opcode: OP_I2C_READ_REPLY
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I2C Addr: 7-bit I2C address
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Data: Length - 2 bytes of data read from I2C bus.
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Opcode | Length | RID | mbz | I2C Addr |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Data ... .
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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SPI Write:
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Opcode: OP_SPI_WRITE
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Enables: Which SPI enables to assert (mask)
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Format: Specifies format of SPI data and Opt Header Bytes
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Opt Header Bytes: 2-byte field containing optional Tx bytes; see Format
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Data: The bytes to write to the SPI bus
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Length: Length of Data + 6
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Opcode | Length | mbz |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Enables | Format | Opt Header Bytes |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Data ... .
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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SPI Read:
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Opcode: OP_SPI_READ
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Enables: Which SPI enables to assert (mask)
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Format: Specifies format of SPI data and Opt Header Bytes
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Opt Header Bytes: 2-byte field containing optional Tx bytes; see Format
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Nbytes: Number of bytes to read from SPI bus.
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Opcode | 7 | RID | mbz |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Enables | Format | Opt Header Bytes |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Nbytes | unspecified padding |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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SPI Read Reply:
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Opcode: OP_SPI_READ_REPLY
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Data: Length - 2 bytes of data read from SPI bus.
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Opcode | Length | RID | mbz |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Data ... .
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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Delay:
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Opcode: OP_DELAY
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Ticks: 16-bit unsigned delay count
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Delay Ticks clock ticks before executing next operation.
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Opcode | 2 | Ticks |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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@ -0,0 +1,303 @@
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[[dev_USRP1_inband_signaling_usb]]
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==== USRP1 in-band USB protocol
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This section specifies the format of USB packets used for in-band data
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transmission and signaling on the USRP1. All packets are 512-byte long, and are
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transfered using USB "bulk" transfers.
|
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IN packets are sent towards the host. OUT packets are sent away from the host.
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The layout is 32-bits wide. All data is transmitted in little-endian format
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across the USB.
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----
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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|O|U|D|S|E| RSSI | Chan | mbz | Tag | Payload Len |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Timestamp |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| |
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+ +
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| Payload |
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. .
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. .
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. .
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| |
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+ +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| ... | .
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+-+-+-+-+-+-+-+ .
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. .
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. Padding .
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. .
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| |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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----
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mbz: Must be Zero::
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These bits must be zero in both IN and OUT packets.
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O: Overrun Flag::
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Set in an IN packet if an overrun condition was detected. Must be zero in OUT
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packets. Overrun occurs when the FPGA has data to transmit to the host and there
|
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is no buffer space available. This generally indicates a problem on the host.
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Either it is not keeping up, or it has configured the FPGA to transmit data at a
|
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higher rate than the transport (USB) can support.
|
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|
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U: Underrun Flag::
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Set in an IN packet if an underrun condition was detected. Must be zero in OUT
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packets. Underrun occurs when the FPGA runs out of samples, and it's not between
|
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bursts. See the "End of Burst flag" below.
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D: Dropped Packet Flag::
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Set in an IN packet if the FPGA discarded an OUT packet because its timestamp
|
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had already passed.
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S: Start of Burst Flag::
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Set in an OUT packet if the data is the first segment of what is logically a
|
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continuous burst of data. Must be zero in IN packets.
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E: End of Burst Flag::
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Set in an OUT packet if the data is the last segment of what is logically a
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continuous burst of data. Must be zero in IN packets. Underruns are not
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reported when the FPGA runs out of samples between bursts.
|
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|
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RSSI: 6-bit Received Strength Signal Indicator::
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Must be zero in OUT packets. In IN packets, indicates RSSI as reported by front
|
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end. FIXME The format and interpretation are to be determined.
|
||||
|
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Chan: 5-bit logical channel number::
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Channel number 0x1f is reserved for control information. See "Control Channel"
|
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below. Other channels are "data channels". Each data channel is logically
|
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independent of the others. A data channel payload field contains a sequence of
|
||||
homogeneous samples. The format of the samples is determined by the
|
||||
configuration associated with the given channel. It is often the case that the
|
||||
payload field contains 32-bit complex samples, each containing 16-bit real and
|
||||
imaginary components.
|
||||
|
||||
Tag::
|
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4-bit tag for matching IN packets with OUT packets.
|
||||
//FIXME, write more...
|
||||
|
||||
Payload Len::
|
||||
9-bit field that specifies the length of the payload field in bytes. Must be in
|
||||
the range 0 to 504 inclusive.
|
||||
|
||||
Timestamp: 32-bit timestamp::
|
||||
On IN packets, the timestamp indicates the time at which the first sample of the
|
||||
packet was produced by the A/D converter(s) for that channel. On OUT packets,
|
||||
the timestamp specifies the time at which the first sample in the packet should
|
||||
go out the D/A converter(s) for that channel. If a packet reaches the head of
|
||||
the transmit queue, and the current time is later than the timestamp, an error
|
||||
is assumed to have occurred and the packet is discarded. As a special case, the
|
||||
timestamp 0xffffffff is interpreted as "Now".
|
||||
The time base is a free running 32-bit counter that is incremented by the A/D
|
||||
sample-clock.
|
||||
|
||||
Payload::
|
||||
Variable length field Length is specified by the Payload Len field.
|
||||
|
||||
Padding::
|
||||
This field is 504 - Payload Len bytes long, and its content is unspecified.
|
||||
This field pads the packet out to a constant 512 bytes.
|
||||
|
||||
|
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===== "Data Channel" payload format
|
||||
|
||||
If `Chan != 0x1f`, the packet is a "data packet" and the payload is a sequence of
|
||||
homogeneous samples. The format of the samples is determined by the
|
||||
configuration associated with the given channel. It is often the case that the
|
||||
payload field contains 32-bit complex samples, each containing 16-bit real and
|
||||
imaginary components.
|
||||
|
||||
|
||||
===== "Control Channel" payload format
|
||||
|
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If `Chan == 0x1f`, the packet is a "control packet". The control channel payload
|
||||
consists of a sequence of 0 or more sub-packets.
|
||||
|
||||
Each sub-packet starts on a 32-bit boundary, and consists of an 8-bit Opcode
|
||||
field, an 8-bit Length field, Length bytes of arguments, and 0, 1, 2 or 3 bytes
|
||||
of padding to align the tail of the sub-packet to a 32-bit boundary.
|
||||
|
||||
Control channel packets shall be processed at the head of the queue, and shall
|
||||
observe the timestamp semantics described above.
|
||||
|
||||
|
||||
===== General sub-packet format
|
||||
|
||||
----
|
||||
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-//-+-+-+-+-+-+-+-+
|
||||
| Opcode | Length | <length bytes> ... |
|
||||
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-//-+-+-+-+-+-+-+-+
|
||||
----
|
||||
|
||||
===== Specific sub-packet formats
|
||||
|
||||
RID: 6-bit Request-ID::
|
||||
Copied from request sub-packet into corresponding reply sub-packet. RID allows
|
||||
the host to match requests and replies.
|
||||
|
||||
Reg Number::
|
||||
10-bit Register Number.
|
||||
|
||||
Ping Fixed Length::
|
||||
|
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* Opcode: OP_PING_FIXED
|
||||
----
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||||
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|
||||
| Opcode | 2 | RID | Ping Value |
|
||||
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|
||||
----
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||||
|
||||
Ping Fixed Length Reply::
|
||||
|
||||
* Opcode: OP_PING_FIXED_REPLY
|
||||
----
|
||||
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|
||||
| Opcode | 2 | RID | Ping Value |
|
||||
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|
||||
----
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||||
|
||||
Write Register::
|
||||
|
||||
* Opcode: OP_WRITE_REG
|
||||
----
|
||||
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|
||||
| Opcode | 6 | mbz | Reg Number |
|
||||
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|
||||
| Register Value |
|
||||
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|
||||
----
|
||||
|
||||
Write Register Masked::
|
||||
Only the register bits that correspond to 1's in the mask are written
|
||||
with the new value. `REG[Num] = (REG[Num] & ~Mask) | (Value & Mask)`
|
||||
|
||||
* Opcode: OP_WRITE_REG_MASKED
|
||||
----
|
||||
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|
||||
| Opcode | 10 | mbz | Reg Number |
|
||||
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|
||||
| Register Value |
|
||||
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|
||||
| Mask Value |
|
||||
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|
||||
----
|
||||
|
||||
Read Register::
|
||||
|
||||
* Opcode: OP_READ_REG
|
||||
----
|
||||
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|
||||
| Opcode | 2 | RID | Reg Number |
|
||||
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|
||||
----
|
||||
|
||||
Read Register Reply::
|
||||
|
||||
* Opcode: OP_READ_REG_REPLY
|
||||
----
|
||||
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|
||||
| Opcode | 6 | RID | Reg Number |
|
||||
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|
||||
| Register Value |
|
||||
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|
||||
----
|
||||
|
||||
I2C Write::
|
||||
|
||||
* Opcode: OP_I2C_WRITE
|
||||
* I2C Addr: 7-bit I2C address
|
||||
* Data: The bytes to write to the I2C bus
|
||||
* Length: Length of Data + 2
|
||||
----
|
||||
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|
||||
| Opcode | Length | mbz | I2C Addr |
|
||||
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|
||||
| Data ... .
|
||||
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|
||||
----
|
||||
|
||||
I2C Read::
|
||||
|
||||
* Opcode: OP_I2C_READ
|
||||
* I2C Addr: 7-bit I2C address
|
||||
* Nbytes: Number of bytes to read from I2C bus
|
||||
----
|
||||
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|
||||
| Opcode | 3 | RID | mbz | I2C Addr |
|
||||
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|
||||
| Nbytes | unspecified padding |
|
||||
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|
||||
----
|
||||
|
||||
I2C Read Reply::
|
||||
|
||||
* Opcode: OP_I2C_READ_REPLY
|
||||
* I2C Addr: 7-bit I2C address
|
||||
* Data: Length - 2 bytes of data read from I2C bus.
|
||||
----
|
||||
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|
||||
| Opcode | Length | RID | mbz | I2C Addr |
|
||||
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|
||||
| Data ... .
|
||||
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|
||||
----
|
||||
|
||||
SPI Write::
|
||||
|
||||
* Opcode: OP_SPI_WRITE
|
||||
* Enables: Which SPI enables to assert (mask)
|
||||
* Format: Specifies format of SPI data and Opt Header Bytes
|
||||
* Opt Header Bytes: 2-byte field containing optional Tx bytes; see Format
|
||||
* Data: The bytes to write to the SPI bus
|
||||
* Length: Length of Data + 6
|
||||
----
|
||||
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|
||||
| Opcode | Length | mbz |
|
||||
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|
||||
| Enables | Format | Opt Header Bytes |
|
||||
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|
||||
| Data ... .
|
||||
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|
||||
----
|
||||
|
||||
SPI Read::
|
||||
|
||||
* Opcode: OP_SPI_READ
|
||||
* Enables: Which SPI enables to assert (mask)
|
||||
* Format: Specifies format of SPI data and Opt Header Bytes
|
||||
* Opt Header Bytes: 2-byte field containing optional Tx bytes; see Format
|
||||
* Nbytes: Number of bytes to read from SPI bus.
|
||||
----
|
||||
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|
||||
| Opcode | 7 | RID | mbz |
|
||||
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|
||||
| Enables | Format | Opt Header Bytes |
|
||||
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|
||||
| Nbytes | unspecified padding |
|
||||
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|
||||
----
|
||||
|
||||
SPI Read Reply::
|
||||
|
||||
* Opcode: OP_SPI_READ_REPLY
|
||||
* Data: Length - 2 bytes of data read from SPI bus.
|
||||
----
|
||||
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|
||||
| Opcode | Length | RID | mbz |
|
||||
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|
||||
| Data ... .
|
||||
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|
||||
----
|
||||
|
||||
Delay::
|
||||
|
||||
* Opcode: OP_DELAY
|
||||
* Ticks: 16-bit unsigned delay count
|
||||
* Delay Ticks clock ticks before executing next operation.
|
||||
----
|
||||
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|
||||
| Opcode | 2 | Ticks |
|
||||
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|
||||
----
|
|
@ -29,6 +29,8 @@ flags, which can be found in each subsection relative to each backend below.
|
|||
|
||||
The binary _osmo-trx-usrp1_ is used to drive this device, see <<backend_usrp1>>.
|
||||
|
||||
include::./device-usrp-inband-signaling-usb.adoc[]
|
||||
|
||||
[[dev_ettus_b200]]
|
||||
=== Ettus B200
|
||||
|
||||
|
|
Loading…
Reference in New Issue