osmo-pcu/tests/alloc/AllocTest.ok

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Testing alloc_a direction(0)
Testing alloc_a direction(1)
Testing alloc_a direction(0)
Testing alloc_a direction(1)
Going to test multislot assignment MS_CLASS=0
Testing UL then DL assignment.
PDCH[6] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing DL then UL assignment followed by update
PDCH[6] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
PDCH[6] is used for UL
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
PDCH[7] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing jolly example
PDCH[3] is used for UL
PDCH[3] is control_ts for UL
PDCH[3] is first common for UL
PDCH[1] is used for DL
PDCH[2] is used for DL
PDCH[3] is used for DL
PDCH[4] is used for DL
PDCH[3] is control_ts for DL
PDCH[3] is first common for DL
Going to test multislot assignment MS_CLASS=1
Testing UL then DL assignment.
PDCH[5] is used for UL
PDCH[5] is control_ts for UL
PDCH[5] is first common for UL
PDCH[5] is used for DL
PDCH[5] is control_ts for DL
PDCH[5] is first common for DL
Testing DL then UL assignment followed by update
PDCH[5] is used for DL
PDCH[5] is control_ts for DL
PDCH[5] is first common for DL
PDCH[5] is used for UL
PDCH[5] is control_ts for UL
PDCH[5] is first common for UL
PDCH[5] is used for DL
PDCH[5] is control_ts for DL
PDCH[5] is first common for DL
Testing jolly example
PDCH[1] is used for UL
PDCH[1] is control_ts for UL
PDCH[1] is first common for UL
PDCH[1] is used for DL
PDCH[1] is control_ts for DL
PDCH[1] is first common for DL
Going to test multislot assignment MS_CLASS=2
Testing UL then DL assignment.
PDCH[6] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing DL then UL assignment followed by update
PDCH[6] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
PDCH[6] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing jolly example
PDCH[2] is used for UL
PDCH[2] is control_ts for UL
PDCH[2] is first common for UL
PDCH[1] is used for DL
PDCH[2] is used for DL
PDCH[2] is control_ts for DL
PDCH[2] is first common for DL
Going to test multislot assignment MS_CLASS=3
Testing UL then DL assignment.
PDCH[6] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing DL then UL assignment followed by update
PDCH[6] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
PDCH[6] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing jolly example
PDCH[2] is used for UL
PDCH[2] is control_ts for UL
PDCH[2] is first common for UL
PDCH[1] is used for DL
PDCH[2] is used for DL
PDCH[2] is control_ts for DL
PDCH[2] is first common for DL
Going to test multislot assignment MS_CLASS=4
Testing UL then DL assignment.
PDCH[6] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing DL then UL assignment followed by update
PDCH[6] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
PDCH[6] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing jolly example
PDCH[2] is used for UL
PDCH[2] is control_ts for UL
PDCH[2] is first common for UL
PDCH[1] is used for DL
PDCH[2] is used for DL
PDCH[3] is used for DL
PDCH[2] is control_ts for DL
PDCH[2] is first common for DL
Going to test multislot assignment MS_CLASS=5
Testing UL then DL assignment.
PDCH[5] is used for UL
PDCH[5] is control_ts for UL
PDCH[5] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[5] is control_ts for DL
PDCH[5] is first common for DL
Testing DL then UL assignment followed by update
PDCH[5] is used for DL
PDCH[5] is control_ts for DL
PDCH[5] is first common for DL
PDCH[5] is used for UL
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
PDCH[6] is used for UL
PDCH[5] is control_ts for UL
PDCH[5] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[5] is control_ts for DL
PDCH[5] is first common for DL
Testing jolly example
PDCH[1] is used for UL
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
PDCH[2] is used for UL
PDCH[1] is control_ts for UL
PDCH[1] is first common for UL
PDCH[1] is used for DL
PDCH[2] is used for DL
PDCH[1] is control_ts for DL
PDCH[1] is first common for DL
Going to test multislot assignment MS_CLASS=6
Testing UL then DL assignment.
PDCH[6] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing DL then UL assignment followed by update
PDCH[6] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
PDCH[6] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing jolly example
PDCH[2] is used for UL
PDCH[2] is control_ts for UL
PDCH[2] is first common for UL
PDCH[1] is used for DL
PDCH[2] is used for DL
PDCH[3] is used for DL
PDCH[2] is control_ts for DL
PDCH[2] is first common for DL
Going to test multislot assignment MS_CLASS=7
Testing UL then DL assignment.
PDCH[6] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing DL then UL assignment followed by update
PDCH[6] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
PDCH[6] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing jolly example
PDCH[2] is used for UL
PDCH[2] is control_ts for UL
PDCH[2] is first common for UL
PDCH[1] is used for DL
PDCH[2] is used for DL
PDCH[3] is used for DL
PDCH[2] is control_ts for DL
PDCH[2] is first common for DL
Going to test multislot assignment MS_CLASS=8
Testing UL then DL assignment.
PDCH[6] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing DL then UL assignment followed by update
PDCH[6] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
PDCH[6] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing jolly example
PDCH[3] is used for UL
PDCH[3] is control_ts for UL
PDCH[3] is first common for UL
PDCH[1] is used for DL
PDCH[2] is used for DL
PDCH[3] is used for DL
PDCH[4] is used for DL
PDCH[3] is control_ts for DL
PDCH[3] is first common for DL
Going to test multislot assignment MS_CLASS=9
Testing UL then DL assignment.
PDCH[6] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing DL then UL assignment followed by update
PDCH[6] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
PDCH[6] is used for UL
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
PDCH[7] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing jolly example
PDCH[2] is used for UL
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
PDCH[3] is used for UL
PDCH[2] is control_ts for UL
PDCH[2] is first common for UL
PDCH[1] is used for DL
PDCH[2] is used for DL
PDCH[3] is used for DL
PDCH[2] is control_ts for DL
PDCH[2] is first common for DL
Going to test multislot assignment MS_CLASS=10
Testing UL then DL assignment.
PDCH[6] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing DL then UL assignment followed by update
PDCH[6] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
PDCH[6] is used for UL
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
PDCH[7] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing jolly example
PDCH[3] is used for UL
PDCH[3] is control_ts for UL
PDCH[3] is first common for UL
PDCH[1] is used for DL
PDCH[2] is used for DL
PDCH[3] is used for DL
PDCH[4] is used for DL
PDCH[3] is control_ts for DL
PDCH[3] is first common for DL
Going to test multislot assignment MS_CLASS=11
Testing UL then DL assignment.
PDCH[6] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing DL then UL assignment followed by update
PDCH[6] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
PDCH[6] is used for UL
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
PDCH[7] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing jolly example
PDCH[3] is used for UL
PDCH[3] is control_ts for UL
PDCH[3] is first common for UL
PDCH[1] is used for DL
PDCH[2] is used for DL
PDCH[3] is used for DL
PDCH[4] is used for DL
PDCH[3] is control_ts for DL
PDCH[3] is first common for DL
Going to test multislot assignment MS_CLASS=12
Testing UL then DL assignment.
PDCH[6] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing DL then UL assignment followed by update
PDCH[6] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
PDCH[6] is used for UL
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
PDCH[7] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing jolly example
PDCH[3] is used for UL
PDCH[3] is control_ts for UL
PDCH[3] is first common for UL
PDCH[1] is used for DL
PDCH[2] is used for DL
PDCH[3] is used for DL
PDCH[4] is used for DL
PDCH[3] is control_ts for DL
PDCH[3] is first common for DL
Going to test multislot assignment MS_CLASS=13
Testing UL then DL assignment.
PDCH[5] is used for UL
PDCH[5] is control_ts for UL
PDCH[5] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[5] is control_ts for DL
PDCH[5] is first common for DL
Testing DL then UL assignment followed by update
PDCH[5] is used for DL
PDCH[5] is control_ts for DL
PDCH[5] is first common for DL
PDCH[5] is used for UL
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
PDCH[6] is used for UL
PDCH[7] is used for UL
PDCH[5] is control_ts for UL
PDCH[5] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[5] is control_ts for DL
PDCH[5] is first common for DL
Testing jolly example
PDCH[1] is used for UL
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
PDCH[2] is used for UL
PDCH[3] is used for UL
PDCH[1] is control_ts for UL
PDCH[1] is first common for UL
PDCH[1] is used for DL
PDCH[2] is used for DL
PDCH[3] is used for DL
PDCH[1] is control_ts for DL
PDCH[1] is first common for DL
Going to test multislot assignment MS_CLASS=14
Testing UL then DL assignment.
PDCH[5] is used for UL
PDCH[5] is control_ts for UL
PDCH[5] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[5] is control_ts for DL
PDCH[5] is first common for DL
Testing DL then UL assignment followed by update
PDCH[5] is used for DL
PDCH[5] is control_ts for DL
PDCH[5] is first common for DL
PDCH[5] is used for UL
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
PDCH[6] is used for UL
PDCH[7] is used for UL
PDCH[5] is control_ts for UL
PDCH[5] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[5] is control_ts for DL
PDCH[5] is first common for DL
Testing jolly example
PDCH[1] is used for UL
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
PDCH[2] is used for UL
PDCH[3] is used for UL
PDCH[4] is used for UL
PDCH[1] is control_ts for UL
PDCH[1] is first common for UL
PDCH[1] is used for DL
PDCH[2] is used for DL
PDCH[3] is used for DL
PDCH[4] is used for DL
PDCH[1] is control_ts for DL
PDCH[1] is first common for DL
Going to test multislot assignment MS_CLASS=15
Testing UL then DL assignment.
PDCH[5] is used for UL
PDCH[5] is control_ts for UL
PDCH[5] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[5] is control_ts for DL
PDCH[5] is first common for DL
Testing DL then UL assignment followed by update
PDCH[5] is used for DL
PDCH[5] is control_ts for DL
PDCH[5] is first common for DL
PDCH[5] is used for UL
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
PDCH[6] is used for UL
PDCH[7] is used for UL
PDCH[5] is control_ts for UL
PDCH[5] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[5] is control_ts for DL
PDCH[5] is first common for DL
Testing jolly example
PDCH[1] is used for UL
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
PDCH[2] is used for UL
PDCH[3] is used for UL
PDCH[4] is used for UL
PDCH[1] is control_ts for UL
PDCH[1] is first common for UL
PDCH[1] is used for DL
PDCH[2] is used for DL
PDCH[3] is used for DL
PDCH[4] is used for DL
PDCH[1] is control_ts for DL
PDCH[1] is first common for DL
Going to test multislot assignment MS_CLASS=16
Testing UL then DL assignment.
PDCH[5] is used for UL
PDCH[5] is control_ts for UL
PDCH[5] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[5] is control_ts for DL
PDCH[5] is first common for DL
Testing DL then UL assignment followed by update
PDCH[5] is used for DL
PDCH[5] is control_ts for DL
PDCH[5] is first common for DL
PDCH[5] is used for UL
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
PDCH[6] is used for UL
PDCH[7] is used for UL
PDCH[5] is control_ts for UL
PDCH[5] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[5] is control_ts for DL
PDCH[5] is first common for DL
Testing jolly example
PDCH[1] is used for UL
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
PDCH[2] is used for UL
PDCH[3] is used for UL
PDCH[4] is used for UL
PDCH[1] is control_ts for UL
PDCH[1] is first common for UL
PDCH[1] is used for DL
PDCH[2] is used for DL
PDCH[3] is used for DL
PDCH[4] is used for DL
PDCH[1] is control_ts for DL
PDCH[1] is first common for DL
Going to test multislot assignment MS_CLASS=17
Testing UL then DL assignment.
PDCH[5] is used for UL
PDCH[5] is control_ts for UL
PDCH[5] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[5] is control_ts for DL
PDCH[5] is first common for DL
Testing DL then UL assignment followed by update
PDCH[5] is used for DL
PDCH[5] is control_ts for DL
PDCH[5] is first common for DL
PDCH[5] is used for UL
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
PDCH[6] is used for UL
PDCH[7] is used for UL
PDCH[5] is control_ts for UL
PDCH[5] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[5] is control_ts for DL
PDCH[5] is first common for DL
Testing jolly example
PDCH[1] is used for UL
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
PDCH[2] is used for UL
PDCH[3] is used for UL
PDCH[4] is used for UL
PDCH[1] is control_ts for UL
PDCH[1] is first common for UL
PDCH[1] is used for DL
PDCH[2] is used for DL
PDCH[3] is used for DL
PDCH[4] is used for DL
PDCH[1] is control_ts for DL
PDCH[1] is first common for DL
Going to test multislot assignment MS_CLASS=18
Testing UL then DL assignment.
PDCH[5] is used for UL
PDCH[5] is control_ts for UL
PDCH[5] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[5] is control_ts for DL
PDCH[5] is first common for DL
Testing DL then UL assignment followed by update
PDCH[5] is used for DL
PDCH[5] is control_ts for DL
PDCH[5] is first common for DL
PDCH[5] is used for UL
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
PDCH[6] is used for UL
PDCH[7] is used for UL
PDCH[5] is control_ts for UL
PDCH[5] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[5] is control_ts for DL
PDCH[5] is first common for DL
Testing jolly example
PDCH[1] is used for UL
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
PDCH[2] is used for UL
PDCH[3] is used for UL
PDCH[4] is used for UL
PDCH[1] is control_ts for UL
PDCH[1] is first common for UL
PDCH[1] is used for DL
PDCH[2] is used for DL
PDCH[3] is used for DL
PDCH[4] is used for DL
PDCH[1] is control_ts for DL
PDCH[1] is first common for DL
Going to test multislot assignment MS_CLASS=19
Testing UL then DL assignment.
PDCH[6] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing DL then UL assignment followed by update
PDCH[6] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
PDCH[6] is used for UL
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
PDCH[7] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing jolly example
PDCH[3] is used for UL
PDCH[3] is control_ts for UL
PDCH[3] is first common for UL
PDCH[1] is used for DL
PDCH[2] is used for DL
PDCH[3] is used for DL
PDCH[4] is used for DL
PDCH[3] is control_ts for DL
PDCH[3] is first common for DL
Going to test multislot assignment MS_CLASS=20
Testing UL then DL assignment.
PDCH[6] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing DL then UL assignment followed by update
PDCH[6] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
PDCH[6] is used for UL
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
PDCH[7] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing jolly example
PDCH[3] is used for UL
PDCH[3] is control_ts for UL
PDCH[3] is first common for UL
PDCH[1] is used for DL
PDCH[2] is used for DL
PDCH[3] is used for DL
PDCH[4] is used for DL
PDCH[3] is control_ts for DL
PDCH[3] is first common for DL
Going to test multislot assignment MS_CLASS=21
Testing UL then DL assignment.
PDCH[6] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing DL then UL assignment followed by update
PDCH[6] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
PDCH[6] is used for UL
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
PDCH[7] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing jolly example
PDCH[3] is used for UL
PDCH[3] is control_ts for UL
PDCH[3] is first common for UL
PDCH[1] is used for DL
PDCH[2] is used for DL
PDCH[3] is used for DL
PDCH[4] is used for DL
PDCH[3] is control_ts for DL
PDCH[3] is first common for DL
Going to test multislot assignment MS_CLASS=22
Testing UL then DL assignment.
PDCH[6] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing DL then UL assignment followed by update
PDCH[6] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
PDCH[6] is used for UL
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
PDCH[7] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing jolly example
PDCH[3] is used for UL
PDCH[3] is control_ts for UL
PDCH[3] is first common for UL
PDCH[1] is used for DL
PDCH[2] is used for DL
PDCH[3] is used for DL
PDCH[4] is used for DL
PDCH[3] is control_ts for DL
PDCH[3] is first common for DL
Going to test multislot assignment MS_CLASS=23
Testing UL then DL assignment.
PDCH[6] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing DL then UL assignment followed by update
PDCH[6] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
PDCH[6] is used for UL
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
PDCH[7] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing jolly example
PDCH[3] is used for UL
PDCH[3] is control_ts for UL
PDCH[3] is first common for UL
PDCH[1] is used for DL
PDCH[2] is used for DL
PDCH[3] is used for DL
PDCH[4] is used for DL
PDCH[3] is control_ts for DL
PDCH[3] is first common for DL
Going to test multislot assignment MS_CLASS=24
Testing UL then DL assignment.
PDCH[6] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing DL then UL assignment followed by update
PDCH[6] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
PDCH[6] is used for UL
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
PDCH[7] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing jolly example
PDCH[3] is used for UL
PDCH[3] is control_ts for UL
PDCH[3] is first common for UL
PDCH[1] is used for DL
PDCH[2] is used for DL
PDCH[3] is used for DL
PDCH[4] is used for DL
PDCH[3] is control_ts for DL
PDCH[3] is first common for DL
Going to test multislot assignment MS_CLASS=25
Testing UL then DL assignment.
PDCH[6] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing DL then UL assignment followed by update
PDCH[6] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
PDCH[6] is used for UL
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
PDCH[7] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing jolly example
PDCH[3] is used for UL
PDCH[3] is control_ts for UL
PDCH[3] is first common for UL
PDCH[1] is used for DL
PDCH[2] is used for DL
PDCH[3] is used for DL
PDCH[4] is used for DL
PDCH[3] is control_ts for DL
PDCH[3] is first common for DL
Going to test multislot assignment MS_CLASS=26
Testing UL then DL assignment.
PDCH[6] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing DL then UL assignment followed by update
PDCH[6] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
PDCH[6] is used for UL
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
PDCH[7] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing jolly example
PDCH[3] is used for UL
PDCH[3] is control_ts for UL
PDCH[3] is first common for UL
PDCH[1] is used for DL
PDCH[2] is used for DL
PDCH[3] is used for DL
PDCH[4] is used for DL
PDCH[3] is control_ts for DL
PDCH[3] is first common for DL
Going to test multislot assignment MS_CLASS=27
Testing UL then DL assignment.
PDCH[6] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing DL then UL assignment followed by update
PDCH[6] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
PDCH[6] is used for UL
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
PDCH[7] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing jolly example
PDCH[3] is used for UL
PDCH[3] is control_ts for UL
PDCH[3] is first common for UL
PDCH[1] is used for DL
PDCH[2] is used for DL
PDCH[3] is used for DL
PDCH[4] is used for DL
PDCH[3] is control_ts for DL
PDCH[3] is first common for DL
Going to test multislot assignment MS_CLASS=28
Testing UL then DL assignment.
PDCH[6] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing DL then UL assignment followed by update
PDCH[6] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
PDCH[6] is used for UL
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
PDCH[7] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing jolly example
PDCH[3] is used for UL
PDCH[3] is control_ts for UL
PDCH[3] is first common for UL
PDCH[1] is used for DL
PDCH[2] is used for DL
PDCH[3] is used for DL
PDCH[4] is used for DL
PDCH[3] is control_ts for DL
PDCH[3] is first common for DL
Going to test multislot assignment MS_CLASS=29
Testing UL then DL assignment.
PDCH[6] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing DL then UL assignment followed by update
PDCH[6] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
PDCH[6] is used for UL
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
PDCH[7] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing jolly example
PDCH[3] is used for UL
PDCH[3] is control_ts for UL
PDCH[3] is first common for UL
PDCH[1] is used for DL
PDCH[2] is used for DL
PDCH[3] is used for DL
PDCH[4] is used for DL
PDCH[3] is control_ts for DL
PDCH[3] is first common for DL
Going to test multislot assignment MS_CLASS=30
Testing UL then DL assignment.
PDCH[6] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing DL then UL assignment followed by update
PDCH[6] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
PDCH[6] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing jolly example
PDCH[3] is used for UL
PDCH[3] is control_ts for UL
PDCH[3] is first common for UL
PDCH[1] is used for DL
PDCH[2] is used for DL
PDCH[3] is used for DL
PDCH[4] is used for DL
PDCH[3] is control_ts for DL
PDCH[3] is first common for DL
Going to test multislot assignment MS_CLASS=31
Testing UL then DL assignment.
PDCH[6] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing DL then UL assignment followed by update
PDCH[6] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
PDCH[6] is used for UL
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
PDCH[7] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing jolly example
PDCH[3] is used for UL
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
PDCH[4] is used for UL
PDCH[3] is control_ts for UL
PDCH[3] is first common for UL
PDCH[1] is used for DL
PDCH[2] is used for DL
PDCH[3] is used for DL
PDCH[4] is used for DL
PDCH[3] is control_ts for DL
PDCH[3] is first common for DL
Going to test multislot assignment MS_CLASS=32
Testing UL then DL assignment.
PDCH[6] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing DL then UL assignment followed by update
PDCH[6] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
PDCH[6] is used for UL
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
PDCH[7] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing jolly example
PDCH[3] is used for UL
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
PDCH[4] is used for UL
PDCH[3] is control_ts for UL
PDCH[3] is first common for UL
PDCH[1] is used for DL
PDCH[2] is used for DL
PDCH[3] is used for DL
PDCH[4] is used for DL
PDCH[3] is control_ts for DL
PDCH[3] is first common for DL
Going to test multislot assignment MS_CLASS=33
Testing UL then DL assignment.
PDCH[6] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing DL then UL assignment followed by update
PDCH[6] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
PDCH[6] is used for UL
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
PDCH[7] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing jolly example
PDCH[3] is used for UL
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
PDCH[4] is used for UL
PDCH[3] is control_ts for UL
PDCH[3] is first common for UL
PDCH[1] is used for DL
PDCH[2] is used for DL
PDCH[3] is used for DL
PDCH[4] is used for DL
PDCH[3] is control_ts for DL
PDCH[3] is first common for DL
Going to test multislot assignment MS_CLASS=34
Testing UL then DL assignment.
PDCH[6] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing DL then UL assignment followed by update
PDCH[6] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
PDCH[6] is used for UL
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
PDCH[7] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing jolly example
PDCH[3] is used for UL
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
PDCH[4] is used for UL
PDCH[3] is control_ts for UL
PDCH[3] is first common for UL
PDCH[1] is used for DL
PDCH[2] is used for DL
PDCH[3] is used for DL
PDCH[4] is used for DL
PDCH[3] is control_ts for DL
PDCH[3] is first common for DL
Going to test multislot assignment MS_CLASS=35
Testing UL then DL assignment.
PDCH[6] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing DL then UL assignment followed by update
PDCH[6] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
PDCH[6] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing jolly example
PDCH[3] is used for UL
PDCH[3] is control_ts for UL
PDCH[3] is first common for UL
PDCH[1] is used for DL
PDCH[2] is used for DL
PDCH[3] is used for DL
PDCH[4] is used for DL
PDCH[3] is control_ts for DL
PDCH[3] is first common for DL
Going to test multislot assignment MS_CLASS=36
Testing UL then DL assignment.
PDCH[6] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing DL then UL assignment followed by update
PDCH[6] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
PDCH[6] is used for UL
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
PDCH[7] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing jolly example
PDCH[3] is used for UL
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
PDCH[4] is used for UL
PDCH[3] is control_ts for UL
PDCH[3] is first common for UL
PDCH[1] is used for DL
PDCH[2] is used for DL
PDCH[3] is used for DL
PDCH[4] is used for DL
PDCH[3] is control_ts for DL
PDCH[3] is first common for DL
Going to test multislot assignment MS_CLASS=37
Testing UL then DL assignment.
PDCH[6] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing DL then UL assignment followed by update
PDCH[6] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
PDCH[6] is used for UL
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
PDCH[7] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing jolly example
PDCH[3] is used for UL
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
PDCH[4] is used for UL
PDCH[3] is control_ts for UL
PDCH[3] is first common for UL
PDCH[1] is used for DL
PDCH[2] is used for DL
PDCH[3] is used for DL
PDCH[4] is used for DL
PDCH[3] is control_ts for DL
PDCH[3] is first common for DL
Going to test multislot assignment MS_CLASS=38
Testing UL then DL assignment.
PDCH[6] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing DL then UL assignment followed by update
PDCH[6] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
PDCH[6] is used for UL
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
PDCH[7] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing jolly example
PDCH[3] is used for UL
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
PDCH[4] is used for UL
PDCH[3] is control_ts for UL
PDCH[3] is first common for UL
PDCH[1] is used for DL
PDCH[2] is used for DL
PDCH[3] is used for DL
PDCH[4] is used for DL
PDCH[3] is control_ts for DL
PDCH[3] is first common for DL
Going to test multislot assignment MS_CLASS=39
Testing UL then DL assignment.
PDCH[6] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing DL then UL assignment followed by update
PDCH[6] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
PDCH[6] is used for UL
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
PDCH[7] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing jolly example
PDCH[3] is used for UL
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
PDCH[4] is used for UL
PDCH[3] is control_ts for UL
PDCH[3] is first common for UL
PDCH[1] is used for DL
PDCH[2] is used for DL
PDCH[3] is used for DL
PDCH[4] is used for DL
PDCH[3] is control_ts for DL
PDCH[3] is first common for DL
Going to test multislot assignment MS_CLASS=40
Testing UL then DL assignment.
PDCH[6] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing DL then UL assignment followed by update
PDCH[6] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
PDCH[6] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing jolly example
PDCH[3] is used for UL
PDCH[3] is control_ts for UL
PDCH[3] is first common for UL
PDCH[1] is used for DL
PDCH[2] is used for DL
PDCH[3] is used for DL
PDCH[4] is used for DL
PDCH[3] is control_ts for DL
PDCH[3] is first common for DL
Going to test multislot assignment MS_CLASS=41
Testing UL then DL assignment.
PDCH[6] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing DL then UL assignment followed by update
PDCH[6] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
PDCH[6] is used for UL
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
PDCH[7] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing jolly example
PDCH[3] is used for UL
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
PDCH[4] is used for UL
PDCH[3] is control_ts for UL
PDCH[3] is first common for UL
PDCH[1] is used for DL
PDCH[2] is used for DL
PDCH[3] is used for DL
PDCH[4] is used for DL
PDCH[3] is control_ts for DL
PDCH[3] is first common for DL
Going to test multislot assignment MS_CLASS=42
Testing UL then DL assignment.
PDCH[6] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing DL then UL assignment followed by update
PDCH[6] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
PDCH[6] is used for UL
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
PDCH[7] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing jolly example
PDCH[3] is used for UL
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
PDCH[4] is used for UL
PDCH[3] is control_ts for UL
PDCH[3] is first common for UL
PDCH[1] is used for DL
PDCH[2] is used for DL
PDCH[3] is used for DL
PDCH[4] is used for DL
PDCH[3] is control_ts for DL
PDCH[3] is first common for DL
Going to test multislot assignment MS_CLASS=43
Testing UL then DL assignment.
PDCH[6] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing DL then UL assignment followed by update
PDCH[6] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
PDCH[6] is used for UL
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
PDCH[7] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing jolly example
PDCH[3] is used for UL
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
PDCH[4] is used for UL
PDCH[3] is control_ts for UL
PDCH[3] is first common for UL
PDCH[1] is used for DL
PDCH[2] is used for DL
PDCH[3] is used for DL
PDCH[4] is used for DL
PDCH[3] is control_ts for DL
PDCH[3] is first common for DL
Going to test multislot assignment MS_CLASS=44
Testing UL then DL assignment.
PDCH[6] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing DL then UL assignment followed by update
PDCH[6] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
PDCH[6] is used for UL
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
PDCH[7] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing jolly example
PDCH[3] is used for UL
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
PDCH[4] is used for UL
PDCH[3] is control_ts for UL
PDCH[3] is first common for UL
PDCH[1] is used for DL
PDCH[2] is used for DL
PDCH[3] is used for DL
PDCH[4] is used for DL
PDCH[3] is control_ts for DL
PDCH[3] is first common for DL
Going to test multislot assignment MS_CLASS=45
Testing UL then DL assignment.
PDCH[6] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing DL then UL assignment followed by update
PDCH[6] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
PDCH[6] is used for UL
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
PDCH[7] is used for UL
PDCH[6] is control_ts for UL
PDCH[6] is first common for UL
PDCH[5] is used for DL
PDCH[6] is used for DL
PDCH[7] is used for DL
PDCH[6] is control_ts for DL
PDCH[6] is first common for DL
Testing jolly example
PDCH[3] is used for UL
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
PDCH[4] is used for UL
PDCH[3] is control_ts for UL
PDCH[3] is first common for UL
PDCH[1] is used for DL
PDCH[2] is used for DL
PDCH[3] is used for DL
PDCH[4] is used for DL
PDCH[3] is control_ts for DL
PDCH[3] is first common for DL
Mass test: TS0(xxxxxxxO)TS7 MS_Class=0
Mass test: TS0(xxxxxxxO)TS7 MS_Class=1
Mass test: TS0(xxxxxxxO)TS7 MS_Class=2
Mass test: TS0(xxxxxxxO)TS7 MS_Class=3
Mass test: TS0(xxxxxxxO)TS7 MS_Class=4
Mass test: TS0(xxxxxxxO)TS7 MS_Class=5
Mass test: TS0(xxxxxxxO)TS7 MS_Class=6
Mass test: TS0(xxxxxxxO)TS7 MS_Class=7
Mass test: TS0(xxxxxxxO)TS7 MS_Class=8
Mass test: TS0(xxxxxxxO)TS7 MS_Class=9
Mass test: TS0(xxxxxxxO)TS7 MS_Class=10
Mass test: TS0(xxxxxxxO)TS7 MS_Class=11
Mass test: TS0(xxxxxxxO)TS7 MS_Class=12
Mass test: TS0(xxxxxxxO)TS7 MS_Class=13
Mass test: TS0(xxxxxxxO)TS7 MS_Class=14
Mass test: TS0(xxxxxxxO)TS7 MS_Class=15
Mass test: TS0(xxxxxxxO)TS7 MS_Class=16
Mass test: TS0(xxxxxxxO)TS7 MS_Class=17
Mass test: TS0(xxxxxxxO)TS7 MS_Class=18
Mass test: TS0(xxxxxxxO)TS7 MS_Class=19
Mass test: TS0(xxxxxxxO)TS7 MS_Class=20
Mass test: TS0(xxxxxxxO)TS7 MS_Class=21
Mass test: TS0(xxxxxxxO)TS7 MS_Class=22
Mass test: TS0(xxxxxxxO)TS7 MS_Class=23
Mass test: TS0(xxxxxxxO)TS7 MS_Class=24
Mass test: TS0(xxxxxxxO)TS7 MS_Class=25
Mass test: TS0(xxxxxxxO)TS7 MS_Class=26
Mass test: TS0(xxxxxxxO)TS7 MS_Class=27
Mass test: TS0(xxxxxxxO)TS7 MS_Class=28
Mass test: TS0(xxxxxxxO)TS7 MS_Class=29
Mass test: TS0(xxxxxxxO)TS7 MS_Class=30
Mass test: TS0(xxxxxxxO)TS7 MS_Class=31
Mass test: TS0(xxxxxxxO)TS7 MS_Class=32
Mass test: TS0(xxxxxxxO)TS7 MS_Class=33
Mass test: TS0(xxxxxxxO)TS7 MS_Class=34
Mass test: TS0(xxxxxxxO)TS7 MS_Class=35
Mass test: TS0(xxxxxxxO)TS7 MS_Class=36
Mass test: TS0(xxxxxxxO)TS7 MS_Class=37
Mass test: TS0(xxxxxxxO)TS7 MS_Class=38
Mass test: TS0(xxxxxxxO)TS7 MS_Class=39
Mass test: TS0(xxxxxxxO)TS7 MS_Class=40
Mass test: TS0(xxxxxxxO)TS7 MS_Class=41
Mass test: TS0(xxxxxxxO)TS7 MS_Class=42
Mass test: TS0(xxxxxxxO)TS7 MS_Class=43
Mass test: TS0(xxxxxxxO)TS7 MS_Class=44
Mass test: TS0(xxxxxxxO)TS7 MS_Class=45
Mass test: TS0(xxxxxxOx)TS7 MS_Class=0
Mass test: TS0(xxxxxxOx)TS7 MS_Class=1
Mass test: TS0(xxxxxxOx)TS7 MS_Class=2
Mass test: TS0(xxxxxxOx)TS7 MS_Class=3
Mass test: TS0(xxxxxxOx)TS7 MS_Class=4
Mass test: TS0(xxxxxxOx)TS7 MS_Class=5
Mass test: TS0(xxxxxxOx)TS7 MS_Class=6
Mass test: TS0(xxxxxxOx)TS7 MS_Class=7
Mass test: TS0(xxxxxxOx)TS7 MS_Class=8
Mass test: TS0(xxxxxxOx)TS7 MS_Class=9
Mass test: TS0(xxxxxxOx)TS7 MS_Class=10
Mass test: TS0(xxxxxxOx)TS7 MS_Class=11
Mass test: TS0(xxxxxxOx)TS7 MS_Class=12
Mass test: TS0(xxxxxxOx)TS7 MS_Class=13
Mass test: TS0(xxxxxxOx)TS7 MS_Class=14
Mass test: TS0(xxxxxxOx)TS7 MS_Class=15
Mass test: TS0(xxxxxxOx)TS7 MS_Class=16
Mass test: TS0(xxxxxxOx)TS7 MS_Class=17
Mass test: TS0(xxxxxxOx)TS7 MS_Class=18
Mass test: TS0(xxxxxxOx)TS7 MS_Class=19
Mass test: TS0(xxxxxxOx)TS7 MS_Class=20
Mass test: TS0(xxxxxxOx)TS7 MS_Class=21
Mass test: TS0(xxxxxxOx)TS7 MS_Class=22
Mass test: TS0(xxxxxxOx)TS7 MS_Class=23
Mass test: TS0(xxxxxxOx)TS7 MS_Class=24
Mass test: TS0(xxxxxxOx)TS7 MS_Class=25
Mass test: TS0(xxxxxxOx)TS7 MS_Class=26
Mass test: TS0(xxxxxxOx)TS7 MS_Class=27
Mass test: TS0(xxxxxxOx)TS7 MS_Class=28
Mass test: TS0(xxxxxxOx)TS7 MS_Class=29
Mass test: TS0(xxxxxxOx)TS7 MS_Class=30
Mass test: TS0(xxxxxxOx)TS7 MS_Class=31
Mass test: TS0(xxxxxxOx)TS7 MS_Class=32
Mass test: TS0(xxxxxxOx)TS7 MS_Class=33
Mass test: TS0(xxxxxxOx)TS7 MS_Class=34
Mass test: TS0(xxxxxxOx)TS7 MS_Class=35
Mass test: TS0(xxxxxxOx)TS7 MS_Class=36
Mass test: TS0(xxxxxxOx)TS7 MS_Class=37
Mass test: TS0(xxxxxxOx)TS7 MS_Class=38
Mass test: TS0(xxxxxxOx)TS7 MS_Class=39
Mass test: TS0(xxxxxxOx)TS7 MS_Class=40
Mass test: TS0(xxxxxxOx)TS7 MS_Class=41
Mass test: TS0(xxxxxxOx)TS7 MS_Class=42
Mass test: TS0(xxxxxxOx)TS7 MS_Class=43
Mass test: TS0(xxxxxxOx)TS7 MS_Class=44
Mass test: TS0(xxxxxxOx)TS7 MS_Class=45
Mass test: TS0(xxxxxxOO)TS7 MS_Class=0
Mass test: TS0(xxxxxxOO)TS7 MS_Class=1
Mass test: TS0(xxxxxxOO)TS7 MS_Class=2
Mass test: TS0(xxxxxxOO)TS7 MS_Class=3
Mass test: TS0(xxxxxxOO)TS7 MS_Class=4
Mass test: TS0(xxxxxxOO)TS7 MS_Class=5
Mass test: TS0(xxxxxxOO)TS7 MS_Class=6
Mass test: TS0(xxxxxxOO)TS7 MS_Class=7
Mass test: TS0(xxxxxxOO)TS7 MS_Class=8
Mass test: TS0(xxxxxxOO)TS7 MS_Class=9
Mass test: TS0(xxxxxxOO)TS7 MS_Class=10
Mass test: TS0(xxxxxxOO)TS7 MS_Class=11
Mass test: TS0(xxxxxxOO)TS7 MS_Class=12
Mass test: TS0(xxxxxxOO)TS7 MS_Class=13
Mass test: TS0(xxxxxxOO)TS7 MS_Class=14
Mass test: TS0(xxxxxxOO)TS7 MS_Class=15
Mass test: TS0(xxxxxxOO)TS7 MS_Class=16
Mass test: TS0(xxxxxxOO)TS7 MS_Class=17
Mass test: TS0(xxxxxxOO)TS7 MS_Class=18
Mass test: TS0(xxxxxxOO)TS7 MS_Class=19
Mass test: TS0(xxxxxxOO)TS7 MS_Class=20
Mass test: TS0(xxxxxxOO)TS7 MS_Class=21
Mass test: TS0(xxxxxxOO)TS7 MS_Class=22
Mass test: TS0(xxxxxxOO)TS7 MS_Class=23
Mass test: TS0(xxxxxxOO)TS7 MS_Class=24
Mass test: TS0(xxxxxxOO)TS7 MS_Class=25
Mass test: TS0(xxxxxxOO)TS7 MS_Class=26
Mass test: TS0(xxxxxxOO)TS7 MS_Class=27
Mass test: TS0(xxxxxxOO)TS7 MS_Class=28
Mass test: TS0(xxxxxxOO)TS7 MS_Class=29
Mass test: TS0(xxxxxxOO)TS7 MS_Class=30
Mass test: TS0(xxxxxxOO)TS7 MS_Class=31
Mass test: TS0(xxxxxxOO)TS7 MS_Class=32
Mass test: TS0(xxxxxxOO)TS7 MS_Class=33
Mass test: TS0(xxxxxxOO)TS7 MS_Class=34
Mass test: TS0(xxxxxxOO)TS7 MS_Class=35
Mass test: TS0(xxxxxxOO)TS7 MS_Class=36
Mass test: TS0(xxxxxxOO)TS7 MS_Class=37
Mass test: TS0(xxxxxxOO)TS7 MS_Class=38
Mass test: TS0(xxxxxxOO)TS7 MS_Class=39
Mass test: TS0(xxxxxxOO)TS7 MS_Class=40
Mass test: TS0(xxxxxxOO)TS7 MS_Class=41
Mass test: TS0(xxxxxxOO)TS7 MS_Class=42
Mass test: TS0(xxxxxxOO)TS7 MS_Class=43
Mass test: TS0(xxxxxxOO)TS7 MS_Class=44
Mass test: TS0(xxxxxxOO)TS7 MS_Class=45
Mass test: TS0(xxxxxOxx)TS7 MS_Class=0
Mass test: TS0(xxxxxOxx)TS7 MS_Class=1
Mass test: TS0(xxxxxOxx)TS7 MS_Class=2
Mass test: TS0(xxxxxOxx)TS7 MS_Class=3
Mass test: TS0(xxxxxOxx)TS7 MS_Class=4
Mass test: TS0(xxxxxOxx)TS7 MS_Class=5
Mass test: TS0(xxxxxOxx)TS7 MS_Class=6
Mass test: TS0(xxxxxOxx)TS7 MS_Class=7
Mass test: TS0(xxxxxOxx)TS7 MS_Class=8
Mass test: TS0(xxxxxOxx)TS7 MS_Class=9
Mass test: TS0(xxxxxOxx)TS7 MS_Class=10
Mass test: TS0(xxxxxOxx)TS7 MS_Class=11
Mass test: TS0(xxxxxOxx)TS7 MS_Class=12
Mass test: TS0(xxxxxOxx)TS7 MS_Class=13
Mass test: TS0(xxxxxOxx)TS7 MS_Class=14
Mass test: TS0(xxxxxOxx)TS7 MS_Class=15
Mass test: TS0(xxxxxOxx)TS7 MS_Class=16
Mass test: TS0(xxxxxOxx)TS7 MS_Class=17
Mass test: TS0(xxxxxOxx)TS7 MS_Class=18
Mass test: TS0(xxxxxOxx)TS7 MS_Class=19
Mass test: TS0(xxxxxOxx)TS7 MS_Class=20
Mass test: TS0(xxxxxOxx)TS7 MS_Class=21
Mass test: TS0(xxxxxOxx)TS7 MS_Class=22
Mass test: TS0(xxxxxOxx)TS7 MS_Class=23
Mass test: TS0(xxxxxOxx)TS7 MS_Class=24
Mass test: TS0(xxxxxOxx)TS7 MS_Class=25
Mass test: TS0(xxxxxOxx)TS7 MS_Class=26
Mass test: TS0(xxxxxOxx)TS7 MS_Class=27
Mass test: TS0(xxxxxOxx)TS7 MS_Class=28
Mass test: TS0(xxxxxOxx)TS7 MS_Class=29
Mass test: TS0(xxxxxOxx)TS7 MS_Class=30
Mass test: TS0(xxxxxOxx)TS7 MS_Class=31
Mass test: TS0(xxxxxOxx)TS7 MS_Class=32
Mass test: TS0(xxxxxOxx)TS7 MS_Class=33
Mass test: TS0(xxxxxOxx)TS7 MS_Class=34
Mass test: TS0(xxxxxOxx)TS7 MS_Class=35
Mass test: TS0(xxxxxOxx)TS7 MS_Class=36
Mass test: TS0(xxxxxOxx)TS7 MS_Class=37
Mass test: TS0(xxxxxOxx)TS7 MS_Class=38
Mass test: TS0(xxxxxOxx)TS7 MS_Class=39
Mass test: TS0(xxxxxOxx)TS7 MS_Class=40
Mass test: TS0(xxxxxOxx)TS7 MS_Class=41
Mass test: TS0(xxxxxOxx)TS7 MS_Class=42
Mass test: TS0(xxxxxOxx)TS7 MS_Class=43
Mass test: TS0(xxxxxOxx)TS7 MS_Class=44
Mass test: TS0(xxxxxOxx)TS7 MS_Class=45
Mass test: TS0(xxxxxOxO)TS7 MS_Class=0
Mass test: TS0(xxxxxOxO)TS7 MS_Class=1
Mass test: TS0(xxxxxOxO)TS7 MS_Class=2
Mass test: TS0(xxxxxOxO)TS7 MS_Class=3
Mass test: TS0(xxxxxOxO)TS7 MS_Class=4
Mass test: TS0(xxxxxOxO)TS7 MS_Class=5
Mass test: TS0(xxxxxOxO)TS7 MS_Class=6
Mass test: TS0(xxxxxOxO)TS7 MS_Class=7
Mass test: TS0(xxxxxOxO)TS7 MS_Class=8
Mass test: TS0(xxxxxOxO)TS7 MS_Class=9
Mass test: TS0(xxxxxOxO)TS7 MS_Class=10
Mass test: TS0(xxxxxOxO)TS7 MS_Class=11
Mass test: TS0(xxxxxOxO)TS7 MS_Class=12
Mass test: TS0(xxxxxOxO)TS7 MS_Class=13
Mass test: TS0(xxxxxOxO)TS7 MS_Class=14
Mass test: TS0(xxxxxOxO)TS7 MS_Class=15
Mass test: TS0(xxxxxOxO)TS7 MS_Class=16
Mass test: TS0(xxxxxOxO)TS7 MS_Class=17
Mass test: TS0(xxxxxOxO)TS7 MS_Class=18
Mass test: TS0(xxxxxOxO)TS7 MS_Class=19
Mass test: TS0(xxxxxOxO)TS7 MS_Class=20
Mass test: TS0(xxxxxOxO)TS7 MS_Class=21
Mass test: TS0(xxxxxOxO)TS7 MS_Class=22
Mass test: TS0(xxxxxOxO)TS7 MS_Class=23
Mass test: TS0(xxxxxOxO)TS7 MS_Class=24
Mass test: TS0(xxxxxOxO)TS7 MS_Class=25
Mass test: TS0(xxxxxOxO)TS7 MS_Class=26
Mass test: TS0(xxxxxOxO)TS7 MS_Class=27
Mass test: TS0(xxxxxOxO)TS7 MS_Class=28
Mass test: TS0(xxxxxOxO)TS7 MS_Class=29
Mass test: TS0(xxxxxOxO)TS7 MS_Class=30
Mass test: TS0(xxxxxOxO)TS7 MS_Class=31
Mass test: TS0(xxxxxOxO)TS7 MS_Class=32
Mass test: TS0(xxxxxOxO)TS7 MS_Class=33
Mass test: TS0(xxxxxOxO)TS7 MS_Class=34
Mass test: TS0(xxxxxOxO)TS7 MS_Class=35
Mass test: TS0(xxxxxOxO)TS7 MS_Class=36
Mass test: TS0(xxxxxOxO)TS7 MS_Class=37
Mass test: TS0(xxxxxOxO)TS7 MS_Class=38
Mass test: TS0(xxxxxOxO)TS7 MS_Class=39
Mass test: TS0(xxxxxOxO)TS7 MS_Class=40
Mass test: TS0(xxxxxOxO)TS7 MS_Class=41
Mass test: TS0(xxxxxOxO)TS7 MS_Class=42
Mass test: TS0(xxxxxOxO)TS7 MS_Class=43
Mass test: TS0(xxxxxOxO)TS7 MS_Class=44
Mass test: TS0(xxxxxOxO)TS7 MS_Class=45
Mass test: TS0(xxxxxOOx)TS7 MS_Class=0
Mass test: TS0(xxxxxOOx)TS7 MS_Class=1
Mass test: TS0(xxxxxOOx)TS7 MS_Class=2
Mass test: TS0(xxxxxOOx)TS7 MS_Class=3
Mass test: TS0(xxxxxOOx)TS7 MS_Class=4
Mass test: TS0(xxxxxOOx)TS7 MS_Class=5
Mass test: TS0(xxxxxOOx)TS7 MS_Class=6
Mass test: TS0(xxxxxOOx)TS7 MS_Class=7
Mass test: TS0(xxxxxOOx)TS7 MS_Class=8
Mass test: TS0(xxxxxOOx)TS7 MS_Class=9
Mass test: TS0(xxxxxOOx)TS7 MS_Class=10
Mass test: TS0(xxxxxOOx)TS7 MS_Class=11
Mass test: TS0(xxxxxOOx)TS7 MS_Class=12
Mass test: TS0(xxxxxOOx)TS7 MS_Class=13
Mass test: TS0(xxxxxOOx)TS7 MS_Class=14
Mass test: TS0(xxxxxOOx)TS7 MS_Class=15
Mass test: TS0(xxxxxOOx)TS7 MS_Class=16
Mass test: TS0(xxxxxOOx)TS7 MS_Class=17
Mass test: TS0(xxxxxOOx)TS7 MS_Class=18
Mass test: TS0(xxxxxOOx)TS7 MS_Class=19
Mass test: TS0(xxxxxOOx)TS7 MS_Class=20
Mass test: TS0(xxxxxOOx)TS7 MS_Class=21
Mass test: TS0(xxxxxOOx)TS7 MS_Class=22
Mass test: TS0(xxxxxOOx)TS7 MS_Class=23
Mass test: TS0(xxxxxOOx)TS7 MS_Class=24
Mass test: TS0(xxxxxOOx)TS7 MS_Class=25
Mass test: TS0(xxxxxOOx)TS7 MS_Class=26
Mass test: TS0(xxxxxOOx)TS7 MS_Class=27
Mass test: TS0(xxxxxOOx)TS7 MS_Class=28
Mass test: TS0(xxxxxOOx)TS7 MS_Class=29
Mass test: TS0(xxxxxOOx)TS7 MS_Class=30
Mass test: TS0(xxxxxOOx)TS7 MS_Class=31
Mass test: TS0(xxxxxOOx)TS7 MS_Class=32
Mass test: TS0(xxxxxOOx)TS7 MS_Class=33
Mass test: TS0(xxxxxOOx)TS7 MS_Class=34
Mass test: TS0(xxxxxOOx)TS7 MS_Class=35
Mass test: TS0(xxxxxOOx)TS7 MS_Class=36
Mass test: TS0(xxxxxOOx)TS7 MS_Class=37
Mass test: TS0(xxxxxOOx)TS7 MS_Class=38
Mass test: TS0(xxxxxOOx)TS7 MS_Class=39
Mass test: TS0(xxxxxOOx)TS7 MS_Class=40
Mass test: TS0(xxxxxOOx)TS7 MS_Class=41
Mass test: TS0(xxxxxOOx)TS7 MS_Class=42
Mass test: TS0(xxxxxOOx)TS7 MS_Class=43
Mass test: TS0(xxxxxOOx)TS7 MS_Class=44
Mass test: TS0(xxxxxOOx)TS7 MS_Class=45
Mass test: TS0(xxxxxOOO)TS7 MS_Class=0
Mass test: TS0(xxxxxOOO)TS7 MS_Class=1
Mass test: TS0(xxxxxOOO)TS7 MS_Class=2
Mass test: TS0(xxxxxOOO)TS7 MS_Class=3
Mass test: TS0(xxxxxOOO)TS7 MS_Class=4
Mass test: TS0(xxxxxOOO)TS7 MS_Class=5
Mass test: TS0(xxxxxOOO)TS7 MS_Class=6
Mass test: TS0(xxxxxOOO)TS7 MS_Class=7
Mass test: TS0(xxxxxOOO)TS7 MS_Class=8
Mass test: TS0(xxxxxOOO)TS7 MS_Class=9
Mass test: TS0(xxxxxOOO)TS7 MS_Class=10
Mass test: TS0(xxxxxOOO)TS7 MS_Class=11
Mass test: TS0(xxxxxOOO)TS7 MS_Class=12
Mass test: TS0(xxxxxOOO)TS7 MS_Class=13
Mass test: TS0(xxxxxOOO)TS7 MS_Class=14
Mass test: TS0(xxxxxOOO)TS7 MS_Class=15
Mass test: TS0(xxxxxOOO)TS7 MS_Class=16
Mass test: TS0(xxxxxOOO)TS7 MS_Class=17
Mass test: TS0(xxxxxOOO)TS7 MS_Class=18
Mass test: TS0(xxxxxOOO)TS7 MS_Class=19
Mass test: TS0(xxxxxOOO)TS7 MS_Class=20
Mass test: TS0(xxxxxOOO)TS7 MS_Class=21
Mass test: TS0(xxxxxOOO)TS7 MS_Class=22
Mass test: TS0(xxxxxOOO)TS7 MS_Class=23
Mass test: TS0(xxxxxOOO)TS7 MS_Class=24
Mass test: TS0(xxxxxOOO)TS7 MS_Class=25
Mass test: TS0(xxxxxOOO)TS7 MS_Class=26
Mass test: TS0(xxxxxOOO)TS7 MS_Class=27
Mass test: TS0(xxxxxOOO)TS7 MS_Class=28
Mass test: TS0(xxxxxOOO)TS7 MS_Class=29
Mass test: TS0(xxxxxOOO)TS7 MS_Class=30
Mass test: TS0(xxxxxOOO)TS7 MS_Class=31
Mass test: TS0(xxxxxOOO)TS7 MS_Class=32
Mass test: TS0(xxxxxOOO)TS7 MS_Class=33
Mass test: TS0(xxxxxOOO)TS7 MS_Class=34
Mass test: TS0(xxxxxOOO)TS7 MS_Class=35
Mass test: TS0(xxxxxOOO)TS7 MS_Class=36
Mass test: TS0(xxxxxOOO)TS7 MS_Class=37
Mass test: TS0(xxxxxOOO)TS7 MS_Class=38
Mass test: TS0(xxxxxOOO)TS7 MS_Class=39
Mass test: TS0(xxxxxOOO)TS7 MS_Class=40
Mass test: TS0(xxxxxOOO)TS7 MS_Class=41
Mass test: TS0(xxxxxOOO)TS7 MS_Class=42
Mass test: TS0(xxxxxOOO)TS7 MS_Class=43
Mass test: TS0(xxxxxOOO)TS7 MS_Class=44
Mass test: TS0(xxxxxOOO)TS7 MS_Class=45
Mass test: TS0(xxxxOxxx)TS7 MS_Class=0
Mass test: TS0(xxxxOxxx)TS7 MS_Class=1
Mass test: TS0(xxxxOxxx)TS7 MS_Class=2
Mass test: TS0(xxxxOxxx)TS7 MS_Class=3
Mass test: TS0(xxxxOxxx)TS7 MS_Class=4
Mass test: TS0(xxxxOxxx)TS7 MS_Class=5
Mass test: TS0(xxxxOxxx)TS7 MS_Class=6
Mass test: TS0(xxxxOxxx)TS7 MS_Class=7
Mass test: TS0(xxxxOxxx)TS7 MS_Class=8
Mass test: TS0(xxxxOxxx)TS7 MS_Class=9
Mass test: TS0(xxxxOxxx)TS7 MS_Class=10
Mass test: TS0(xxxxOxxx)TS7 MS_Class=11
Mass test: TS0(xxxxOxxx)TS7 MS_Class=12
Mass test: TS0(xxxxOxxx)TS7 MS_Class=13
Mass test: TS0(xxxxOxxx)TS7 MS_Class=14
Mass test: TS0(xxxxOxxx)TS7 MS_Class=15
Mass test: TS0(xxxxOxxx)TS7 MS_Class=16
Mass test: TS0(xxxxOxxx)TS7 MS_Class=17
Mass test: TS0(xxxxOxxx)TS7 MS_Class=18
Mass test: TS0(xxxxOxxx)TS7 MS_Class=19
Mass test: TS0(xxxxOxxx)TS7 MS_Class=20
Mass test: TS0(xxxxOxxx)TS7 MS_Class=21
Mass test: TS0(xxxxOxxx)TS7 MS_Class=22
Mass test: TS0(xxxxOxxx)TS7 MS_Class=23
Mass test: TS0(xxxxOxxx)TS7 MS_Class=24
Mass test: TS0(xxxxOxxx)TS7 MS_Class=25
Mass test: TS0(xxxxOxxx)TS7 MS_Class=26
Mass test: TS0(xxxxOxxx)TS7 MS_Class=27
Mass test: TS0(xxxxOxxx)TS7 MS_Class=28
Mass test: TS0(xxxxOxxx)TS7 MS_Class=29
Mass test: TS0(xxxxOxxx)TS7 MS_Class=30
Mass test: TS0(xxxxOxxx)TS7 MS_Class=31
Mass test: TS0(xxxxOxxx)TS7 MS_Class=32
Mass test: TS0(xxxxOxxx)TS7 MS_Class=33
Mass test: TS0(xxxxOxxx)TS7 MS_Class=34
Mass test: TS0(xxxxOxxx)TS7 MS_Class=35
Mass test: TS0(xxxxOxxx)TS7 MS_Class=36
Mass test: TS0(xxxxOxxx)TS7 MS_Class=37
Mass test: TS0(xxxxOxxx)TS7 MS_Class=38
Mass test: TS0(xxxxOxxx)TS7 MS_Class=39
Mass test: TS0(xxxxOxxx)TS7 MS_Class=40
Mass test: TS0(xxxxOxxx)TS7 MS_Class=41
Mass test: TS0(xxxxOxxx)TS7 MS_Class=42
Mass test: TS0(xxxxOxxx)TS7 MS_Class=43
Mass test: TS0(xxxxOxxx)TS7 MS_Class=44
Mass test: TS0(xxxxOxxx)TS7 MS_Class=45
Mass test: TS0(xxxxOxxO)TS7 MS_Class=0
Mass test: TS0(xxxxOxxO)TS7 MS_Class=1
Mass test: TS0(xxxxOxxO)TS7 MS_Class=2
Mass test: TS0(xxxxOxxO)TS7 MS_Class=3
Mass test: TS0(xxxxOxxO)TS7 MS_Class=4
Mass test: TS0(xxxxOxxO)TS7 MS_Class=5
Mass test: TS0(xxxxOxxO)TS7 MS_Class=6
Mass test: TS0(xxxxOxxO)TS7 MS_Class=7
Mass test: TS0(xxxxOxxO)TS7 MS_Class=8
Mass test: TS0(xxxxOxxO)TS7 MS_Class=9
Mass test: TS0(xxxxOxxO)TS7 MS_Class=10
Mass test: TS0(xxxxOxxO)TS7 MS_Class=11
Mass test: TS0(xxxxOxxO)TS7 MS_Class=12
Mass test: TS0(xxxxOxxO)TS7 MS_Class=13
Mass test: TS0(xxxxOxxO)TS7 MS_Class=14
Mass test: TS0(xxxxOxxO)TS7 MS_Class=15
Mass test: TS0(xxxxOxxO)TS7 MS_Class=16
Mass test: TS0(xxxxOxxO)TS7 MS_Class=17
Mass test: TS0(xxxxOxxO)TS7 MS_Class=18
Mass test: TS0(xxxxOxxO)TS7 MS_Class=19
Mass test: TS0(xxxxOxxO)TS7 MS_Class=20
Mass test: TS0(xxxxOxxO)TS7 MS_Class=21
Mass test: TS0(xxxxOxxO)TS7 MS_Class=22
Mass test: TS0(xxxxOxxO)TS7 MS_Class=23
Mass test: TS0(xxxxOxxO)TS7 MS_Class=24
Mass test: TS0(xxxxOxxO)TS7 MS_Class=25
Mass test: TS0(xxxxOxxO)TS7 MS_Class=26
Mass test: TS0(xxxxOxxO)TS7 MS_Class=27
Mass test: TS0(xxxxOxxO)TS7 MS_Class=28
Mass test: TS0(xxxxOxxO)TS7 MS_Class=29
Mass test: TS0(xxxxOxxO)TS7 MS_Class=30
Mass test: TS0(xxxxOxxO)TS7 MS_Class=31
Mass test: TS0(xxxxOxxO)TS7 MS_Class=32
Mass test: TS0(xxxxOxxO)TS7 MS_Class=33
Mass test: TS0(xxxxOxxO)TS7 MS_Class=34
Mass test: TS0(xxxxOxxO)TS7 MS_Class=35
Mass test: TS0(xxxxOxxO)TS7 MS_Class=36
Mass test: TS0(xxxxOxxO)TS7 MS_Class=37
Mass test: TS0(xxxxOxxO)TS7 MS_Class=38
Mass test: TS0(xxxxOxxO)TS7 MS_Class=39
Mass test: TS0(xxxxOxxO)TS7 MS_Class=40
Mass test: TS0(xxxxOxxO)TS7 MS_Class=41
Mass test: TS0(xxxxOxxO)TS7 MS_Class=42
Mass test: TS0(xxxxOxxO)TS7 MS_Class=43
Mass test: TS0(xxxxOxxO)TS7 MS_Class=44
Mass test: TS0(xxxxOxxO)TS7 MS_Class=45
Mass test: TS0(xxxxOxOx)TS7 MS_Class=0
Mass test: TS0(xxxxOxOx)TS7 MS_Class=1
Mass test: TS0(xxxxOxOx)TS7 MS_Class=2
Mass test: TS0(xxxxOxOx)TS7 MS_Class=3
Mass test: TS0(xxxxOxOx)TS7 MS_Class=4
Mass test: TS0(xxxxOxOx)TS7 MS_Class=5
Mass test: TS0(xxxxOxOx)TS7 MS_Class=6
Mass test: TS0(xxxxOxOx)TS7 MS_Class=7
Mass test: TS0(xxxxOxOx)TS7 MS_Class=8
Mass test: TS0(xxxxOxOx)TS7 MS_Class=9
Mass test: TS0(xxxxOxOx)TS7 MS_Class=10
Mass test: TS0(xxxxOxOx)TS7 MS_Class=11
Mass test: TS0(xxxxOxOx)TS7 MS_Class=12
Mass test: TS0(xxxxOxOx)TS7 MS_Class=13
Mass test: TS0(xxxxOxOx)TS7 MS_Class=14
Mass test: TS0(xxxxOxOx)TS7 MS_Class=15
Mass test: TS0(xxxxOxOx)TS7 MS_Class=16
Mass test: TS0(xxxxOxOx)TS7 MS_Class=17
Mass test: TS0(xxxxOxOx)TS7 MS_Class=18
Mass test: TS0(xxxxOxOx)TS7 MS_Class=19
Mass test: TS0(xxxxOxOx)TS7 MS_Class=20
Mass test: TS0(xxxxOxOx)TS7 MS_Class=21
Mass test: TS0(xxxxOxOx)TS7 MS_Class=22
Mass test: TS0(xxxxOxOx)TS7 MS_Class=23
Mass test: TS0(xxxxOxOx)TS7 MS_Class=24
Mass test: TS0(xxxxOxOx)TS7 MS_Class=25
Mass test: TS0(xxxxOxOx)TS7 MS_Class=26
Mass test: TS0(xxxxOxOx)TS7 MS_Class=27
Mass test: TS0(xxxxOxOx)TS7 MS_Class=28
Mass test: TS0(xxxxOxOx)TS7 MS_Class=29
Mass test: TS0(xxxxOxOx)TS7 MS_Class=30
Mass test: TS0(xxxxOxOx)TS7 MS_Class=31
Mass test: TS0(xxxxOxOx)TS7 MS_Class=32
Mass test: TS0(xxxxOxOx)TS7 MS_Class=33
Mass test: TS0(xxxxOxOx)TS7 MS_Class=34
Mass test: TS0(xxxxOxOx)TS7 MS_Class=35
Mass test: TS0(xxxxOxOx)TS7 MS_Class=36
Mass test: TS0(xxxxOxOx)TS7 MS_Class=37
Mass test: TS0(xxxxOxOx)TS7 MS_Class=38
Mass test: TS0(xxxxOxOx)TS7 MS_Class=39
Mass test: TS0(xxxxOxOx)TS7 MS_Class=40
Mass test: TS0(xxxxOxOx)TS7 MS_Class=41
Mass test: TS0(xxxxOxOx)TS7 MS_Class=42
Mass test: TS0(xxxxOxOx)TS7 MS_Class=43
Mass test: TS0(xxxxOxOx)TS7 MS_Class=44
Mass test: TS0(xxxxOxOx)TS7 MS_Class=45
Mass test: TS0(xxxxOxOO)TS7 MS_Class=0
Mass test: TS0(xxxxOxOO)TS7 MS_Class=1
Mass test: TS0(xxxxOxOO)TS7 MS_Class=2
Mass test: TS0(xxxxOxOO)TS7 MS_Class=3
Mass test: TS0(xxxxOxOO)TS7 MS_Class=4
Mass test: TS0(xxxxOxOO)TS7 MS_Class=5
Mass test: TS0(xxxxOxOO)TS7 MS_Class=6
Mass test: TS0(xxxxOxOO)TS7 MS_Class=7
Mass test: TS0(xxxxOxOO)TS7 MS_Class=8
Mass test: TS0(xxxxOxOO)TS7 MS_Class=9
Mass test: TS0(xxxxOxOO)TS7 MS_Class=10
Mass test: TS0(xxxxOxOO)TS7 MS_Class=11
Mass test: TS0(xxxxOxOO)TS7 MS_Class=12
Mass test: TS0(xxxxOxOO)TS7 MS_Class=13
Mass test: TS0(xxxxOxOO)TS7 MS_Class=14
Mass test: TS0(xxxxOxOO)TS7 MS_Class=15
Mass test: TS0(xxxxOxOO)TS7 MS_Class=16
Mass test: TS0(xxxxOxOO)TS7 MS_Class=17
Mass test: TS0(xxxxOxOO)TS7 MS_Class=18
Mass test: TS0(xxxxOxOO)TS7 MS_Class=19
Mass test: TS0(xxxxOxOO)TS7 MS_Class=20
Mass test: TS0(xxxxOxOO)TS7 MS_Class=21
Mass test: TS0(xxxxOxOO)TS7 MS_Class=22
Mass test: TS0(xxxxOxOO)TS7 MS_Class=23
Mass test: TS0(xxxxOxOO)TS7 MS_Class=24
Mass test: TS0(xxxxOxOO)TS7 MS_Class=25
Mass test: TS0(xxxxOxOO)TS7 MS_Class=26
Mass test: TS0(xxxxOxOO)TS7 MS_Class=27
Mass test: TS0(xxxxOxOO)TS7 MS_Class=28
Mass test: TS0(xxxxOxOO)TS7 MS_Class=29
Mass test: TS0(xxxxOxOO)TS7 MS_Class=30
Mass test: TS0(xxxxOxOO)TS7 MS_Class=31
Mass test: TS0(xxxxOxOO)TS7 MS_Class=32
Mass test: TS0(xxxxOxOO)TS7 MS_Class=33
Mass test: TS0(xxxxOxOO)TS7 MS_Class=34
Mass test: TS0(xxxxOxOO)TS7 MS_Class=35
Mass test: TS0(xxxxOxOO)TS7 MS_Class=36
Mass test: TS0(xxxxOxOO)TS7 MS_Class=37
Mass test: TS0(xxxxOxOO)TS7 MS_Class=38
Mass test: TS0(xxxxOxOO)TS7 MS_Class=39
Mass test: TS0(xxxxOxOO)TS7 MS_Class=40
Mass test: TS0(xxxxOxOO)TS7 MS_Class=41
Mass test: TS0(xxxxOxOO)TS7 MS_Class=42
Mass test: TS0(xxxxOxOO)TS7 MS_Class=43
Mass test: TS0(xxxxOxOO)TS7 MS_Class=44
Mass test: TS0(xxxxOxOO)TS7 MS_Class=45
Mass test: TS0(xxxxOOxx)TS7 MS_Class=0
Mass test: TS0(xxxxOOxx)TS7 MS_Class=1
Mass test: TS0(xxxxOOxx)TS7 MS_Class=2
Mass test: TS0(xxxxOOxx)TS7 MS_Class=3
Mass test: TS0(xxxxOOxx)TS7 MS_Class=4
Mass test: TS0(xxxxOOxx)TS7 MS_Class=5
Mass test: TS0(xxxxOOxx)TS7 MS_Class=6
Mass test: TS0(xxxxOOxx)TS7 MS_Class=7
Mass test: TS0(xxxxOOxx)TS7 MS_Class=8
Mass test: TS0(xxxxOOxx)TS7 MS_Class=9
Mass test: TS0(xxxxOOxx)TS7 MS_Class=10
Mass test: TS0(xxxxOOxx)TS7 MS_Class=11
Mass test: TS0(xxxxOOxx)TS7 MS_Class=12
Mass test: TS0(xxxxOOxx)TS7 MS_Class=13
Mass test: TS0(xxxxOOxx)TS7 MS_Class=14
Mass test: TS0(xxxxOOxx)TS7 MS_Class=15
Mass test: TS0(xxxxOOxx)TS7 MS_Class=16
Mass test: TS0(xxxxOOxx)TS7 MS_Class=17
Mass test: TS0(xxxxOOxx)TS7 MS_Class=18
Mass test: TS0(xxxxOOxx)TS7 MS_Class=19
Mass test: TS0(xxxxOOxx)TS7 MS_Class=20
Mass test: TS0(xxxxOOxx)TS7 MS_Class=21
Mass test: TS0(xxxxOOxx)TS7 MS_Class=22
Mass test: TS0(xxxxOOxx)TS7 MS_Class=23
Mass test: TS0(xxxxOOxx)TS7 MS_Class=24
Mass test: TS0(xxxxOOxx)TS7 MS_Class=25
Mass test: TS0(xxxxOOxx)TS7 MS_Class=26
Mass test: TS0(xxxxOOxx)TS7 MS_Class=27
Mass test: TS0(xxxxOOxx)TS7 MS_Class=28
Mass test: TS0(xxxxOOxx)TS7 MS_Class=29
Mass test: TS0(xxxxOOxx)TS7 MS_Class=30
Mass test: TS0(xxxxOOxx)TS7 MS_Class=31
Mass test: TS0(xxxxOOxx)TS7 MS_Class=32
Mass test: TS0(xxxxOOxx)TS7 MS_Class=33
Mass test: TS0(xxxxOOxx)TS7 MS_Class=34
Mass test: TS0(xxxxOOxx)TS7 MS_Class=35
Mass test: TS0(xxxxOOxx)TS7 MS_Class=36
Mass test: TS0(xxxxOOxx)TS7 MS_Class=37
Mass test: TS0(xxxxOOxx)TS7 MS_Class=38
Mass test: TS0(xxxxOOxx)TS7 MS_Class=39
Mass test: TS0(xxxxOOxx)TS7 MS_Class=40
Mass test: TS0(xxxxOOxx)TS7 MS_Class=41
Mass test: TS0(xxxxOOxx)TS7 MS_Class=42
Mass test: TS0(xxxxOOxx)TS7 MS_Class=43
Mass test: TS0(xxxxOOxx)TS7 MS_Class=44
Mass test: TS0(xxxxOOxx)TS7 MS_Class=45
Mass test: TS0(xxxxOOxO)TS7 MS_Class=0
Mass test: TS0(xxxxOOxO)TS7 MS_Class=1
Mass test: TS0(xxxxOOxO)TS7 MS_Class=2
Mass test: TS0(xxxxOOxO)TS7 MS_Class=3
Mass test: TS0(xxxxOOxO)TS7 MS_Class=4
Mass test: TS0(xxxxOOxO)TS7 MS_Class=5
Mass test: TS0(xxxxOOxO)TS7 MS_Class=6
Mass test: TS0(xxxxOOxO)TS7 MS_Class=7
Mass test: TS0(xxxxOOxO)TS7 MS_Class=8
Mass test: TS0(xxxxOOxO)TS7 MS_Class=9
Mass test: TS0(xxxxOOxO)TS7 MS_Class=10
Mass test: TS0(xxxxOOxO)TS7 MS_Class=11
Mass test: TS0(xxxxOOxO)TS7 MS_Class=12
Mass test: TS0(xxxxOOxO)TS7 MS_Class=13
Mass test: TS0(xxxxOOxO)TS7 MS_Class=14
Mass test: TS0(xxxxOOxO)TS7 MS_Class=15
Mass test: TS0(xxxxOOxO)TS7 MS_Class=16
Mass test: TS0(xxxxOOxO)TS7 MS_Class=17
Mass test: TS0(xxxxOOxO)TS7 MS_Class=18
Mass test: TS0(xxxxOOxO)TS7 MS_Class=19
Mass test: TS0(xxxxOOxO)TS7 MS_Class=20
Mass test: TS0(xxxxOOxO)TS7 MS_Class=21
Mass test: TS0(xxxxOOxO)TS7 MS_Class=22
Mass test: TS0(xxxxOOxO)TS7 MS_Class=23
Mass test: TS0(xxxxOOxO)TS7 MS_Class=24
Mass test: TS0(xxxxOOxO)TS7 MS_Class=25
Mass test: TS0(xxxxOOxO)TS7 MS_Class=26
Mass test: TS0(xxxxOOxO)TS7 MS_Class=27
Mass test: TS0(xxxxOOxO)TS7 MS_Class=28
Mass test: TS0(xxxxOOxO)TS7 MS_Class=29
Mass test: TS0(xxxxOOxO)TS7 MS_Class=30
Mass test: TS0(xxxxOOxO)TS7 MS_Class=31
Mass test: TS0(xxxxOOxO)TS7 MS_Class=32
Mass test: TS0(xxxxOOxO)TS7 MS_Class=33
Mass test: TS0(xxxxOOxO)TS7 MS_Class=34
Mass test: TS0(xxxxOOxO)TS7 MS_Class=35
Mass test: TS0(xxxxOOxO)TS7 MS_Class=36
Mass test: TS0(xxxxOOxO)TS7 MS_Class=37
Mass test: TS0(xxxxOOxO)TS7 MS_Class=38
Mass test: TS0(xxxxOOxO)TS7 MS_Class=39
Mass test: TS0(xxxxOOxO)TS7 MS_Class=40
Mass test: TS0(xxxxOOxO)TS7 MS_Class=41
Mass test: TS0(xxxxOOxO)TS7 MS_Class=42
Mass test: TS0(xxxxOOxO)TS7 MS_Class=43
Mass test: TS0(xxxxOOxO)TS7 MS_Class=44
Mass test: TS0(xxxxOOxO)TS7 MS_Class=45
Mass test: TS0(xxxxOOOx)TS7 MS_Class=0
Mass test: TS0(xxxxOOOx)TS7 MS_Class=1
Mass test: TS0(xxxxOOOx)TS7 MS_Class=2
Mass test: TS0(xxxxOOOx)TS7 MS_Class=3
Mass test: TS0(xxxxOOOx)TS7 MS_Class=4
Mass test: TS0(xxxxOOOx)TS7 MS_Class=5
Mass test: TS0(xxxxOOOx)TS7 MS_Class=6
Mass test: TS0(xxxxOOOx)TS7 MS_Class=7
Mass test: TS0(xxxxOOOx)TS7 MS_Class=8
Mass test: TS0(xxxxOOOx)TS7 MS_Class=9
Mass test: TS0(xxxxOOOx)TS7 MS_Class=10
Mass test: TS0(xxxxOOOx)TS7 MS_Class=11
Mass test: TS0(xxxxOOOx)TS7 MS_Class=12
Mass test: TS0(xxxxOOOx)TS7 MS_Class=13
Mass test: TS0(xxxxOOOx)TS7 MS_Class=14
Mass test: TS0(xxxxOOOx)TS7 MS_Class=15
Mass test: TS0(xxxxOOOx)TS7 MS_Class=16
Mass test: TS0(xxxxOOOx)TS7 MS_Class=17
Mass test: TS0(xxxxOOOx)TS7 MS_Class=18
Mass test: TS0(xxxxOOOx)TS7 MS_Class=19
Mass test: TS0(xxxxOOOx)TS7 MS_Class=20
Mass test: TS0(xxxxOOOx)TS7 MS_Class=21
Mass test: TS0(xxxxOOOx)TS7 MS_Class=22
Mass test: TS0(xxxxOOOx)TS7 MS_Class=23
Mass test: TS0(xxxxOOOx)TS7 MS_Class=24
Mass test: TS0(xxxxOOOx)TS7 MS_Class=25
Mass test: TS0(xxxxOOOx)TS7 MS_Class=26
Mass test: TS0(xxxxOOOx)TS7 MS_Class=27
Mass test: TS0(xxxxOOOx)TS7 MS_Class=28
Mass test: TS0(xxxxOOOx)TS7 MS_Class=29
Mass test: TS0(xxxxOOOx)TS7 MS_Class=30
Mass test: TS0(xxxxOOOx)TS7 MS_Class=31
Mass test: TS0(xxxxOOOx)TS7 MS_Class=32
Mass test: TS0(xxxxOOOx)TS7 MS_Class=33
Mass test: TS0(xxxxOOOx)TS7 MS_Class=34
Mass test: TS0(xxxxOOOx)TS7 MS_Class=35
Mass test: TS0(xxxxOOOx)TS7 MS_Class=36
Mass test: TS0(xxxxOOOx)TS7 MS_Class=37
Mass test: TS0(xxxxOOOx)TS7 MS_Class=38
Mass test: TS0(xxxxOOOx)TS7 MS_Class=39
Mass test: TS0(xxxxOOOx)TS7 MS_Class=40
Mass test: TS0(xxxxOOOx)TS7 MS_Class=41
Mass test: TS0(xxxxOOOx)TS7 MS_Class=42
Mass test: TS0(xxxxOOOx)TS7 MS_Class=43
Mass test: TS0(xxxxOOOx)TS7 MS_Class=44
Mass test: TS0(xxxxOOOx)TS7 MS_Class=45
Mass test: TS0(xxxxOOOO)TS7 MS_Class=0
Mass test: TS0(xxxxOOOO)TS7 MS_Class=1
Mass test: TS0(xxxxOOOO)TS7 MS_Class=2
Mass test: TS0(xxxxOOOO)TS7 MS_Class=3
Mass test: TS0(xxxxOOOO)TS7 MS_Class=4
Mass test: TS0(xxxxOOOO)TS7 MS_Class=5
Mass test: TS0(xxxxOOOO)TS7 MS_Class=6
Mass test: TS0(xxxxOOOO)TS7 MS_Class=7
Mass test: TS0(xxxxOOOO)TS7 MS_Class=8
Mass test: TS0(xxxxOOOO)TS7 MS_Class=9
Mass test: TS0(xxxxOOOO)TS7 MS_Class=10
Mass test: TS0(xxxxOOOO)TS7 MS_Class=11
Mass test: TS0(xxxxOOOO)TS7 MS_Class=12
Mass test: TS0(xxxxOOOO)TS7 MS_Class=13
Mass test: TS0(xxxxOOOO)TS7 MS_Class=14
Mass test: TS0(xxxxOOOO)TS7 MS_Class=15
Mass test: TS0(xxxxOOOO)TS7 MS_Class=16
Mass test: TS0(xxxxOOOO)TS7 MS_Class=17
Mass test: TS0(xxxxOOOO)TS7 MS_Class=18
Mass test: TS0(xxxxOOOO)TS7 MS_Class=19
Mass test: TS0(xxxxOOOO)TS7 MS_Class=20
Mass test: TS0(xxxxOOOO)TS7 MS_Class=21
Mass test: TS0(xxxxOOOO)TS7 MS_Class=22
Mass test: TS0(xxxxOOOO)TS7 MS_Class=23
Mass test: TS0(xxxxOOOO)TS7 MS_Class=24
Mass test: TS0(xxxxOOOO)TS7 MS_Class=25
Mass test: TS0(xxxxOOOO)TS7 MS_Class=26
Mass test: TS0(xxxxOOOO)TS7 MS_Class=27
Mass test: TS0(xxxxOOOO)TS7 MS_Class=28
Mass test: TS0(xxxxOOOO)TS7 MS_Class=29
Mass test: TS0(xxxxOOOO)TS7 MS_Class=30
Mass test: TS0(xxxxOOOO)TS7 MS_Class=31
Mass test: TS0(xxxxOOOO)TS7 MS_Class=32
Mass test: TS0(xxxxOOOO)TS7 MS_Class=33
Mass test: TS0(xxxxOOOO)TS7 MS_Class=34
Mass test: TS0(xxxxOOOO)TS7 MS_Class=35
Mass test: TS0(xxxxOOOO)TS7 MS_Class=36
Mass test: TS0(xxxxOOOO)TS7 MS_Class=37
Mass test: TS0(xxxxOOOO)TS7 MS_Class=38
Mass test: TS0(xxxxOOOO)TS7 MS_Class=39
Mass test: TS0(xxxxOOOO)TS7 MS_Class=40
Mass test: TS0(xxxxOOOO)TS7 MS_Class=41
Mass test: TS0(xxxxOOOO)TS7 MS_Class=42
Mass test: TS0(xxxxOOOO)TS7 MS_Class=43
Mass test: TS0(xxxxOOOO)TS7 MS_Class=44
Mass test: TS0(xxxxOOOO)TS7 MS_Class=45
Mass test: TS0(xxxOxxxx)TS7 MS_Class=0
Mass test: TS0(xxxOxxxx)TS7 MS_Class=1
Mass test: TS0(xxxOxxxx)TS7 MS_Class=2
Mass test: TS0(xxxOxxxx)TS7 MS_Class=3
Mass test: TS0(xxxOxxxx)TS7 MS_Class=4
Mass test: TS0(xxxOxxxx)TS7 MS_Class=5
Mass test: TS0(xxxOxxxx)TS7 MS_Class=6
Mass test: TS0(xxxOxxxx)TS7 MS_Class=7
Mass test: TS0(xxxOxxxx)TS7 MS_Class=8
Mass test: TS0(xxxOxxxx)TS7 MS_Class=9
Mass test: TS0(xxxOxxxx)TS7 MS_Class=10
Mass test: TS0(xxxOxxxx)TS7 MS_Class=11
Mass test: TS0(xxxOxxxx)TS7 MS_Class=12
Mass test: TS0(xxxOxxxx)TS7 MS_Class=13
Mass test: TS0(xxxOxxxx)TS7 MS_Class=14
Mass test: TS0(xxxOxxxx)TS7 MS_Class=15
Mass test: TS0(xxxOxxxx)TS7 MS_Class=16
Mass test: TS0(xxxOxxxx)TS7 MS_Class=17
Mass test: TS0(xxxOxxxx)TS7 MS_Class=18
Mass test: TS0(xxxOxxxx)TS7 MS_Class=19
Mass test: TS0(xxxOxxxx)TS7 MS_Class=20
Mass test: TS0(xxxOxxxx)TS7 MS_Class=21
Mass test: TS0(xxxOxxxx)TS7 MS_Class=22
Mass test: TS0(xxxOxxxx)TS7 MS_Class=23
Mass test: TS0(xxxOxxxx)TS7 MS_Class=24
Mass test: TS0(xxxOxxxx)TS7 MS_Class=25
Mass test: TS0(xxxOxxxx)TS7 MS_Class=26
Mass test: TS0(xxxOxxxx)TS7 MS_Class=27
Mass test: TS0(xxxOxxxx)TS7 MS_Class=28
Mass test: TS0(xxxOxxxx)TS7 MS_Class=29
Mass test: TS0(xxxOxxxx)TS7 MS_Class=30
Mass test: TS0(xxxOxxxx)TS7 MS_Class=31
Mass test: TS0(xxxOxxxx)TS7 MS_Class=32
Mass test: TS0(xxxOxxxx)TS7 MS_Class=33
Mass test: TS0(xxxOxxxx)TS7 MS_Class=34
Mass test: TS0(xxxOxxxx)TS7 MS_Class=35
Mass test: TS0(xxxOxxxx)TS7 MS_Class=36
Mass test: TS0(xxxOxxxx)TS7 MS_Class=37
Mass test: TS0(xxxOxxxx)TS7 MS_Class=38
Mass test: TS0(xxxOxxxx)TS7 MS_Class=39
Mass test: TS0(xxxOxxxx)TS7 MS_Class=40
Mass test: TS0(xxxOxxxx)TS7 MS_Class=41
Mass test: TS0(xxxOxxxx)TS7 MS_Class=42
Mass test: TS0(xxxOxxxx)TS7 MS_Class=43
Mass test: TS0(xxxOxxxx)TS7 MS_Class=44
Mass test: TS0(xxxOxxxx)TS7 MS_Class=45
Mass test: TS0(xxxOxxxO)TS7 MS_Class=0
Mass test: TS0(xxxOxxxO)TS7 MS_Class=1
Mass test: TS0(xxxOxxxO)TS7 MS_Class=2
Mass test: TS0(xxxOxxxO)TS7 MS_Class=3
Mass test: TS0(xxxOxxxO)TS7 MS_Class=4
Mass test: TS0(xxxOxxxO)TS7 MS_Class=5
Mass test: TS0(xxxOxxxO)TS7 MS_Class=6
Mass test: TS0(xxxOxxxO)TS7 MS_Class=7
Mass test: TS0(xxxOxxxO)TS7 MS_Class=8
Mass test: TS0(xxxOxxxO)TS7 MS_Class=9
Mass test: TS0(xxxOxxxO)TS7 MS_Class=10
Mass test: TS0(xxxOxxxO)TS7 MS_Class=11
Mass test: TS0(xxxOxxxO)TS7 MS_Class=12
Mass test: TS0(xxxOxxxO)TS7 MS_Class=13
Mass test: TS0(xxxOxxxO)TS7 MS_Class=14
Mass test: TS0(xxxOxxxO)TS7 MS_Class=15
Mass test: TS0(xxxOxxxO)TS7 MS_Class=16
Mass test: TS0(xxxOxxxO)TS7 MS_Class=17
Mass test: TS0(xxxOxxxO)TS7 MS_Class=18
Mass test: TS0(xxxOxxxO)TS7 MS_Class=19
Mass test: TS0(xxxOxxxO)TS7 MS_Class=20
Mass test: TS0(xxxOxxxO)TS7 MS_Class=21
Mass test: TS0(xxxOxxxO)TS7 MS_Class=22
Mass test: TS0(xxxOxxxO)TS7 MS_Class=23
Mass test: TS0(xxxOxxxO)TS7 MS_Class=24
Mass test: TS0(xxxOxxxO)TS7 MS_Class=25
Mass test: TS0(xxxOxxxO)TS7 MS_Class=26
Mass test: TS0(xxxOxxxO)TS7 MS_Class=27
Mass test: TS0(xxxOxxxO)TS7 MS_Class=28
Mass test: TS0(xxxOxxxO)TS7 MS_Class=29
Mass test: TS0(xxxOxxxO)TS7 MS_Class=30
Mass test: TS0(xxxOxxxO)TS7 MS_Class=31
Mass test: TS0(xxxOxxxO)TS7 MS_Class=32
Mass test: TS0(xxxOxxxO)TS7 MS_Class=33
Mass test: TS0(xxxOxxxO)TS7 MS_Class=34
Mass test: TS0(xxxOxxxO)TS7 MS_Class=35
Mass test: TS0(xxxOxxxO)TS7 MS_Class=36
Mass test: TS0(xxxOxxxO)TS7 MS_Class=37
Mass test: TS0(xxxOxxxO)TS7 MS_Class=38
Mass test: TS0(xxxOxxxO)TS7 MS_Class=39
Mass test: TS0(xxxOxxxO)TS7 MS_Class=40
Mass test: TS0(xxxOxxxO)TS7 MS_Class=41
Mass test: TS0(xxxOxxxO)TS7 MS_Class=42
Mass test: TS0(xxxOxxxO)TS7 MS_Class=43
Mass test: TS0(xxxOxxxO)TS7 MS_Class=44
Mass test: TS0(xxxOxxxO)TS7 MS_Class=45
Mass test: TS0(xxxOxxOx)TS7 MS_Class=0
Mass test: TS0(xxxOxxOx)TS7 MS_Class=1
Mass test: TS0(xxxOxxOx)TS7 MS_Class=2
Mass test: TS0(xxxOxxOx)TS7 MS_Class=3
Mass test: TS0(xxxOxxOx)TS7 MS_Class=4
Mass test: TS0(xxxOxxOx)TS7 MS_Class=5
Mass test: TS0(xxxOxxOx)TS7 MS_Class=6
Mass test: TS0(xxxOxxOx)TS7 MS_Class=7
Mass test: TS0(xxxOxxOx)TS7 MS_Class=8
Mass test: TS0(xxxOxxOx)TS7 MS_Class=9
Mass test: TS0(xxxOxxOx)TS7 MS_Class=10
Mass test: TS0(xxxOxxOx)TS7 MS_Class=11
Mass test: TS0(xxxOxxOx)TS7 MS_Class=12
Mass test: TS0(xxxOxxOx)TS7 MS_Class=13
Mass test: TS0(xxxOxxOx)TS7 MS_Class=14
Mass test: TS0(xxxOxxOx)TS7 MS_Class=15
Mass test: TS0(xxxOxxOx)TS7 MS_Class=16
Mass test: TS0(xxxOxxOx)TS7 MS_Class=17
Mass test: TS0(xxxOxxOx)TS7 MS_Class=18
Mass test: TS0(xxxOxxOx)TS7 MS_Class=19
Mass test: TS0(xxxOxxOx)TS7 MS_Class=20
Mass test: TS0(xxxOxxOx)TS7 MS_Class=21
Mass test: TS0(xxxOxxOx)TS7 MS_Class=22
Mass test: TS0(xxxOxxOx)TS7 MS_Class=23
Mass test: TS0(xxxOxxOx)TS7 MS_Class=24
Mass test: TS0(xxxOxxOx)TS7 MS_Class=25
Mass test: TS0(xxxOxxOx)TS7 MS_Class=26
Mass test: TS0(xxxOxxOx)TS7 MS_Class=27
Mass test: TS0(xxxOxxOx)TS7 MS_Class=28
Mass test: TS0(xxxOxxOx)TS7 MS_Class=29
Mass test: TS0(xxxOxxOx)TS7 MS_Class=30
Mass test: TS0(xxxOxxOx)TS7 MS_Class=31
Mass test: TS0(xxxOxxOx)TS7 MS_Class=32
Mass test: TS0(xxxOxxOx)TS7 MS_Class=33
Mass test: TS0(xxxOxxOx)TS7 MS_Class=34
Mass test: TS0(xxxOxxOx)TS7 MS_Class=35
Mass test: TS0(xxxOxxOx)TS7 MS_Class=36
Mass test: TS0(xxxOxxOx)TS7 MS_Class=37
Mass test: TS0(xxxOxxOx)TS7 MS_Class=38
Mass test: TS0(xxxOxxOx)TS7 MS_Class=39
Mass test: TS0(xxxOxxOx)TS7 MS_Class=40
Mass test: TS0(xxxOxxOx)TS7 MS_Class=41
Mass test: TS0(xxxOxxOx)TS7 MS_Class=42
Mass test: TS0(xxxOxxOx)TS7 MS_Class=43
Mass test: TS0(xxxOxxOx)TS7 MS_Class=44
Mass test: TS0(xxxOxxOx)TS7 MS_Class=45
Mass test: TS0(xxxOxxOO)TS7 MS_Class=0
Mass test: TS0(xxxOxxOO)TS7 MS_Class=1
Mass test: TS0(xxxOxxOO)TS7 MS_Class=2
Mass test: TS0(xxxOxxOO)TS7 MS_Class=3
Mass test: TS0(xxxOxxOO)TS7 MS_Class=4
Mass test: TS0(xxxOxxOO)TS7 MS_Class=5
Mass test: TS0(xxxOxxOO)TS7 MS_Class=6
Mass test: TS0(xxxOxxOO)TS7 MS_Class=7
Mass test: TS0(xxxOxxOO)TS7 MS_Class=8
Mass test: TS0(xxxOxxOO)TS7 MS_Class=9
Mass test: TS0(xxxOxxOO)TS7 MS_Class=10
Mass test: TS0(xxxOxxOO)TS7 MS_Class=11
Mass test: TS0(xxxOxxOO)TS7 MS_Class=12
Mass test: TS0(xxxOxxOO)TS7 MS_Class=13
Mass test: TS0(xxxOxxOO)TS7 MS_Class=14
Mass test: TS0(xxxOxxOO)TS7 MS_Class=15
Mass test: TS0(xxxOxxOO)TS7 MS_Class=16
Mass test: TS0(xxxOxxOO)TS7 MS_Class=17
Mass test: TS0(xxxOxxOO)TS7 MS_Class=18
Mass test: TS0(xxxOxxOO)TS7 MS_Class=19
Mass test: TS0(xxxOxxOO)TS7 MS_Class=20
Mass test: TS0(xxxOxxOO)TS7 MS_Class=21
Mass test: TS0(xxxOxxOO)TS7 MS_Class=22
Mass test: TS0(xxxOxxOO)TS7 MS_Class=23
Mass test: TS0(xxxOxxOO)TS7 MS_Class=24
Mass test: TS0(xxxOxxOO)TS7 MS_Class=25
Mass test: TS0(xxxOxxOO)TS7 MS_Class=26
Mass test: TS0(xxxOxxOO)TS7 MS_Class=27
Mass test: TS0(xxxOxxOO)TS7 MS_Class=28
Mass test: TS0(xxxOxxOO)TS7 MS_Class=29
Mass test: TS0(xxxOxxOO)TS7 MS_Class=30
Mass test: TS0(xxxOxxOO)TS7 MS_Class=31
Mass test: TS0(xxxOxxOO)TS7 MS_Class=32
Mass test: TS0(xxxOxxOO)TS7 MS_Class=33
Mass test: TS0(xxxOxxOO)TS7 MS_Class=34
Mass test: TS0(xxxOxxOO)TS7 MS_Class=35
Mass test: TS0(xxxOxxOO)TS7 MS_Class=36
Mass test: TS0(xxxOxxOO)TS7 MS_Class=37
Mass test: TS0(xxxOxxOO)TS7 MS_Class=38
Mass test: TS0(xxxOxxOO)TS7 MS_Class=39
Mass test: TS0(xxxOxxOO)TS7 MS_Class=40
Mass test: TS0(xxxOxxOO)TS7 MS_Class=41
Mass test: TS0(xxxOxxOO)TS7 MS_Class=42
Mass test: TS0(xxxOxxOO)TS7 MS_Class=43
Mass test: TS0(xxxOxxOO)TS7 MS_Class=44
Mass test: TS0(xxxOxxOO)TS7 MS_Class=45
Mass test: TS0(xxxOxOxx)TS7 MS_Class=0
Mass test: TS0(xxxOxOxx)TS7 MS_Class=1
Mass test: TS0(xxxOxOxx)TS7 MS_Class=2
Mass test: TS0(xxxOxOxx)TS7 MS_Class=3
Mass test: TS0(xxxOxOxx)TS7 MS_Class=4
Mass test: TS0(xxxOxOxx)TS7 MS_Class=5
Mass test: TS0(xxxOxOxx)TS7 MS_Class=6
Mass test: TS0(xxxOxOxx)TS7 MS_Class=7
Mass test: TS0(xxxOxOxx)TS7 MS_Class=8
Mass test: TS0(xxxOxOxx)TS7 MS_Class=9
Mass test: TS0(xxxOxOxx)TS7 MS_Class=10
Mass test: TS0(xxxOxOxx)TS7 MS_Class=11
Mass test: TS0(xxxOxOxx)TS7 MS_Class=12
Mass test: TS0(xxxOxOxx)TS7 MS_Class=13
Mass test: TS0(xxxOxOxx)TS7 MS_Class=14
Mass test: TS0(xxxOxOxx)TS7 MS_Class=15
Mass test: TS0(xxxOxOxx)TS7 MS_Class=16
Mass test: TS0(xxxOxOxx)TS7 MS_Class=17
Mass test: TS0(xxxOxOxx)TS7 MS_Class=18
Mass test: TS0(xxxOxOxx)TS7 MS_Class=19
Mass test: TS0(xxxOxOxx)TS7 MS_Class=20
Mass test: TS0(xxxOxOxx)TS7 MS_Class=21
Mass test: TS0(xxxOxOxx)TS7 MS_Class=22
Mass test: TS0(xxxOxOxx)TS7 MS_Class=23
Mass test: TS0(xxxOxOxx)TS7 MS_Class=24
Mass test: TS0(xxxOxOxx)TS7 MS_Class=25
Mass test: TS0(xxxOxOxx)TS7 MS_Class=26
Mass test: TS0(xxxOxOxx)TS7 MS_Class=27
Mass test: TS0(xxxOxOxx)TS7 MS_Class=28
Mass test: TS0(xxxOxOxx)TS7 MS_Class=29
Mass test: TS0(xxxOxOxx)TS7 MS_Class=30
Mass test: TS0(xxxOxOxx)TS7 MS_Class=31
Mass test: TS0(xxxOxOxx)TS7 MS_Class=32
Mass test: TS0(xxxOxOxx)TS7 MS_Class=33
Mass test: TS0(xxxOxOxx)TS7 MS_Class=34
Mass test: TS0(xxxOxOxx)TS7 MS_Class=35
Mass test: TS0(xxxOxOxx)TS7 MS_Class=36
Mass test: TS0(xxxOxOxx)TS7 MS_Class=37
Mass test: TS0(xxxOxOxx)TS7 MS_Class=38
Mass test: TS0(xxxOxOxx)TS7 MS_Class=39
Mass test: TS0(xxxOxOxx)TS7 MS_Class=40
Mass test: TS0(xxxOxOxx)TS7 MS_Class=41
Mass test: TS0(xxxOxOxx)TS7 MS_Class=42
Mass test: TS0(xxxOxOxx)TS7 MS_Class=43
Mass test: TS0(xxxOxOxx)TS7 MS_Class=44
Mass test: TS0(xxxOxOxx)TS7 MS_Class=45
Mass test: TS0(xxxOxOxO)TS7 MS_Class=0
Mass test: TS0(xxxOxOxO)TS7 MS_Class=1
Mass test: TS0(xxxOxOxO)TS7 MS_Class=2
Mass test: TS0(xxxOxOxO)TS7 MS_Class=3
Mass test: TS0(xxxOxOxO)TS7 MS_Class=4
Mass test: TS0(xxxOxOxO)TS7 MS_Class=5
Mass test: TS0(xxxOxOxO)TS7 MS_Class=6
Mass test: TS0(xxxOxOxO)TS7 MS_Class=7
Mass test: TS0(xxxOxOxO)TS7 MS_Class=8
Mass test: TS0(xxxOxOxO)TS7 MS_Class=9
Mass test: TS0(xxxOxOxO)TS7 MS_Class=10
Mass test: TS0(xxxOxOxO)TS7 MS_Class=11
Mass test: TS0(xxxOxOxO)TS7 MS_Class=12
Mass test: TS0(xxxOxOxO)TS7 MS_Class=13
Mass test: TS0(xxxOxOxO)TS7 MS_Class=14
Mass test: TS0(xxxOxOxO)TS7 MS_Class=15
Mass test: TS0(xxxOxOxO)TS7 MS_Class=16
Mass test: TS0(xxxOxOxO)TS7 MS_Class=17
Mass test: TS0(xxxOxOxO)TS7 MS_Class=18
Mass test: TS0(xxxOxOxO)TS7 MS_Class=19
Mass test: TS0(xxxOxOxO)TS7 MS_Class=20
Mass test: TS0(xxxOxOxO)TS7 MS_Class=21
Mass test: TS0(xxxOxOxO)TS7 MS_Class=22
Mass test: TS0(xxxOxOxO)TS7 MS_Class=23
Mass test: TS0(xxxOxOxO)TS7 MS_Class=24
Mass test: TS0(xxxOxOxO)TS7 MS_Class=25
Mass test: TS0(xxxOxOxO)TS7 MS_Class=26
Mass test: TS0(xxxOxOxO)TS7 MS_Class=27
Mass test: TS0(xxxOxOxO)TS7 MS_Class=28
Mass test: TS0(xxxOxOxO)TS7 MS_Class=29
Mass test: TS0(xxxOxOxO)TS7 MS_Class=30
Mass test: TS0(xxxOxOxO)TS7 MS_Class=31
Mass test: TS0(xxxOxOxO)TS7 MS_Class=32
Mass test: TS0(xxxOxOxO)TS7 MS_Class=33
Mass test: TS0(xxxOxOxO)TS7 MS_Class=34
Mass test: TS0(xxxOxOxO)TS7 MS_Class=35
Mass test: TS0(xxxOxOxO)TS7 MS_Class=36
Mass test: TS0(xxxOxOxO)TS7 MS_Class=37
Mass test: TS0(xxxOxOxO)TS7 MS_Class=38
Mass test: TS0(xxxOxOxO)TS7 MS_Class=39
Mass test: TS0(xxxOxOxO)TS7 MS_Class=40
Mass test: TS0(xxxOxOxO)TS7 MS_Class=41
Mass test: TS0(xxxOxOxO)TS7 MS_Class=42
Mass test: TS0(xxxOxOxO)TS7 MS_Class=43
Mass test: TS0(xxxOxOxO)TS7 MS_Class=44
Mass test: TS0(xxxOxOxO)TS7 MS_Class=45
Mass test: TS0(xxxOxOOx)TS7 MS_Class=0
Mass test: TS0(xxxOxOOx)TS7 MS_Class=1
Mass test: TS0(xxxOxOOx)TS7 MS_Class=2
Mass test: TS0(xxxOxOOx)TS7 MS_Class=3
Mass test: TS0(xxxOxOOx)TS7 MS_Class=4
Mass test: TS0(xxxOxOOx)TS7 MS_Class=5
Mass test: TS0(xxxOxOOx)TS7 MS_Class=6
Mass test: TS0(xxxOxOOx)TS7 MS_Class=7
Mass test: TS0(xxxOxOOx)TS7 MS_Class=8
Mass test: TS0(xxxOxOOx)TS7 MS_Class=9
Mass test: TS0(xxxOxOOx)TS7 MS_Class=10
Mass test: TS0(xxxOxOOx)TS7 MS_Class=11
Mass test: TS0(xxxOxOOx)TS7 MS_Class=12
Mass test: TS0(xxxOxOOx)TS7 MS_Class=13
Mass test: TS0(xxxOxOOx)TS7 MS_Class=14
Mass test: TS0(xxxOxOOx)TS7 MS_Class=15
Mass test: TS0(xxxOxOOx)TS7 MS_Class=16
Mass test: TS0(xxxOxOOx)TS7 MS_Class=17
Mass test: TS0(xxxOxOOx)TS7 MS_Class=18
Mass test: TS0(xxxOxOOx)TS7 MS_Class=19
Mass test: TS0(xxxOxOOx)TS7 MS_Class=20
Mass test: TS0(xxxOxOOx)TS7 MS_Class=21
Mass test: TS0(xxxOxOOx)TS7 MS_Class=22
Mass test: TS0(xxxOxOOx)TS7 MS_Class=23
Mass test: TS0(xxxOxOOx)TS7 MS_Class=24
Mass test: TS0(xxxOxOOx)TS7 MS_Class=25
Mass test: TS0(xxxOxOOx)TS7 MS_Class=26
Mass test: TS0(xxxOxOOx)TS7 MS_Class=27
Mass test: TS0(xxxOxOOx)TS7 MS_Class=28
Mass test: TS0(xxxOxOOx)TS7 MS_Class=29
Mass test: TS0(xxxOxOOx)TS7 MS_Class=30
Mass test: TS0(xxxOxOOx)TS7 MS_Class=31
Mass test: TS0(xxxOxOOx)TS7 MS_Class=32
Mass test: TS0(xxxOxOOx)TS7 MS_Class=33
Mass test: TS0(xxxOxOOx)TS7 MS_Class=34
Mass test: TS0(xxxOxOOx)TS7 MS_Class=35
Mass test: TS0(xxxOxOOx)TS7 MS_Class=36
Mass test: TS0(xxxOxOOx)TS7 MS_Class=37
Mass test: TS0(xxxOxOOx)TS7 MS_Class=38
Mass test: TS0(xxxOxOOx)TS7 MS_Class=39
Mass test: TS0(xxxOxOOx)TS7 MS_Class=40
Mass test: TS0(xxxOxOOx)TS7 MS_Class=41
Mass test: TS0(xxxOxOOx)TS7 MS_Class=42
Mass test: TS0(xxxOxOOx)TS7 MS_Class=43
Mass test: TS0(xxxOxOOx)TS7 MS_Class=44
Mass test: TS0(xxxOxOOx)TS7 MS_Class=45
Mass test: TS0(xxxOxOOO)TS7 MS_Class=0
Mass test: TS0(xxxOxOOO)TS7 MS_Class=1
Mass test: TS0(xxxOxOOO)TS7 MS_Class=2
Mass test: TS0(xxxOxOOO)TS7 MS_Class=3
Mass test: TS0(xxxOxOOO)TS7 MS_Class=4
Mass test: TS0(xxxOxOOO)TS7 MS_Class=5
Mass test: TS0(xxxOxOOO)TS7 MS_Class=6
Mass test: TS0(xxxOxOOO)TS7 MS_Class=7
Mass test: TS0(xxxOxOOO)TS7 MS_Class=8
Mass test: TS0(xxxOxOOO)TS7 MS_Class=9
Mass test: TS0(xxxOxOOO)TS7 MS_Class=10
Mass test: TS0(xxxOxOOO)TS7 MS_Class=11
Mass test: TS0(xxxOxOOO)TS7 MS_Class=12
Mass test: TS0(xxxOxOOO)TS7 MS_Class=13
Mass test: TS0(xxxOxOOO)TS7 MS_Class=14
Mass test: TS0(xxxOxOOO)TS7 MS_Class=15
Mass test: TS0(xxxOxOOO)TS7 MS_Class=16
Mass test: TS0(xxxOxOOO)TS7 MS_Class=17
Mass test: TS0(xxxOxOOO)TS7 MS_Class=18
Mass test: TS0(xxxOxOOO)TS7 MS_Class=19
Mass test: TS0(xxxOxOOO)TS7 MS_Class=20
Mass test: TS0(xxxOxOOO)TS7 MS_Class=21
Mass test: TS0(xxxOxOOO)TS7 MS_Class=22
Mass test: TS0(xxxOxOOO)TS7 MS_Class=23
Mass test: TS0(xxxOxOOO)TS7 MS_Class=24
Mass test: TS0(xxxOxOOO)TS7 MS_Class=25
Mass test: TS0(xxxOxOOO)TS7 MS_Class=26
Mass test: TS0(xxxOxOOO)TS7 MS_Class=27
Mass test: TS0(xxxOxOOO)TS7 MS_Class=28
Mass test: TS0(xxxOxOOO)TS7 MS_Class=29
Mass test: TS0(xxxOxOOO)TS7 MS_Class=30
Mass test: TS0(xxxOxOOO)TS7 MS_Class=31
Mass test: TS0(xxxOxOOO)TS7 MS_Class=32
Mass test: TS0(xxxOxOOO)TS7 MS_Class=33
Mass test: TS0(xxxOxOOO)TS7 MS_Class=34
Mass test: TS0(xxxOxOOO)TS7 MS_Class=35
Mass test: TS0(xxxOxOOO)TS7 MS_Class=36
Mass test: TS0(xxxOxOOO)TS7 MS_Class=37
Mass test: TS0(xxxOxOOO)TS7 MS_Class=38
Mass test: TS0(xxxOxOOO)TS7 MS_Class=39
Mass test: TS0(xxxOxOOO)TS7 MS_Class=40
Mass test: TS0(xxxOxOOO)TS7 MS_Class=41
Mass test: TS0(xxxOxOOO)TS7 MS_Class=42
Mass test: TS0(xxxOxOOO)TS7 MS_Class=43
Mass test: TS0(xxxOxOOO)TS7 MS_Class=44
Mass test: TS0(xxxOxOOO)TS7 MS_Class=45
Mass test: TS0(xxxOOxxx)TS7 MS_Class=0
Mass test: TS0(xxxOOxxx)TS7 MS_Class=1
Mass test: TS0(xxxOOxxx)TS7 MS_Class=2
Mass test: TS0(xxxOOxxx)TS7 MS_Class=3
Mass test: TS0(xxxOOxxx)TS7 MS_Class=4
Mass test: TS0(xxxOOxxx)TS7 MS_Class=5
Mass test: TS0(xxxOOxxx)TS7 MS_Class=6
Mass test: TS0(xxxOOxxx)TS7 MS_Class=7
Mass test: TS0(xxxOOxxx)TS7 MS_Class=8
Mass test: TS0(xxxOOxxx)TS7 MS_Class=9
Mass test: TS0(xxxOOxxx)TS7 MS_Class=10
Mass test: TS0(xxxOOxxx)TS7 MS_Class=11
Mass test: TS0(xxxOOxxx)TS7 MS_Class=12
Mass test: TS0(xxxOOxxx)TS7 MS_Class=13
Mass test: TS0(xxxOOxxx)TS7 MS_Class=14
Mass test: TS0(xxxOOxxx)TS7 MS_Class=15
Mass test: TS0(xxxOOxxx)TS7 MS_Class=16
Mass test: TS0(xxxOOxxx)TS7 MS_Class=17
Mass test: TS0(xxxOOxxx)TS7 MS_Class=18
Mass test: TS0(xxxOOxxx)TS7 MS_Class=19
Mass test: TS0(xxxOOxxx)TS7 MS_Class=20
Mass test: TS0(xxxOOxxx)TS7 MS_Class=21
Mass test: TS0(xxxOOxxx)TS7 MS_Class=22
Mass test: TS0(xxxOOxxx)TS7 MS_Class=23
Mass test: TS0(xxxOOxxx)TS7 MS_Class=24
Mass test: TS0(xxxOOxxx)TS7 MS_Class=25
Mass test: TS0(xxxOOxxx)TS7 MS_Class=26
Mass test: TS0(xxxOOxxx)TS7 MS_Class=27
Mass test: TS0(xxxOOxxx)TS7 MS_Class=28
Mass test: TS0(xxxOOxxx)TS7 MS_Class=29
Mass test: TS0(xxxOOxxx)TS7 MS_Class=30
Mass test: TS0(xxxOOxxx)TS7 MS_Class=31
Mass test: TS0(xxxOOxxx)TS7 MS_Class=32
Mass test: TS0(xxxOOxxx)TS7 MS_Class=33
Mass test: TS0(xxxOOxxx)TS7 MS_Class=34
Mass test: TS0(xxxOOxxx)TS7 MS_Class=35
Mass test: TS0(xxxOOxxx)TS7 MS_Class=36
Mass test: TS0(xxxOOxxx)TS7 MS_Class=37
Mass test: TS0(xxxOOxxx)TS7 MS_Class=38
Mass test: TS0(xxxOOxxx)TS7 MS_Class=39
Mass test: TS0(xxxOOxxx)TS7 MS_Class=40
Mass test: TS0(xxxOOxxx)TS7 MS_Class=41
Mass test: TS0(xxxOOxxx)TS7 MS_Class=42
Mass test: TS0(xxxOOxxx)TS7 MS_Class=43
Mass test: TS0(xxxOOxxx)TS7 MS_Class=44
Mass test: TS0(xxxOOxxx)TS7 MS_Class=45
Mass test: TS0(xxxOOxxO)TS7 MS_Class=0
Mass test: TS0(xxxOOxxO)TS7 MS_Class=1
Mass test: TS0(xxxOOxxO)TS7 MS_Class=2
Mass test: TS0(xxxOOxxO)TS7 MS_Class=3
Mass test: TS0(xxxOOxxO)TS7 MS_Class=4
Mass test: TS0(xxxOOxxO)TS7 MS_Class=5
Mass test: TS0(xxxOOxxO)TS7 MS_Class=6
Mass test: TS0(xxxOOxxO)TS7 MS_Class=7
Mass test: TS0(xxxOOxxO)TS7 MS_Class=8
Mass test: TS0(xxxOOxxO)TS7 MS_Class=9
Mass test: TS0(xxxOOxxO)TS7 MS_Class=10
Mass test: TS0(xxxOOxxO)TS7 MS_Class=11
Mass test: TS0(xxxOOxxO)TS7 MS_Class=12
Mass test: TS0(xxxOOxxO)TS7 MS_Class=13
Mass test: TS0(xxxOOxxO)TS7 MS_Class=14
Mass test: TS0(xxxOOxxO)TS7 MS_Class=15
Mass test: TS0(xxxOOxxO)TS7 MS_Class=16
Mass test: TS0(xxxOOxxO)TS7 MS_Class=17
Mass test: TS0(xxxOOxxO)TS7 MS_Class=18
Mass test: TS0(xxxOOxxO)TS7 MS_Class=19
Mass test: TS0(xxxOOxxO)TS7 MS_Class=20
Mass test: TS0(xxxOOxxO)TS7 MS_Class=21
Mass test: TS0(xxxOOxxO)TS7 MS_Class=22
Mass test: TS0(xxxOOxxO)TS7 MS_Class=23
Mass test: TS0(xxxOOxxO)TS7 MS_Class=24
Mass test: TS0(xxxOOxxO)TS7 MS_Class=25
Mass test: TS0(xxxOOxxO)TS7 MS_Class=26
Mass test: TS0(xxxOOxxO)TS7 MS_Class=27
Mass test: TS0(xxxOOxxO)TS7 MS_Class=28
Mass test: TS0(xxxOOxxO)TS7 MS_Class=29
Mass test: TS0(xxxOOxxO)TS7 MS_Class=30
Mass test: TS0(xxxOOxxO)TS7 MS_Class=31
Mass test: TS0(xxxOOxxO)TS7 MS_Class=32
Mass test: TS0(xxxOOxxO)TS7 MS_Class=33
Mass test: TS0(xxxOOxxO)TS7 MS_Class=34
Mass test: TS0(xxxOOxxO)TS7 MS_Class=35
Mass test: TS0(xxxOOxxO)TS7 MS_Class=36
Mass test: TS0(xxxOOxxO)TS7 MS_Class=37
Mass test: TS0(xxxOOxxO)TS7 MS_Class=38
Mass test: TS0(xxxOOxxO)TS7 MS_Class=39
Mass test: TS0(xxxOOxxO)TS7 MS_Class=40
Mass test: TS0(xxxOOxxO)TS7 MS_Class=41
Mass test: TS0(xxxOOxxO)TS7 MS_Class=42
Mass test: TS0(xxxOOxxO)TS7 MS_Class=43
Mass test: TS0(xxxOOxxO)TS7 MS_Class=44
Mass test: TS0(xxxOOxxO)TS7 MS_Class=45
Mass test: TS0(xxxOOxOx)TS7 MS_Class=0
Mass test: TS0(xxxOOxOx)TS7 MS_Class=1
Mass test: TS0(xxxOOxOx)TS7 MS_Class=2
Mass test: TS0(xxxOOxOx)TS7 MS_Class=3
Mass test: TS0(xxxOOxOx)TS7 MS_Class=4
Mass test: TS0(xxxOOxOx)TS7 MS_Class=5
Mass test: TS0(xxxOOxOx)TS7 MS_Class=6
Mass test: TS0(xxxOOxOx)TS7 MS_Class=7
Mass test: TS0(xxxOOxOx)TS7 MS_Class=8
Mass test: TS0(xxxOOxOx)TS7 MS_Class=9
Mass test: TS0(xxxOOxOx)TS7 MS_Class=10
Mass test: TS0(xxxOOxOx)TS7 MS_Class=11
Mass test: TS0(xxxOOxOx)TS7 MS_Class=12
Mass test: TS0(xxxOOxOx)TS7 MS_Class=13
Mass test: TS0(xxxOOxOx)TS7 MS_Class=14
Mass test: TS0(xxxOOxOx)TS7 MS_Class=15
Mass test: TS0(xxxOOxOx)TS7 MS_Class=16
Mass test: TS0(xxxOOxOx)TS7 MS_Class=17
Mass test: TS0(xxxOOxOx)TS7 MS_Class=18
Mass test: TS0(xxxOOxOx)TS7 MS_Class=19
Mass test: TS0(xxxOOxOx)TS7 MS_Class=20
Mass test: TS0(xxxOOxOx)TS7 MS_Class=21
Mass test: TS0(xxxOOxOx)TS7 MS_Class=22
Mass test: TS0(xxxOOxOx)TS7 MS_Class=23
Mass test: TS0(xxxOOxOx)TS7 MS_Class=24
Mass test: TS0(xxxOOxOx)TS7 MS_Class=25
Mass test: TS0(xxxOOxOx)TS7 MS_Class=26
Mass test: TS0(xxxOOxOx)TS7 MS_Class=27
Mass test: TS0(xxxOOxOx)TS7 MS_Class=28
Mass test: TS0(xxxOOxOx)TS7 MS_Class=29
Mass test: TS0(xxxOOxOx)TS7 MS_Class=30
Mass test: TS0(xxxOOxOx)TS7 MS_Class=31
Mass test: TS0(xxxOOxOx)TS7 MS_Class=32
Mass test: TS0(xxxOOxOx)TS7 MS_Class=33
Mass test: TS0(xxxOOxOx)TS7 MS_Class=34
Mass test: TS0(xxxOOxOx)TS7 MS_Class=35
Mass test: TS0(xxxOOxOx)TS7 MS_Class=36
Mass test: TS0(xxxOOxOx)TS7 MS_Class=37
Mass test: TS0(xxxOOxOx)TS7 MS_Class=38
Mass test: TS0(xxxOOxOx)TS7 MS_Class=39
Mass test: TS0(xxxOOxOx)TS7 MS_Class=40
Mass test: TS0(xxxOOxOx)TS7 MS_Class=41
Mass test: TS0(xxxOOxOx)TS7 MS_Class=42
Mass test: TS0(xxxOOxOx)TS7 MS_Class=43
Mass test: TS0(xxxOOxOx)TS7 MS_Class=44
Mass test: TS0(xxxOOxOx)TS7 MS_Class=45
Mass test: TS0(xxxOOxOO)TS7 MS_Class=0
Mass test: TS0(xxxOOxOO)TS7 MS_Class=1
Mass test: TS0(xxxOOxOO)TS7 MS_Class=2
Mass test: TS0(xxxOOxOO)TS7 MS_Class=3
Mass test: TS0(xxxOOxOO)TS7 MS_Class=4
Mass test: TS0(xxxOOxOO)TS7 MS_Class=5
Mass test: TS0(xxxOOxOO)TS7 MS_Class=6
Mass test: TS0(xxxOOxOO)TS7 MS_Class=7
Mass test: TS0(xxxOOxOO)TS7 MS_Class=8
Mass test: TS0(xxxOOxOO)TS7 MS_Class=9
Mass test: TS0(xxxOOxOO)TS7 MS_Class=10
Mass test: TS0(xxxOOxOO)TS7 MS_Class=11
Mass test: TS0(xxxOOxOO)TS7 MS_Class=12
Mass test: TS0(xxxOOxOO)TS7 MS_Class=13
Mass test: TS0(xxxOOxOO)TS7 MS_Class=14
Mass test: TS0(xxxOOxOO)TS7 MS_Class=15
Mass test: TS0(xxxOOxOO)TS7 MS_Class=16
Mass test: TS0(xxxOOxOO)TS7 MS_Class=17
Mass test: TS0(xxxOOxOO)TS7 MS_Class=18
Mass test: TS0(xxxOOxOO)TS7 MS_Class=19
Mass test: TS0(xxxOOxOO)TS7 MS_Class=20
Mass test: TS0(xxxOOxOO)TS7 MS_Class=21
Mass test: TS0(xxxOOxOO)TS7 MS_Class=22
Mass test: TS0(xxxOOxOO)TS7 MS_Class=23
Mass test: TS0(xxxOOxOO)TS7 MS_Class=24
Mass test: TS0(xxxOOxOO)TS7 MS_Class=25
Mass test: TS0(xxxOOxOO)TS7 MS_Class=26
Mass test: TS0(xxxOOxOO)TS7 MS_Class=27
Mass test: TS0(xxxOOxOO)TS7 MS_Class=28
Mass test: TS0(xxxOOxOO)TS7 MS_Class=29
Mass test: TS0(xxxOOxOO)TS7 MS_Class=30
Mass test: TS0(xxxOOxOO)TS7 MS_Class=31
Mass test: TS0(xxxOOxOO)TS7 MS_Class=32
Mass test: TS0(xxxOOxOO)TS7 MS_Class=33
Mass test: TS0(xxxOOxOO)TS7 MS_Class=34
Mass test: TS0(xxxOOxOO)TS7 MS_Class=35
Mass test: TS0(xxxOOxOO)TS7 MS_Class=36
Mass test: TS0(xxxOOxOO)TS7 MS_Class=37
Mass test: TS0(xxxOOxOO)TS7 MS_Class=38
Mass test: TS0(xxxOOxOO)TS7 MS_Class=39
Mass test: TS0(xxxOOxOO)TS7 MS_Class=40
Mass test: TS0(xxxOOxOO)TS7 MS_Class=41
Mass test: TS0(xxxOOxOO)TS7 MS_Class=42
Mass test: TS0(xxxOOxOO)TS7 MS_Class=43
Mass test: TS0(xxxOOxOO)TS7 MS_Class=44
Mass test: TS0(xxxOOxOO)TS7 MS_Class=45
Mass test: TS0(xxxOOOxx)TS7 MS_Class=0
Mass test: TS0(xxxOOOxx)TS7 MS_Class=1
Mass test: TS0(xxxOOOxx)TS7 MS_Class=2
Mass test: TS0(xxxOOOxx)TS7 MS_Class=3
Mass test: TS0(xxxOOOxx)TS7 MS_Class=4
Mass test: TS0(xxxOOOxx)TS7 MS_Class=5
Mass test: TS0(xxxOOOxx)TS7 MS_Class=6
Mass test: TS0(xxxOOOxx)TS7 MS_Class=7
Mass test: TS0(xxxOOOxx)TS7 MS_Class=8
Mass test: TS0(xxxOOOxx)TS7 MS_Class=9
Mass test: TS0(xxxOOOxx)TS7 MS_Class=10
Mass test: TS0(xxxOOOxx)TS7 MS_Class=11
Mass test: TS0(xxxOOOxx)TS7 MS_Class=12
Mass test: TS0(xxxOOOxx)TS7 MS_Class=13
Mass test: TS0(xxxOOOxx)TS7 MS_Class=14
Mass test: TS0(xxxOOOxx)TS7 MS_Class=15
Mass test: TS0(xxxOOOxx)TS7 MS_Class=16
Mass test: TS0(xxxOOOxx)TS7 MS_Class=17
Mass test: TS0(xxxOOOxx)TS7 MS_Class=18
Mass test: TS0(xxxOOOxx)TS7 MS_Class=19
Mass test: TS0(xxxOOOxx)TS7 MS_Class=20
Mass test: TS0(xxxOOOxx)TS7 MS_Class=21
Mass test: TS0(xxxOOOxx)TS7 MS_Class=22
Mass test: TS0(xxxOOOxx)TS7 MS_Class=23
Mass test: TS0(xxxOOOxx)TS7 MS_Class=24
Mass test: TS0(xxxOOOxx)TS7 MS_Class=25
Mass test: TS0(xxxOOOxx)TS7 MS_Class=26
Mass test: TS0(xxxOOOxx)TS7 MS_Class=27
Mass test: TS0(xxxOOOxx)TS7 MS_Class=28
Mass test: TS0(xxxOOOxx)TS7 MS_Class=29
Mass test: TS0(xxxOOOxx)TS7 MS_Class=30
Mass test: TS0(xxxOOOxx)TS7 MS_Class=31
Mass test: TS0(xxxOOOxx)TS7 MS_Class=32
Mass test: TS0(xxxOOOxx)TS7 MS_Class=33
Mass test: TS0(xxxOOOxx)TS7 MS_Class=34
Mass test: TS0(xxxOOOxx)TS7 MS_Class=35
Mass test: TS0(xxxOOOxx)TS7 MS_Class=36
Mass test: TS0(xxxOOOxx)TS7 MS_Class=37
Mass test: TS0(xxxOOOxx)TS7 MS_Class=38
Mass test: TS0(xxxOOOxx)TS7 MS_Class=39
Mass test: TS0(xxxOOOxx)TS7 MS_Class=40
Mass test: TS0(xxxOOOxx)TS7 MS_Class=41
Mass test: TS0(xxxOOOxx)TS7 MS_Class=42
Mass test: TS0(xxxOOOxx)TS7 MS_Class=43
Mass test: TS0(xxxOOOxx)TS7 MS_Class=44
Mass test: TS0(xxxOOOxx)TS7 MS_Class=45
Mass test: TS0(xxxOOOxO)TS7 MS_Class=0
Mass test: TS0(xxxOOOxO)TS7 MS_Class=1
Mass test: TS0(xxxOOOxO)TS7 MS_Class=2
Mass test: TS0(xxxOOOxO)TS7 MS_Class=3
Mass test: TS0(xxxOOOxO)TS7 MS_Class=4
Mass test: TS0(xxxOOOxO)TS7 MS_Class=5
Mass test: TS0(xxxOOOxO)TS7 MS_Class=6
Mass test: TS0(xxxOOOxO)TS7 MS_Class=7
Mass test: TS0(xxxOOOxO)TS7 MS_Class=8
Mass test: TS0(xxxOOOxO)TS7 MS_Class=9
Mass test: TS0(xxxOOOxO)TS7 MS_Class=10
Mass test: TS0(xxxOOOxO)TS7 MS_Class=11
Mass test: TS0(xxxOOOxO)TS7 MS_Class=12
Mass test: TS0(xxxOOOxO)TS7 MS_Class=13
Mass test: TS0(xxxOOOxO)TS7 MS_Class=14
Mass test: TS0(xxxOOOxO)TS7 MS_Class=15
Mass test: TS0(xxxOOOxO)TS7 MS_Class=16
Mass test: TS0(xxxOOOxO)TS7 MS_Class=17
Mass test: TS0(xxxOOOxO)TS7 MS_Class=18
Mass test: TS0(xxxOOOxO)TS7 MS_Class=19
Mass test: TS0(xxxOOOxO)TS7 MS_Class=20
Mass test: TS0(xxxOOOxO)TS7 MS_Class=21
Mass test: TS0(xxxOOOxO)TS7 MS_Class=22
Mass test: TS0(xxxOOOxO)TS7 MS_Class=23
Mass test: TS0(xxxOOOxO)TS7 MS_Class=24
Mass test: TS0(xxxOOOxO)TS7 MS_Class=25
Mass test: TS0(xxxOOOxO)TS7 MS_Class=26
Mass test: TS0(xxxOOOxO)TS7 MS_Class=27
Mass test: TS0(xxxOOOxO)TS7 MS_Class=28
Mass test: TS0(xxxOOOxO)TS7 MS_Class=29
Mass test: TS0(xxxOOOxO)TS7 MS_Class=30
Mass test: TS0(xxxOOOxO)TS7 MS_Class=31
Mass test: TS0(xxxOOOxO)TS7 MS_Class=32
Mass test: TS0(xxxOOOxO)TS7 MS_Class=33
Mass test: TS0(xxxOOOxO)TS7 MS_Class=34
Mass test: TS0(xxxOOOxO)TS7 MS_Class=35
Mass test: TS0(xxxOOOxO)TS7 MS_Class=36
Mass test: TS0(xxxOOOxO)TS7 MS_Class=37
Mass test: TS0(xxxOOOxO)TS7 MS_Class=38
Mass test: TS0(xxxOOOxO)TS7 MS_Class=39
Mass test: TS0(xxxOOOxO)TS7 MS_Class=40
Mass test: TS0(xxxOOOxO)TS7 MS_Class=41
Mass test: TS0(xxxOOOxO)TS7 MS_Class=42
Mass test: TS0(xxxOOOxO)TS7 MS_Class=43
Mass test: TS0(xxxOOOxO)TS7 MS_Class=44
Mass test: TS0(xxxOOOxO)TS7 MS_Class=45
Mass test: TS0(xxxOOOOx)TS7 MS_Class=0
Mass test: TS0(xxxOOOOx)TS7 MS_Class=1
Mass test: TS0(xxxOOOOx)TS7 MS_Class=2
Mass test: TS0(xxxOOOOx)TS7 MS_Class=3
Mass test: TS0(xxxOOOOx)TS7 MS_Class=4
Mass test: TS0(xxxOOOOx)TS7 MS_Class=5
Mass test: TS0(xxxOOOOx)TS7 MS_Class=6
Mass test: TS0(xxxOOOOx)TS7 MS_Class=7
Mass test: TS0(xxxOOOOx)TS7 MS_Class=8
Mass test: TS0(xxxOOOOx)TS7 MS_Class=9
Mass test: TS0(xxxOOOOx)TS7 MS_Class=10
Mass test: TS0(xxxOOOOx)TS7 MS_Class=11
Mass test: TS0(xxxOOOOx)TS7 MS_Class=12
Mass test: TS0(xxxOOOOx)TS7 MS_Class=13
Mass test: TS0(xxxOOOOx)TS7 MS_Class=14
Mass test: TS0(xxxOOOOx)TS7 MS_Class=15
Mass test: TS0(xxxOOOOx)TS7 MS_Class=16
Mass test: TS0(xxxOOOOx)TS7 MS_Class=17
Mass test: TS0(xxxOOOOx)TS7 MS_Class=18
Mass test: TS0(xxxOOOOx)TS7 MS_Class=19
Mass test: TS0(xxxOOOOx)TS7 MS_Class=20
Mass test: TS0(xxxOOOOx)TS7 MS_Class=21
Mass test: TS0(xxxOOOOx)TS7 MS_Class=22
Mass test: TS0(xxxOOOOx)TS7 MS_Class=23
Mass test: TS0(xxxOOOOx)TS7 MS_Class=24
Mass test: TS0(xxxOOOOx)TS7 MS_Class=25
Mass test: TS0(xxxOOOOx)TS7 MS_Class=26
Mass test: TS0(xxxOOOOx)TS7 MS_Class=27
Mass test: TS0(xxxOOOOx)TS7 MS_Class=28
Mass test: TS0(xxxOOOOx)TS7 MS_Class=29
Mass test: TS0(xxxOOOOx)TS7 MS_Class=30
Mass test: TS0(xxxOOOOx)TS7 MS_Class=31
Mass test: TS0(xxxOOOOx)TS7 MS_Class=32
Mass test: TS0(xxxOOOOx)TS7 MS_Class=33
Mass test: TS0(xxxOOOOx)TS7 MS_Class=34
Mass test: TS0(xxxOOOOx)TS7 MS_Class=35
Mass test: TS0(xxxOOOOx)TS7 MS_Class=36
Mass test: TS0(xxxOOOOx)TS7 MS_Class=37
Mass test: TS0(xxxOOOOx)TS7 MS_Class=38
Mass test: TS0(xxxOOOOx)TS7 MS_Class=39
Mass test: TS0(xxxOOOOx)TS7 MS_Class=40
Mass test: TS0(xxxOOOOx)TS7 MS_Class=41
Mass test: TS0(xxxOOOOx)TS7 MS_Class=42
Mass test: TS0(xxxOOOOx)TS7 MS_Class=43
Mass test: TS0(xxxOOOOx)TS7 MS_Class=44
Mass test: TS0(xxxOOOOx)TS7 MS_Class=45
Mass test: TS0(xxxOOOOO)TS7 MS_Class=0
Mass test: TS0(xxxOOOOO)TS7 MS_Class=1
Mass test: TS0(xxxOOOOO)TS7 MS_Class=2
Mass test: TS0(xxxOOOOO)TS7 MS_Class=3
Mass test: TS0(xxxOOOOO)TS7 MS_Class=4
Mass test: TS0(xxxOOOOO)TS7 MS_Class=5
Mass test: TS0(xxxOOOOO)TS7 MS_Class=6
Mass test: TS0(xxxOOOOO)TS7 MS_Class=7
Mass test: TS0(xxxOOOOO)TS7 MS_Class=8
Mass test: TS0(xxxOOOOO)TS7 MS_Class=9
Mass test: TS0(xxxOOOOO)TS7 MS_Class=10
Mass test: TS0(xxxOOOOO)TS7 MS_Class=11
Mass test: TS0(xxxOOOOO)TS7 MS_Class=12
Mass test: TS0(xxxOOOOO)TS7 MS_Class=13
Mass test: TS0(xxxOOOOO)TS7 MS_Class=14
Mass test: TS0(xxxOOOOO)TS7 MS_Class=15
Mass test: TS0(xxxOOOOO)TS7 MS_Class=16
Mass test: TS0(xxxOOOOO)TS7 MS_Class=17
Mass test: TS0(xxxOOOOO)TS7 MS_Class=18
Mass test: TS0(xxxOOOOO)TS7 MS_Class=19
Mass test: TS0(xxxOOOOO)TS7 MS_Class=20
Mass test: TS0(xxxOOOOO)TS7 MS_Class=21
Mass test: TS0(xxxOOOOO)TS7 MS_Class=22
Mass test: TS0(xxxOOOOO)TS7 MS_Class=23
Mass test: TS0(xxxOOOOO)TS7 MS_Class=24
Mass test: TS0(xxxOOOOO)TS7 MS_Class=25
Mass test: TS0(xxxOOOOO)TS7 MS_Class=26
Mass test: TS0(xxxOOOOO)TS7 MS_Class=27
Mass test: TS0(xxxOOOOO)TS7 MS_Class=28
Mass test: TS0(xxxOOOOO)TS7 MS_Class=29
Mass test: TS0(xxxOOOOO)TS7 MS_Class=30
Mass test: TS0(xxxOOOOO)TS7 MS_Class=31
Mass test: TS0(xxxOOOOO)TS7 MS_Class=32
Mass test: TS0(xxxOOOOO)TS7 MS_Class=33
Mass test: TS0(xxxOOOOO)TS7 MS_Class=34
Mass test: TS0(xxxOOOOO)TS7 MS_Class=35
Mass test: TS0(xxxOOOOO)TS7 MS_Class=36
Mass test: TS0(xxxOOOOO)TS7 MS_Class=37
Mass test: TS0(xxxOOOOO)TS7 MS_Class=38
Mass test: TS0(xxxOOOOO)TS7 MS_Class=39
Mass test: TS0(xxxOOOOO)TS7 MS_Class=40
Mass test: TS0(xxxOOOOO)TS7 MS_Class=41
Mass test: TS0(xxxOOOOO)TS7 MS_Class=42
Mass test: TS0(xxxOOOOO)TS7 MS_Class=43
Mass test: TS0(xxxOOOOO)TS7 MS_Class=44
Mass test: TS0(xxxOOOOO)TS7 MS_Class=45
Mass test: TS0(xxOxxxxx)TS7 MS_Class=0
Mass test: TS0(xxOxxxxx)TS7 MS_Class=1
Mass test: TS0(xxOxxxxx)TS7 MS_Class=2
Mass test: TS0(xxOxxxxx)TS7 MS_Class=3
Mass test: TS0(xxOxxxxx)TS7 MS_Class=4
Mass test: TS0(xxOxxxxx)TS7 MS_Class=5
Mass test: TS0(xxOxxxxx)TS7 MS_Class=6
Mass test: TS0(xxOxxxxx)TS7 MS_Class=7
Mass test: TS0(xxOxxxxx)TS7 MS_Class=8
Mass test: TS0(xxOxxxxx)TS7 MS_Class=9
Mass test: TS0(xxOxxxxx)TS7 MS_Class=10
Mass test: TS0(xxOxxxxx)TS7 MS_Class=11
Mass test: TS0(xxOxxxxx)TS7 MS_Class=12
Mass test: TS0(xxOxxxxx)TS7 MS_Class=13
Mass test: TS0(xxOxxxxx)TS7 MS_Class=14
Mass test: TS0(xxOxxxxx)TS7 MS_Class=15
Mass test: TS0(xxOxxxxx)TS7 MS_Class=16
Mass test: TS0(xxOxxxxx)TS7 MS_Class=17
Mass test: TS0(xxOxxxxx)TS7 MS_Class=18
Mass test: TS0(xxOxxxxx)TS7 MS_Class=19
Mass test: TS0(xxOxxxxx)TS7 MS_Class=20
Mass test: TS0(xxOxxxxx)TS7 MS_Class=21
Mass test: TS0(xxOxxxxx)TS7 MS_Class=22
Mass test: TS0(xxOxxxxx)TS7 MS_Class=23
Mass test: TS0(xxOxxxxx)TS7 MS_Class=24
Mass test: TS0(xxOxxxxx)TS7 MS_Class=25
Mass test: TS0(xxOxxxxx)TS7 MS_Class=26
Mass test: TS0(xxOxxxxx)TS7 MS_Class=27
Mass test: TS0(xxOxxxxx)TS7 MS_Class=28
Mass test: TS0(xxOxxxxx)TS7 MS_Class=29
Mass test: TS0(xxOxxxxx)TS7 MS_Class=30
Mass test: TS0(xxOxxxxx)TS7 MS_Class=31
Mass test: TS0(xxOxxxxx)TS7 MS_Class=32
Mass test: TS0(xxOxxxxx)TS7 MS_Class=33
Mass test: TS0(xxOxxxxx)TS7 MS_Class=34
Mass test: TS0(xxOxxxxx)TS7 MS_Class=35
Mass test: TS0(xxOxxxxx)TS7 MS_Class=36
Mass test: TS0(xxOxxxxx)TS7 MS_Class=37
Mass test: TS0(xxOxxxxx)TS7 MS_Class=38
Mass test: TS0(xxOxxxxx)TS7 MS_Class=39
Mass test: TS0(xxOxxxxx)TS7 MS_Class=40
Mass test: TS0(xxOxxxxx)TS7 MS_Class=41
Mass test: TS0(xxOxxxxx)TS7 MS_Class=42
Mass test: TS0(xxOxxxxx)TS7 MS_Class=43
Mass test: TS0(xxOxxxxx)TS7 MS_Class=44
Mass test: TS0(xxOxxxxx)TS7 MS_Class=45
Mass test: TS0(xxOxxxxO)TS7 MS_Class=0
Mass test: TS0(xxOxxxxO)TS7 MS_Class=1
Mass test: TS0(xxOxxxxO)TS7 MS_Class=2
Mass test: TS0(xxOxxxxO)TS7 MS_Class=3
Mass test: TS0(xxOxxxxO)TS7 MS_Class=4
Mass test: TS0(xxOxxxxO)TS7 MS_Class=5
Mass test: TS0(xxOxxxxO)TS7 MS_Class=6
Mass test: TS0(xxOxxxxO)TS7 MS_Class=7
Mass test: TS0(xxOxxxxO)TS7 MS_Class=8
Mass test: TS0(xxOxxxxO)TS7 MS_Class=9
Mass test: TS0(xxOxxxxO)TS7 MS_Class=10
Mass test: TS0(xxOxxxxO)TS7 MS_Class=11
Mass test: TS0(xxOxxxxO)TS7 MS_Class=12
Mass test: TS0(xxOxxxxO)TS7 MS_Class=13
Mass test: TS0(xxOxxxxO)TS7 MS_Class=14
Mass test: TS0(xxOxxxxO)TS7 MS_Class=15
Mass test: TS0(xxOxxxxO)TS7 MS_Class=16
Mass test: TS0(xxOxxxxO)TS7 MS_Class=17
Mass test: TS0(xxOxxxxO)TS7 MS_Class=18
Mass test: TS0(xxOxxxxO)TS7 MS_Class=19
Mass test: TS0(xxOxxxxO)TS7 MS_Class=20
Mass test: TS0(xxOxxxxO)TS7 MS_Class=21
Mass test: TS0(xxOxxxxO)TS7 MS_Class=22
Mass test: TS0(xxOxxxxO)TS7 MS_Class=23
Mass test: TS0(xxOxxxxO)TS7 MS_Class=24
Mass test: TS0(xxOxxxxO)TS7 MS_Class=25
Mass test: TS0(xxOxxxxO)TS7 MS_Class=26
Mass test: TS0(xxOxxxxO)TS7 MS_Class=27
Mass test: TS0(xxOxxxxO)TS7 MS_Class=28
Mass test: TS0(xxOxxxxO)TS7 MS_Class=29
Mass test: TS0(xxOxxxxO)TS7 MS_Class=30
Mass test: TS0(xxOxxxxO)TS7 MS_Class=31
Mass test: TS0(xxOxxxxO)TS7 MS_Class=32
Mass test: TS0(xxOxxxxO)TS7 MS_Class=33
Mass test: TS0(xxOxxxxO)TS7 MS_Class=34
Mass test: TS0(xxOxxxxO)TS7 MS_Class=35
Mass test: TS0(xxOxxxxO)TS7 MS_Class=36
Mass test: TS0(xxOxxxxO)TS7 MS_Class=37
Mass test: TS0(xxOxxxxO)TS7 MS_Class=38
Mass test: TS0(xxOxxxxO)TS7 MS_Class=39
Mass test: TS0(xxOxxxxO)TS7 MS_Class=40
Mass test: TS0(xxOxxxxO)TS7 MS_Class=41
Mass test: TS0(xxOxxxxO)TS7 MS_Class=42
Mass test: TS0(xxOxxxxO)TS7 MS_Class=43
Mass test: TS0(xxOxxxxO)TS7 MS_Class=44
Mass test: TS0(xxOxxxxO)TS7 MS_Class=45
Mass test: TS0(xxOxxxOx)TS7 MS_Class=0
Mass test: TS0(xxOxxxOx)TS7 MS_Class=1
Mass test: TS0(xxOxxxOx)TS7 MS_Class=2
Mass test: TS0(xxOxxxOx)TS7 MS_Class=3
Mass test: TS0(xxOxxxOx)TS7 MS_Class=4
Mass test: TS0(xxOxxxOx)TS7 MS_Class=5
Mass test: TS0(xxOxxxOx)TS7 MS_Class=6
Mass test: TS0(xxOxxxOx)TS7 MS_Class=7
Mass test: TS0(xxOxxxOx)TS7 MS_Class=8
Mass test: TS0(xxOxxxOx)TS7 MS_Class=9
Mass test: TS0(xxOxxxOx)TS7 MS_Class=10
Mass test: TS0(xxOxxxOx)TS7 MS_Class=11
Mass test: TS0(xxOxxxOx)TS7 MS_Class=12
Mass test: TS0(xxOxxxOx)TS7 MS_Class=13
Mass test: TS0(xxOxxxOx)TS7 MS_Class=14
Mass test: TS0(xxOxxxOx)TS7 MS_Class=15
Mass test: TS0(xxOxxxOx)TS7 MS_Class=16
Mass test: TS0(xxOxxxOx)TS7 MS_Class=17
Mass test: TS0(xxOxxxOx)TS7 MS_Class=18
Mass test: TS0(xxOxxxOx)TS7 MS_Class=19
Mass test: TS0(xxOxxxOx)TS7 MS_Class=20
Mass test: TS0(xxOxxxOx)TS7 MS_Class=21
Mass test: TS0(xxOxxxOx)TS7 MS_Class=22
Mass test: TS0(xxOxxxOx)TS7 MS_Class=23
Mass test: TS0(xxOxxxOx)TS7 MS_Class=24
Mass test: TS0(xxOxxxOx)TS7 MS_Class=25
Mass test: TS0(xxOxxxOx)TS7 MS_Class=26
Mass test: TS0(xxOxxxOx)TS7 MS_Class=27
Mass test: TS0(xxOxxxOx)TS7 MS_Class=28
Mass test: TS0(xxOxxxOx)TS7 MS_Class=29
Mass test: TS0(xxOxxxOx)TS7 MS_Class=30
Mass test: TS0(xxOxxxOx)TS7 MS_Class=31
Mass test: TS0(xxOxxxOx)TS7 MS_Class=32
Mass test: TS0(xxOxxxOx)TS7 MS_Class=33
Mass test: TS0(xxOxxxOx)TS7 MS_Class=34
Mass test: TS0(xxOxxxOx)TS7 MS_Class=35
Mass test: TS0(xxOxxxOx)TS7 MS_Class=36
Mass test: TS0(xxOxxxOx)TS7 MS_Class=37
Mass test: TS0(xxOxxxOx)TS7 MS_Class=38
Mass test: TS0(xxOxxxOx)TS7 MS_Class=39
Mass test: TS0(xxOxxxOx)TS7 MS_Class=40
Mass test: TS0(xxOxxxOx)TS7 MS_Class=41
Mass test: TS0(xxOxxxOx)TS7 MS_Class=42
Mass test: TS0(xxOxxxOx)TS7 MS_Class=43
Mass test: TS0(xxOxxxOx)TS7 MS_Class=44
Mass test: TS0(xxOxxxOx)TS7 MS_Class=45
Mass test: TS0(xxOxxxOO)TS7 MS_Class=0
Mass test: TS0(xxOxxxOO)TS7 MS_Class=1
Mass test: TS0(xxOxxxOO)TS7 MS_Class=2
Mass test: TS0(xxOxxxOO)TS7 MS_Class=3
Mass test: TS0(xxOxxxOO)TS7 MS_Class=4
Mass test: TS0(xxOxxxOO)TS7 MS_Class=5
Mass test: TS0(xxOxxxOO)TS7 MS_Class=6
Mass test: TS0(xxOxxxOO)TS7 MS_Class=7
Mass test: TS0(xxOxxxOO)TS7 MS_Class=8
Mass test: TS0(xxOxxxOO)TS7 MS_Class=9
Mass test: TS0(xxOxxxOO)TS7 MS_Class=10
Mass test: TS0(xxOxxxOO)TS7 MS_Class=11
Mass test: TS0(xxOxxxOO)TS7 MS_Class=12
Mass test: TS0(xxOxxxOO)TS7 MS_Class=13
Mass test: TS0(xxOxxxOO)TS7 MS_Class=14
Mass test: TS0(xxOxxxOO)TS7 MS_Class=15
Mass test: TS0(xxOxxxOO)TS7 MS_Class=16
Mass test: TS0(xxOxxxOO)TS7 MS_Class=17
Mass test: TS0(xxOxxxOO)TS7 MS_Class=18
Mass test: TS0(xxOxxxOO)TS7 MS_Class=19
Mass test: TS0(xxOxxxOO)TS7 MS_Class=20
Mass test: TS0(xxOxxxOO)TS7 MS_Class=21
Mass test: TS0(xxOxxxOO)TS7 MS_Class=22
Mass test: TS0(xxOxxxOO)TS7 MS_Class=23
Mass test: TS0(xxOxxxOO)TS7 MS_Class=24
Mass test: TS0(xxOxxxOO)TS7 MS_Class=25
Mass test: TS0(xxOxxxOO)TS7 MS_Class=26
Mass test: TS0(xxOxxxOO)TS7 MS_Class=27
Mass test: TS0(xxOxxxOO)TS7 MS_Class=28
Mass test: TS0(xxOxxxOO)TS7 MS_Class=29
Mass test: TS0(xxOxxxOO)TS7 MS_Class=30
Mass test: TS0(xxOxxxOO)TS7 MS_Class=31
Mass test: TS0(xxOxxxOO)TS7 MS_Class=32
Mass test: TS0(xxOxxxOO)TS7 MS_Class=33
Mass test: TS0(xxOxxxOO)TS7 MS_Class=34
Mass test: TS0(xxOxxxOO)TS7 MS_Class=35
Mass test: TS0(xxOxxxOO)TS7 MS_Class=36
Mass test: TS0(xxOxxxOO)TS7 MS_Class=37
Mass test: TS0(xxOxxxOO)TS7 MS_Class=38
Mass test: TS0(xxOxxxOO)TS7 MS_Class=39
Mass test: TS0(xxOxxxOO)TS7 MS_Class=40
Mass test: TS0(xxOxxxOO)TS7 MS_Class=41
Mass test: TS0(xxOxxxOO)TS7 MS_Class=42
Mass test: TS0(xxOxxxOO)TS7 MS_Class=43
Mass test: TS0(xxOxxxOO)TS7 MS_Class=44
Mass test: TS0(xxOxxxOO)TS7 MS_Class=45
Mass test: TS0(xxOxxOxx)TS7 MS_Class=0
Mass test: TS0(xxOxxOxx)TS7 MS_Class=1
Mass test: TS0(xxOxxOxx)TS7 MS_Class=2
Mass test: TS0(xxOxxOxx)TS7 MS_Class=3
Mass test: TS0(xxOxxOxx)TS7 MS_Class=4
Mass test: TS0(xxOxxOxx)TS7 MS_Class=5
Mass test: TS0(xxOxxOxx)TS7 MS_Class=6
Mass test: TS0(xxOxxOxx)TS7 MS_Class=7
Mass test: TS0(xxOxxOxx)TS7 MS_Class=8
Mass test: TS0(xxOxxOxx)TS7 MS_Class=9
Mass test: TS0(xxOxxOxx)TS7 MS_Class=10
Mass test: TS0(xxOxxOxx)TS7 MS_Class=11
Mass test: TS0(xxOxxOxx)TS7 MS_Class=12
Mass test: TS0(xxOxxOxx)TS7 MS_Class=13
Mass test: TS0(xxOxxOxx)TS7 MS_Class=14
Mass test: TS0(xxOxxOxx)TS7 MS_Class=15
Mass test: TS0(xxOxxOxx)TS7 MS_Class=16
Mass test: TS0(xxOxxOxx)TS7 MS_Class=17
Mass test: TS0(xxOxxOxx)TS7 MS_Class=18
Mass test: TS0(xxOxxOxx)TS7 MS_Class=19
Mass test: TS0(xxOxxOxx)TS7 MS_Class=20
Mass test: TS0(xxOxxOxx)TS7 MS_Class=21
Mass test: TS0(xxOxxOxx)TS7 MS_Class=22
Mass test: TS0(xxOxxOxx)TS7 MS_Class=23
Mass test: TS0(xxOxxOxx)TS7 MS_Class=24
Mass test: TS0(xxOxxOxx)TS7 MS_Class=25
Mass test: TS0(xxOxxOxx)TS7 MS_Class=26
Mass test: TS0(xxOxxOxx)TS7 MS_Class=27
Mass test: TS0(xxOxxOxx)TS7 MS_Class=28
Mass test: TS0(xxOxxOxx)TS7 MS_Class=29
Mass test: TS0(xxOxxOxx)TS7 MS_Class=30
Mass test: TS0(xxOxxOxx)TS7 MS_Class=31
Mass test: TS0(xxOxxOxx)TS7 MS_Class=32
Mass test: TS0(xxOxxOxx)TS7 MS_Class=33
Mass test: TS0(xxOxxOxx)TS7 MS_Class=34
Mass test: TS0(xxOxxOxx)TS7 MS_Class=35
Mass test: TS0(xxOxxOxx)TS7 MS_Class=36
Mass test: TS0(xxOxxOxx)TS7 MS_Class=37
Mass test: TS0(xxOxxOxx)TS7 MS_Class=38
Mass test: TS0(xxOxxOxx)TS7 MS_Class=39
Mass test: TS0(xxOxxOxx)TS7 MS_Class=40
Mass test: TS0(xxOxxOxx)TS7 MS_Class=41
Mass test: TS0(xxOxxOxx)TS7 MS_Class=42
Mass test: TS0(xxOxxOxx)TS7 MS_Class=43
Mass test: TS0(xxOxxOxx)TS7 MS_Class=44
Mass test: TS0(xxOxxOxx)TS7 MS_Class=45
Mass test: TS0(xxOxxOxO)TS7 MS_Class=0
Mass test: TS0(xxOxxOxO)TS7 MS_Class=1
Mass test: TS0(xxOxxOxO)TS7 MS_Class=2
Mass test: TS0(xxOxxOxO)TS7 MS_Class=3
Mass test: TS0(xxOxxOxO)TS7 MS_Class=4
Mass test: TS0(xxOxxOxO)TS7 MS_Class=5
Mass test: TS0(xxOxxOxO)TS7 MS_Class=6
Mass test: TS0(xxOxxOxO)TS7 MS_Class=7
Mass test: TS0(xxOxxOxO)TS7 MS_Class=8
Mass test: TS0(xxOxxOxO)TS7 MS_Class=9
Mass test: TS0(xxOxxOxO)TS7 MS_Class=10
Mass test: TS0(xxOxxOxO)TS7 MS_Class=11
Mass test: TS0(xxOxxOxO)TS7 MS_Class=12
Mass test: TS0(xxOxxOxO)TS7 MS_Class=13
Mass test: TS0(xxOxxOxO)TS7 MS_Class=14
Mass test: TS0(xxOxxOxO)TS7 MS_Class=15
Mass test: TS0(xxOxxOxO)TS7 MS_Class=16
Mass test: TS0(xxOxxOxO)TS7 MS_Class=17
Mass test: TS0(xxOxxOxO)TS7 MS_Class=18
Mass test: TS0(xxOxxOxO)TS7 MS_Class=19
Mass test: TS0(xxOxxOxO)TS7 MS_Class=20
Mass test: TS0(xxOxxOxO)TS7 MS_Class=21
Mass test: TS0(xxOxxOxO)TS7 MS_Class=22
Mass test: TS0(xxOxxOxO)TS7 MS_Class=23
Mass test: TS0(xxOxxOxO)TS7 MS_Class=24
Mass test: TS0(xxOxxOxO)TS7 MS_Class=25
Mass test: TS0(xxOxxOxO)TS7 MS_Class=26
Mass test: TS0(xxOxxOxO)TS7 MS_Class=27
Mass test: TS0(xxOxxOxO)TS7 MS_Class=28
Mass test: TS0(xxOxxOxO)TS7 MS_Class=29
Mass test: TS0(xxOxxOxO)TS7 MS_Class=30
Mass test: TS0(xxOxxOxO)TS7 MS_Class=31
Mass test: TS0(xxOxxOxO)TS7 MS_Class=32
Mass test: TS0(xxOxxOxO)TS7 MS_Class=33
Mass test: TS0(xxOxxOxO)TS7 MS_Class=34
Mass test: TS0(xxOxxOxO)TS7 MS_Class=35
Mass test: TS0(xxOxxOxO)TS7 MS_Class=36
Mass test: TS0(xxOxxOxO)TS7 MS_Class=37
Mass test: TS0(xxOxxOxO)TS7 MS_Class=38
Mass test: TS0(xxOxxOxO)TS7 MS_Class=39
Mass test: TS0(xxOxxOxO)TS7 MS_Class=40
Mass test: TS0(xxOxxOxO)TS7 MS_Class=41
Mass test: TS0(xxOxxOxO)TS7 MS_Class=42
Mass test: TS0(xxOxxOxO)TS7 MS_Class=43
Mass test: TS0(xxOxxOxO)TS7 MS_Class=44
Mass test: TS0(xxOxxOxO)TS7 MS_Class=45
Mass test: TS0(xxOxxOOx)TS7 MS_Class=0
Mass test: TS0(xxOxxOOx)TS7 MS_Class=1
Mass test: TS0(xxOxxOOx)TS7 MS_Class=2
Mass test: TS0(xxOxxOOx)TS7 MS_Class=3
Mass test: TS0(xxOxxOOx)TS7 MS_Class=4
Mass test: TS0(xxOxxOOx)TS7 MS_Class=5
Mass test: TS0(xxOxxOOx)TS7 MS_Class=6
Mass test: TS0(xxOxxOOx)TS7 MS_Class=7
Mass test: TS0(xxOxxOOx)TS7 MS_Class=8
Mass test: TS0(xxOxxOOx)TS7 MS_Class=9
Mass test: TS0(xxOxxOOx)TS7 MS_Class=10
Mass test: TS0(xxOxxOOx)TS7 MS_Class=11
Mass test: TS0(xxOxxOOx)TS7 MS_Class=12
Mass test: TS0(xxOxxOOx)TS7 MS_Class=13
Mass test: TS0(xxOxxOOx)TS7 MS_Class=14
Mass test: TS0(xxOxxOOx)TS7 MS_Class=15
Mass test: TS0(xxOxxOOx)TS7 MS_Class=16
Mass test: TS0(xxOxxOOx)TS7 MS_Class=17
Mass test: TS0(xxOxxOOx)TS7 MS_Class=18
Mass test: TS0(xxOxxOOx)TS7 MS_Class=19
Mass test: TS0(xxOxxOOx)TS7 MS_Class=20
Mass test: TS0(xxOxxOOx)TS7 MS_Class=21
Mass test: TS0(xxOxxOOx)TS7 MS_Class=22
Mass test: TS0(xxOxxOOx)TS7 MS_Class=23
Mass test: TS0(xxOxxOOx)TS7 MS_Class=24
Mass test: TS0(xxOxxOOx)TS7 MS_Class=25
Mass test: TS0(xxOxxOOx)TS7 MS_Class=26
Mass test: TS0(xxOxxOOx)TS7 MS_Class=27
Mass test: TS0(xxOxxOOx)TS7 MS_Class=28
Mass test: TS0(xxOxxOOx)TS7 MS_Class=29
Mass test: TS0(xxOxxOOx)TS7 MS_Class=30
Mass test: TS0(xxOxxOOx)TS7 MS_Class=31
Mass test: TS0(xxOxxOOx)TS7 MS_Class=32
Mass test: TS0(xxOxxOOx)TS7 MS_Class=33
Mass test: TS0(xxOxxOOx)TS7 MS_Class=34
Mass test: TS0(xxOxxOOx)TS7 MS_Class=35
Mass test: TS0(xxOxxOOx)TS7 MS_Class=36
Mass test: TS0(xxOxxOOx)TS7 MS_Class=37
Mass test: TS0(xxOxxOOx)TS7 MS_Class=38
Mass test: TS0(xxOxxOOx)TS7 MS_Class=39
Mass test: TS0(xxOxxOOx)TS7 MS_Class=40
Mass test: TS0(xxOxxOOx)TS7 MS_Class=41
Mass test: TS0(xxOxxOOx)TS7 MS_Class=42
Mass test: TS0(xxOxxOOx)TS7 MS_Class=43
Mass test: TS0(xxOxxOOx)TS7 MS_Class=44
Mass test: TS0(xxOxxOOx)TS7 MS_Class=45
Mass test: TS0(xxOxxOOO)TS7 MS_Class=0
Mass test: TS0(xxOxxOOO)TS7 MS_Class=1
Mass test: TS0(xxOxxOOO)TS7 MS_Class=2
Mass test: TS0(xxOxxOOO)TS7 MS_Class=3
Mass test: TS0(xxOxxOOO)TS7 MS_Class=4
Mass test: TS0(xxOxxOOO)TS7 MS_Class=5
Mass test: TS0(xxOxxOOO)TS7 MS_Class=6
Mass test: TS0(xxOxxOOO)TS7 MS_Class=7
Mass test: TS0(xxOxxOOO)TS7 MS_Class=8
Mass test: TS0(xxOxxOOO)TS7 MS_Class=9
Mass test: TS0(xxOxxOOO)TS7 MS_Class=10
Mass test: TS0(xxOxxOOO)TS7 MS_Class=11
Mass test: TS0(xxOxxOOO)TS7 MS_Class=12
Mass test: TS0(xxOxxOOO)TS7 MS_Class=13
Mass test: TS0(xxOxxOOO)TS7 MS_Class=14
Mass test: TS0(xxOxxOOO)TS7 MS_Class=15
Mass test: TS0(xxOxxOOO)TS7 MS_Class=16
Mass test: TS0(xxOxxOOO)TS7 MS_Class=17
Mass test: TS0(xxOxxOOO)TS7 MS_Class=18
Mass test: TS0(xxOxxOOO)TS7 MS_Class=19
Mass test: TS0(xxOxxOOO)TS7 MS_Class=20
Mass test: TS0(xxOxxOOO)TS7 MS_Class=21
Mass test: TS0(xxOxxOOO)TS7 MS_Class=22
Mass test: TS0(xxOxxOOO)TS7 MS_Class=23
Mass test: TS0(xxOxxOOO)TS7 MS_Class=24
Mass test: TS0(xxOxxOOO)TS7 MS_Class=25
Mass test: TS0(xxOxxOOO)TS7 MS_Class=26
Mass test: TS0(xxOxxOOO)TS7 MS_Class=27
Mass test: TS0(xxOxxOOO)TS7 MS_Class=28
Mass test: TS0(xxOxxOOO)TS7 MS_Class=29
Mass test: TS0(xxOxxOOO)TS7 MS_Class=30
Mass test: TS0(xxOxxOOO)TS7 MS_Class=31
Mass test: TS0(xxOxxOOO)TS7 MS_Class=32
Mass test: TS0(xxOxxOOO)TS7 MS_Class=33
Mass test: TS0(xxOxxOOO)TS7 MS_Class=34
Mass test: TS0(xxOxxOOO)TS7 MS_Class=35
Mass test: TS0(xxOxxOOO)TS7 MS_Class=36
Mass test: TS0(xxOxxOOO)TS7 MS_Class=37
Mass test: TS0(xxOxxOOO)TS7 MS_Class=38
Mass test: TS0(xxOxxOOO)TS7 MS_Class=39
Mass test: TS0(xxOxxOOO)TS7 MS_Class=40
Mass test: TS0(xxOxxOOO)TS7 MS_Class=41
Mass test: TS0(xxOxxOOO)TS7 MS_Class=42
Mass test: TS0(xxOxxOOO)TS7 MS_Class=43
Mass test: TS0(xxOxxOOO)TS7 MS_Class=44
Mass test: TS0(xxOxxOOO)TS7 MS_Class=45
Mass test: TS0(xxOxOxxx)TS7 MS_Class=0
Mass test: TS0(xxOxOxxx)TS7 MS_Class=1
Mass test: TS0(xxOxOxxx)TS7 MS_Class=2
Mass test: TS0(xxOxOxxx)TS7 MS_Class=3
Mass test: TS0(xxOxOxxx)TS7 MS_Class=4
Mass test: TS0(xxOxOxxx)TS7 MS_Class=5
Mass test: TS0(xxOxOxxx)TS7 MS_Class=6
Mass test: TS0(xxOxOxxx)TS7 MS_Class=7
Mass test: TS0(xxOxOxxx)TS7 MS_Class=8
Mass test: TS0(xxOxOxxx)TS7 MS_Class=9
Mass test: TS0(xxOxOxxx)TS7 MS_Class=10
Mass test: TS0(xxOxOxxx)TS7 MS_Class=11
Mass test: TS0(xxOxOxxx)TS7 MS_Class=12
Mass test: TS0(xxOxOxxx)TS7 MS_Class=13
Mass test: TS0(xxOxOxxx)TS7 MS_Class=14
Mass test: TS0(xxOxOxxx)TS7 MS_Class=15
Mass test: TS0(xxOxOxxx)TS7 MS_Class=16
Mass test: TS0(xxOxOxxx)TS7 MS_Class=17
Mass test: TS0(xxOxOxxx)TS7 MS_Class=18
Mass test: TS0(xxOxOxxx)TS7 MS_Class=19
Mass test: TS0(xxOxOxxx)TS7 MS_Class=20
Mass test: TS0(xxOxOxxx)TS7 MS_Class=21
Mass test: TS0(xxOxOxxx)TS7 MS_Class=22
Mass test: TS0(xxOxOxxx)TS7 MS_Class=23
Mass test: TS0(xxOxOxxx)TS7 MS_Class=24
Mass test: TS0(xxOxOxxx)TS7 MS_Class=25
Mass test: TS0(xxOxOxxx)TS7 MS_Class=26
Mass test: TS0(xxOxOxxx)TS7 MS_Class=27
Mass test: TS0(xxOxOxxx)TS7 MS_Class=28
Mass test: TS0(xxOxOxxx)TS7 MS_Class=29
Mass test: TS0(xxOxOxxx)TS7 MS_Class=30
Mass test: TS0(xxOxOxxx)TS7 MS_Class=31
Mass test: TS0(xxOxOxxx)TS7 MS_Class=32
Mass test: TS0(xxOxOxxx)TS7 MS_Class=33
Mass test: TS0(xxOxOxxx)TS7 MS_Class=34
Mass test: TS0(xxOxOxxx)TS7 MS_Class=35
Mass test: TS0(xxOxOxxx)TS7 MS_Class=36
Mass test: TS0(xxOxOxxx)TS7 MS_Class=37
Mass test: TS0(xxOxOxxx)TS7 MS_Class=38
Mass test: TS0(xxOxOxxx)TS7 MS_Class=39
Mass test: TS0(xxOxOxxx)TS7 MS_Class=40
Mass test: TS0(xxOxOxxx)TS7 MS_Class=41
Mass test: TS0(xxOxOxxx)TS7 MS_Class=42
Mass test: TS0(xxOxOxxx)TS7 MS_Class=43
Mass test: TS0(xxOxOxxx)TS7 MS_Class=44
Mass test: TS0(xxOxOxxx)TS7 MS_Class=45
Mass test: TS0(xxOxOxxO)TS7 MS_Class=0
Mass test: TS0(xxOxOxxO)TS7 MS_Class=1
Mass test: TS0(xxOxOxxO)TS7 MS_Class=2
Mass test: TS0(xxOxOxxO)TS7 MS_Class=3
Mass test: TS0(xxOxOxxO)TS7 MS_Class=4
Mass test: TS0(xxOxOxxO)TS7 MS_Class=5
Mass test: TS0(xxOxOxxO)TS7 MS_Class=6
Mass test: TS0(xxOxOxxO)TS7 MS_Class=7
Mass test: TS0(xxOxOxxO)TS7 MS_Class=8
Mass test: TS0(xxOxOxxO)TS7 MS_Class=9
Mass test: TS0(xxOxOxxO)TS7 MS_Class=10
Mass test: TS0(xxOxOxxO)TS7 MS_Class=11
Mass test: TS0(xxOxOxxO)TS7 MS_Class=12
Mass test: TS0(xxOxOxxO)TS7 MS_Class=13
Mass test: TS0(xxOxOxxO)TS7 MS_Class=14
Mass test: TS0(xxOxOxxO)TS7 MS_Class=15
Mass test: TS0(xxOxOxxO)TS7 MS_Class=16
Mass test: TS0(xxOxOxxO)TS7 MS_Class=17
Mass test: TS0(xxOxOxxO)TS7 MS_Class=18
Mass test: TS0(xxOxOxxO)TS7 MS_Class=19
Mass test: TS0(xxOxOxxO)TS7 MS_Class=20
Mass test: TS0(xxOxOxxO)TS7 MS_Class=21
Mass test: TS0(xxOxOxxO)TS7 MS_Class=22
Mass test: TS0(xxOxOxxO)TS7 MS_Class=23
Mass test: TS0(xxOxOxxO)TS7 MS_Class=24
Mass test: TS0(xxOxOxxO)TS7 MS_Class=25
Mass test: TS0(xxOxOxxO)TS7 MS_Class=26
Mass test: TS0(xxOxOxxO)TS7 MS_Class=27
Mass test: TS0(xxOxOxxO)TS7 MS_Class=28
Mass test: TS0(xxOxOxxO)TS7 MS_Class=29
Mass test: TS0(xxOxOxxO)TS7 MS_Class=30
Mass test: TS0(xxOxOxxO)TS7 MS_Class=31
Mass test: TS0(xxOxOxxO)TS7 MS_Class=32
Mass test: TS0(xxOxOxxO)TS7 MS_Class=33
Mass test: TS0(xxOxOxxO)TS7 MS_Class=34
Mass test: TS0(xxOxOxxO)TS7 MS_Class=35
Mass test: TS0(xxOxOxxO)TS7 MS_Class=36
Mass test: TS0(xxOxOxxO)TS7 MS_Class=37
Mass test: TS0(xxOxOxxO)TS7 MS_Class=38
Mass test: TS0(xxOxOxxO)TS7 MS_Class=39
Mass test: TS0(xxOxOxxO)TS7 MS_Class=40
Mass test: TS0(xxOxOxxO)TS7 MS_Class=41
Mass test: TS0(xxOxOxxO)TS7 MS_Class=42
Mass test: TS0(xxOxOxxO)TS7 MS_Class=43
Mass test: TS0(xxOxOxxO)TS7 MS_Class=44
Mass test: TS0(xxOxOxxO)TS7 MS_Class=45
Mass test: TS0(xxOxOxOx)TS7 MS_Class=0
Mass test: TS0(xxOxOxOx)TS7 MS_Class=1
Mass test: TS0(xxOxOxOx)TS7 MS_Class=2
Mass test: TS0(xxOxOxOx)TS7 MS_Class=3
Mass test: TS0(xxOxOxOx)TS7 MS_Class=4
Mass test: TS0(xxOxOxOx)TS7 MS_Class=5
Mass test: TS0(xxOxOxOx)TS7 MS_Class=6
Mass test: TS0(xxOxOxOx)TS7 MS_Class=7
Mass test: TS0(xxOxOxOx)TS7 MS_Class=8
Mass test: TS0(xxOxOxOx)TS7 MS_Class=9
Mass test: TS0(xxOxOxOx)TS7 MS_Class=10
Mass test: TS0(xxOxOxOx)TS7 MS_Class=11
Mass test: TS0(xxOxOxOx)TS7 MS_Class=12
Mass test: TS0(xxOxOxOx)TS7 MS_Class=13
Mass test: TS0(xxOxOxOx)TS7 MS_Class=14
Mass test: TS0(xxOxOxOx)TS7 MS_Class=15
Mass test: TS0(xxOxOxOx)TS7 MS_Class=16
Mass test: TS0(xxOxOxOx)TS7 MS_Class=17
Mass test: TS0(xxOxOxOx)TS7 MS_Class=18
Mass test: TS0(xxOxOxOx)TS7 MS_Class=19
Mass test: TS0(xxOxOxOx)TS7 MS_Class=20
Mass test: TS0(xxOxOxOx)TS7 MS_Class=21
Mass test: TS0(xxOxOxOx)TS7 MS_Class=22
Mass test: TS0(xxOxOxOx)TS7 MS_Class=23
Mass test: TS0(xxOxOxOx)TS7 MS_Class=24
Mass test: TS0(xxOxOxOx)TS7 MS_Class=25
Mass test: TS0(xxOxOxOx)TS7 MS_Class=26
Mass test: TS0(xxOxOxOx)TS7 MS_Class=27
Mass test: TS0(xxOxOxOx)TS7 MS_Class=28
Mass test: TS0(xxOxOxOx)TS7 MS_Class=29
Mass test: TS0(xxOxOxOx)TS7 MS_Class=30
Mass test: TS0(xxOxOxOx)TS7 MS_Class=31
Mass test: TS0(xxOxOxOx)TS7 MS_Class=32
Mass test: TS0(xxOxOxOx)TS7 MS_Class=33
Mass test: TS0(xxOxOxOx)TS7 MS_Class=34
Mass test: TS0(xxOxOxOx)TS7 MS_Class=35
Mass test: TS0(xxOxOxOx)TS7 MS_Class=36
Mass test: TS0(xxOxOxOx)TS7 MS_Class=37
Mass test: TS0(xxOxOxOx)TS7 MS_Class=38
Mass test: TS0(xxOxOxOx)TS7 MS_Class=39
Mass test: TS0(xxOxOxOx)TS7 MS_Class=40
Mass test: TS0(xxOxOxOx)TS7 MS_Class=41
Mass test: TS0(xxOxOxOx)TS7 MS_Class=42
Mass test: TS0(xxOxOxOx)TS7 MS_Class=43
Mass test: TS0(xxOxOxOx)TS7 MS_Class=44
Mass test: TS0(xxOxOxOx)TS7 MS_Class=45
Mass test: TS0(xxOxOxOO)TS7 MS_Class=0
Mass test: TS0(xxOxOxOO)TS7 MS_Class=1
Mass test: TS0(xxOxOxOO)TS7 MS_Class=2
Mass test: TS0(xxOxOxOO)TS7 MS_Class=3
Mass test: TS0(xxOxOxOO)TS7 MS_Class=4
Mass test: TS0(xxOxOxOO)TS7 MS_Class=5
Mass test: TS0(xxOxOxOO)TS7 MS_Class=6
Mass test: TS0(xxOxOxOO)TS7 MS_Class=7
Mass test: TS0(xxOxOxOO)TS7 MS_Class=8
Mass test: TS0(xxOxOxOO)TS7 MS_Class=9
Mass test: TS0(xxOxOxOO)TS7 MS_Class=10
Mass test: TS0(xxOxOxOO)TS7 MS_Class=11
Mass test: TS0(xxOxOxOO)TS7 MS_Class=12
Mass test: TS0(xxOxOxOO)TS7 MS_Class=13
Mass test: TS0(xxOxOxOO)TS7 MS_Class=14
Mass test: TS0(xxOxOxOO)TS7 MS_Class=15
Mass test: TS0(xxOxOxOO)TS7 MS_Class=16
Mass test: TS0(xxOxOxOO)TS7 MS_Class=17
Mass test: TS0(xxOxOxOO)TS7 MS_Class=18
Mass test: TS0(xxOxOxOO)TS7 MS_Class=19
Mass test: TS0(xxOxOxOO)TS7 MS_Class=20
Mass test: TS0(xxOxOxOO)TS7 MS_Class=21
Mass test: TS0(xxOxOxOO)TS7 MS_Class=22
Mass test: TS0(xxOxOxOO)TS7 MS_Class=23
Mass test: TS0(xxOxOxOO)TS7 MS_Class=24
Mass test: TS0(xxOxOxOO)TS7 MS_Class=25
Mass test: TS0(xxOxOxOO)TS7 MS_Class=26
Mass test: TS0(xxOxOxOO)TS7 MS_Class=27
Mass test: TS0(xxOxOxOO)TS7 MS_Class=28
Mass test: TS0(xxOxOxOO)TS7 MS_Class=29
Mass test: TS0(xxOxOxOO)TS7 MS_Class=30
Mass test: TS0(xxOxOxOO)TS7 MS_Class=31
Mass test: TS0(xxOxOxOO)TS7 MS_Class=32
Mass test: TS0(xxOxOxOO)TS7 MS_Class=33
Mass test: TS0(xxOxOxOO)TS7 MS_Class=34
Mass test: TS0(xxOxOxOO)TS7 MS_Class=35
Mass test: TS0(xxOxOxOO)TS7 MS_Class=36
Mass test: TS0(xxOxOxOO)TS7 MS_Class=37
Mass test: TS0(xxOxOxOO)TS7 MS_Class=38
Mass test: TS0(xxOxOxOO)TS7 MS_Class=39
Mass test: TS0(xxOxOxOO)TS7 MS_Class=40
Mass test: TS0(xxOxOxOO)TS7 MS_Class=41
Mass test: TS0(xxOxOxOO)TS7 MS_Class=42
Mass test: TS0(xxOxOxOO)TS7 MS_Class=43
Mass test: TS0(xxOxOxOO)TS7 MS_Class=44
Mass test: TS0(xxOxOxOO)TS7 MS_Class=45
Mass test: TS0(xxOxOOxx)TS7 MS_Class=0
Mass test: TS0(xxOxOOxx)TS7 MS_Class=1
Mass test: TS0(xxOxOOxx)TS7 MS_Class=2
Mass test: TS0(xxOxOOxx)TS7 MS_Class=3
Mass test: TS0(xxOxOOxx)TS7 MS_Class=4
Mass test: TS0(xxOxOOxx)TS7 MS_Class=5
Mass test: TS0(xxOxOOxx)TS7 MS_Class=6
Mass test: TS0(xxOxOOxx)TS7 MS_Class=7
Mass test: TS0(xxOxOOxx)TS7 MS_Class=8
Mass test: TS0(xxOxOOxx)TS7 MS_Class=9
Mass test: TS0(xxOxOOxx)TS7 MS_Class=10
Mass test: TS0(xxOxOOxx)TS7 MS_Class=11
Mass test: TS0(xxOxOOxx)TS7 MS_Class=12
Mass test: TS0(xxOxOOxx)TS7 MS_Class=13
Mass test: TS0(xxOxOOxx)TS7 MS_Class=14
Mass test: TS0(xxOxOOxx)TS7 MS_Class=15
Mass test: TS0(xxOxOOxx)TS7 MS_Class=16
Mass test: TS0(xxOxOOxx)TS7 MS_Class=17
Mass test: TS0(xxOxOOxx)TS7 MS_Class=18
Mass test: TS0(xxOxOOxx)TS7 MS_Class=19
Mass test: TS0(xxOxOOxx)TS7 MS_Class=20
Mass test: TS0(xxOxOOxx)TS7 MS_Class=21
Mass test: TS0(xxOxOOxx)TS7 MS_Class=22
Mass test: TS0(xxOxOOxx)TS7 MS_Class=23
Mass test: TS0(xxOxOOxx)TS7 MS_Class=24
Mass test: TS0(xxOxOOxx)TS7 MS_Class=25
Mass test: TS0(xxOxOOxx)TS7 MS_Class=26
Mass test: TS0(xxOxOOxx)TS7 MS_Class=27
Mass test: TS0(xxOxOOxx)TS7 MS_Class=28
Mass test: TS0(xxOxOOxx)TS7 MS_Class=29
Mass test: TS0(xxOxOOxx)TS7 MS_Class=30
Mass test: TS0(xxOxOOxx)TS7 MS_Class=31
Mass test: TS0(xxOxOOxx)TS7 MS_Class=32
Mass test: TS0(xxOxOOxx)TS7 MS_Class=33
Mass test: TS0(xxOxOOxx)TS7 MS_Class=34
Mass test: TS0(xxOxOOxx)TS7 MS_Class=35
Mass test: TS0(xxOxOOxx)TS7 MS_Class=36
Mass test: TS0(xxOxOOxx)TS7 MS_Class=37
Mass test: TS0(xxOxOOxx)TS7 MS_Class=38
Mass test: TS0(xxOxOOxx)TS7 MS_Class=39
Mass test: TS0(xxOxOOxx)TS7 MS_Class=40
Mass test: TS0(xxOxOOxx)TS7 MS_Class=41
Mass test: TS0(xxOxOOxx)TS7 MS_Class=42
Mass test: TS0(xxOxOOxx)TS7 MS_Class=43
Mass test: TS0(xxOxOOxx)TS7 MS_Class=44
Mass test: TS0(xxOxOOxx)TS7 MS_Class=45
Mass test: TS0(xxOxOOxO)TS7 MS_Class=0
Mass test: TS0(xxOxOOxO)TS7 MS_Class=1
Mass test: TS0(xxOxOOxO)TS7 MS_Class=2
Mass test: TS0(xxOxOOxO)TS7 MS_Class=3
Mass test: TS0(xxOxOOxO)TS7 MS_Class=4
Mass test: TS0(xxOxOOxO)TS7 MS_Class=5
Mass test: TS0(xxOxOOxO)TS7 MS_Class=6
Mass test: TS0(xxOxOOxO)TS7 MS_Class=7
Mass test: TS0(xxOxOOxO)TS7 MS_Class=8
Mass test: TS0(xxOxOOxO)TS7 MS_Class=9
Mass test: TS0(xxOxOOxO)TS7 MS_Class=10
Mass test: TS0(xxOxOOxO)TS7 MS_Class=11
Mass test: TS0(xxOxOOxO)TS7 MS_Class=12
Mass test: TS0(xxOxOOxO)TS7 MS_Class=13
Mass test: TS0(xxOxOOxO)TS7 MS_Class=14
Mass test: TS0(xxOxOOxO)TS7 MS_Class=15
Mass test: TS0(xxOxOOxO)TS7 MS_Class=16
Mass test: TS0(xxOxOOxO)TS7 MS_Class=17
Mass test: TS0(xxOxOOxO)TS7 MS_Class=18
Mass test: TS0(xxOxOOxO)TS7 MS_Class=19
Mass test: TS0(xxOxOOxO)TS7 MS_Class=20
Mass test: TS0(xxOxOOxO)TS7 MS_Class=21
Mass test: TS0(xxOxOOxO)TS7 MS_Class=22
Mass test: TS0(xxOxOOxO)TS7 MS_Class=23
Mass test: TS0(xxOxOOxO)TS7 MS_Class=24
Mass test: TS0(xxOxOOxO)TS7 MS_Class=25
Mass test: TS0(xxOxOOxO)TS7 MS_Class=26
Mass test: TS0(xxOxOOxO)TS7 MS_Class=27
Mass test: TS0(xxOxOOxO)TS7 MS_Class=28
Mass test: TS0(xxOxOOxO)TS7 MS_Class=29
Mass test: TS0(xxOxOOxO)TS7 MS_Class=30
Mass test: TS0(xxOxOOxO)TS7 MS_Class=31
Mass test: TS0(xxOxOOxO)TS7 MS_Class=32
Mass test: TS0(xxOxOOxO)TS7 MS_Class=33
Mass test: TS0(xxOxOOxO)TS7 MS_Class=34
Mass test: TS0(xxOxOOxO)TS7 MS_Class=35
Mass test: TS0(xxOxOOxO)TS7 MS_Class=36
Mass test: TS0(xxOxOOxO)TS7 MS_Class=37
Mass test: TS0(xxOxOOxO)TS7 MS_Class=38
Mass test: TS0(xxOxOOxO)TS7 MS_Class=39
Mass test: TS0(xxOxOOxO)TS7 MS_Class=40
Mass test: TS0(xxOxOOxO)TS7 MS_Class=41
Mass test: TS0(xxOxOOxO)TS7 MS_Class=42
Mass test: TS0(xxOxOOxO)TS7 MS_Class=43
Mass test: TS0(xxOxOOxO)TS7 MS_Class=44
Mass test: TS0(xxOxOOxO)TS7 MS_Class=45
Mass test: TS0(xxOxOOOx)TS7 MS_Class=0
Mass test: TS0(xxOxOOOx)TS7 MS_Class=1
Mass test: TS0(xxOxOOOx)TS7 MS_Class=2
Mass test: TS0(xxOxOOOx)TS7 MS_Class=3
Mass test: TS0(xxOxOOOx)TS7 MS_Class=4
Mass test: TS0(xxOxOOOx)TS7 MS_Class=5
Mass test: TS0(xxOxOOOx)TS7 MS_Class=6
Mass test: TS0(xxOxOOOx)TS7 MS_Class=7
Mass test: TS0(xxOxOOOx)TS7 MS_Class=8
Mass test: TS0(xxOxOOOx)TS7 MS_Class=9
Mass test: TS0(xxOxOOOx)TS7 MS_Class=10
Mass test: TS0(xxOxOOOx)TS7 MS_Class=11
Mass test: TS0(xxOxOOOx)TS7 MS_Class=12
Mass test: TS0(xxOxOOOx)TS7 MS_Class=13
Mass test: TS0(xxOxOOOx)TS7 MS_Class=14
Mass test: TS0(xxOxOOOx)TS7 MS_Class=15
Mass test: TS0(xxOxOOOx)TS7 MS_Class=16
Mass test: TS0(xxOxOOOx)TS7 MS_Class=17
Mass test: TS0(xxOxOOOx)TS7 MS_Class=18
Mass test: TS0(xxOxOOOx)TS7 MS_Class=19
Mass test: TS0(xxOxOOOx)TS7 MS_Class=20
Mass test: TS0(xxOxOOOx)TS7 MS_Class=21
Mass test: TS0(xxOxOOOx)TS7 MS_Class=22
Mass test: TS0(xxOxOOOx)TS7 MS_Class=23
Mass test: TS0(xxOxOOOx)TS7 MS_Class=24
Mass test: TS0(xxOxOOOx)TS7 MS_Class=25
Mass test: TS0(xxOxOOOx)TS7 MS_Class=26
Mass test: TS0(xxOxOOOx)TS7 MS_Class=27
Mass test: TS0(xxOxOOOx)TS7 MS_Class=28
Mass test: TS0(xxOxOOOx)TS7 MS_Class=29
Mass test: TS0(xxOxOOOx)TS7 MS_Class=30
Mass test: TS0(xxOxOOOx)TS7 MS_Class=31
Mass test: TS0(xxOxOOOx)TS7 MS_Class=32
Mass test: TS0(xxOxOOOx)TS7 MS_Class=33
Mass test: TS0(xxOxOOOx)TS7 MS_Class=34
Mass test: TS0(xxOxOOOx)TS7 MS_Class=35
Mass test: TS0(xxOxOOOx)TS7 MS_Class=36
Mass test: TS0(xxOxOOOx)TS7 MS_Class=37
Mass test: TS0(xxOxOOOx)TS7 MS_Class=38
Mass test: TS0(xxOxOOOx)TS7 MS_Class=39
Mass test: TS0(xxOxOOOx)TS7 MS_Class=40
Mass test: TS0(xxOxOOOx)TS7 MS_Class=41
Mass test: TS0(xxOxOOOx)TS7 MS_Class=42
Mass test: TS0(xxOxOOOx)TS7 MS_Class=43
Mass test: TS0(xxOxOOOx)TS7 MS_Class=44
Mass test: TS0(xxOxOOOx)TS7 MS_Class=45
Mass test: TS0(xxOxOOOO)TS7 MS_Class=0
Mass test: TS0(xxOxOOOO)TS7 MS_Class=1
Mass test: TS0(xxOxOOOO)TS7 MS_Class=2
Mass test: TS0(xxOxOOOO)TS7 MS_Class=3
Mass test: TS0(xxOxOOOO)TS7 MS_Class=4
Mass test: TS0(xxOxOOOO)TS7 MS_Class=5
Mass test: TS0(xxOxOOOO)TS7 MS_Class=6
Mass test: TS0(xxOxOOOO)TS7 MS_Class=7
Mass test: TS0(xxOxOOOO)TS7 MS_Class=8
Mass test: TS0(xxOxOOOO)TS7 MS_Class=9
Mass test: TS0(xxOxOOOO)TS7 MS_Class=10
Mass test: TS0(xxOxOOOO)TS7 MS_Class=11
Mass test: TS0(xxOxOOOO)TS7 MS_Class=12
Mass test: TS0(xxOxOOOO)TS7 MS_Class=13
Mass test: TS0(xxOxOOOO)TS7 MS_Class=14
Mass test: TS0(xxOxOOOO)TS7 MS_Class=15
Mass test: TS0(xxOxOOOO)TS7 MS_Class=16
Mass test: TS0(xxOxOOOO)TS7 MS_Class=17
Mass test: TS0(xxOxOOOO)TS7 MS_Class=18
Mass test: TS0(xxOxOOOO)TS7 MS_Class=19
Mass test: TS0(xxOxOOOO)TS7 MS_Class=20
Mass test: TS0(xxOxOOOO)TS7 MS_Class=21
Mass test: TS0(xxOxOOOO)TS7 MS_Class=22
Mass test: TS0(xxOxOOOO)TS7 MS_Class=23
Mass test: TS0(xxOxOOOO)TS7 MS_Class=24
Mass test: TS0(xxOxOOOO)TS7 MS_Class=25
Mass test: TS0(xxOxOOOO)TS7 MS_Class=26
Mass test: TS0(xxOxOOOO)TS7 MS_Class=27
Mass test: TS0(xxOxOOOO)TS7 MS_Class=28
Mass test: TS0(xxOxOOOO)TS7 MS_Class=29
Mass test: TS0(xxOxOOOO)TS7 MS_Class=30
Mass test: TS0(xxOxOOOO)TS7 MS_Class=31
Mass test: TS0(xxOxOOOO)TS7 MS_Class=32
Mass test: TS0(xxOxOOOO)TS7 MS_Class=33
Mass test: TS0(xxOxOOOO)TS7 MS_Class=34
Mass test: TS0(xxOxOOOO)TS7 MS_Class=35
Mass test: TS0(xxOxOOOO)TS7 MS_Class=36
Mass test: TS0(xxOxOOOO)TS7 MS_Class=37
Mass test: TS0(xxOxOOOO)TS7 MS_Class=38
Mass test: TS0(xxOxOOOO)TS7 MS_Class=39
Mass test: TS0(xxOxOOOO)TS7 MS_Class=40
Mass test: TS0(xxOxOOOO)TS7 MS_Class=41
Mass test: TS0(xxOxOOOO)TS7 MS_Class=42
Mass test: TS0(xxOxOOOO)TS7 MS_Class=43
Mass test: TS0(xxOxOOOO)TS7 MS_Class=44
Mass test: TS0(xxOxOOOO)TS7 MS_Class=45
Mass test: TS0(xxOOxxxx)TS7 MS_Class=0
Mass test: TS0(xxOOxxxx)TS7 MS_Class=1
Mass test: TS0(xxOOxxxx)TS7 MS_Class=2
Mass test: TS0(xxOOxxxx)TS7 MS_Class=3
Mass test: TS0(xxOOxxxx)TS7 MS_Class=4
Mass test: TS0(xxOOxxxx)TS7 MS_Class=5
Mass test: TS0(xxOOxxxx)TS7 MS_Class=6
Mass test: TS0(xxOOxxxx)TS7 MS_Class=7
Mass test: TS0(xxOOxxxx)TS7 MS_Class=8
Mass test: TS0(xxOOxxxx)TS7 MS_Class=9
Mass test: TS0(xxOOxxxx)TS7 MS_Class=10
Mass test: TS0(xxOOxxxx)TS7 MS_Class=11
Mass test: TS0(xxOOxxxx)TS7 MS_Class=12
Mass test: TS0(xxOOxxxx)TS7 MS_Class=13
Mass test: TS0(xxOOxxxx)TS7 MS_Class=14
Mass test: TS0(xxOOxxxx)TS7 MS_Class=15
Mass test: TS0(xxOOxxxx)TS7 MS_Class=16
Mass test: TS0(xxOOxxxx)TS7 MS_Class=17
Mass test: TS0(xxOOxxxx)TS7 MS_Class=18
Mass test: TS0(xxOOxxxx)TS7 MS_Class=19
Mass test: TS0(xxOOxxxx)TS7 MS_Class=20
Mass test: TS0(xxOOxxxx)TS7 MS_Class=21
Mass test: TS0(xxOOxxxx)TS7 MS_Class=22
Mass test: TS0(xxOOxxxx)TS7 MS_Class=23
Mass test: TS0(xxOOxxxx)TS7 MS_Class=24
Mass test: TS0(xxOOxxxx)TS7 MS_Class=25
Mass test: TS0(xxOOxxxx)TS7 MS_Class=26
Mass test: TS0(xxOOxxxx)TS7 MS_Class=27
Mass test: TS0(xxOOxxxx)TS7 MS_Class=28
Mass test: TS0(xxOOxxxx)TS7 MS_Class=29
Mass test: TS0(xxOOxxxx)TS7 MS_Class=30
Mass test: TS0(xxOOxxxx)TS7 MS_Class=31
Mass test: TS0(xxOOxxxx)TS7 MS_Class=32
Mass test: TS0(xxOOxxxx)TS7 MS_Class=33
Mass test: TS0(xxOOxxxx)TS7 MS_Class=34
Mass test: TS0(xxOOxxxx)TS7 MS_Class=35
Mass test: TS0(xxOOxxxx)TS7 MS_Class=36
Mass test: TS0(xxOOxxxx)TS7 MS_Class=37
Mass test: TS0(xxOOxxxx)TS7 MS_Class=38
Mass test: TS0(xxOOxxxx)TS7 MS_Class=39
Mass test: TS0(xxOOxxxx)TS7 MS_Class=40
Mass test: TS0(xxOOxxxx)TS7 MS_Class=41
Mass test: TS0(xxOOxxxx)TS7 MS_Class=42
Mass test: TS0(xxOOxxxx)TS7 MS_Class=43
Mass test: TS0(xxOOxxxx)TS7 MS_Class=44
Mass test: TS0(xxOOxxxx)TS7 MS_Class=45
Mass test: TS0(xxOOxxxO)TS7 MS_Class=0
Mass test: TS0(xxOOxxxO)TS7 MS_Class=1
Mass test: TS0(xxOOxxxO)TS7 MS_Class=2
Mass test: TS0(xxOOxxxO)TS7 MS_Class=3
Mass test: TS0(xxOOxxxO)TS7 MS_Class=4
Mass test: TS0(xxOOxxxO)TS7 MS_Class=5
Mass test: TS0(xxOOxxxO)TS7 MS_Class=6
Mass test: TS0(xxOOxxxO)TS7 MS_Class=7
Mass test: TS0(xxOOxxxO)TS7 MS_Class=8
Mass test: TS0(xxOOxxxO)TS7 MS_Class=9
Mass test: TS0(xxOOxxxO)TS7 MS_Class=10
Mass test: TS0(xxOOxxxO)TS7 MS_Class=11
Mass test: TS0(xxOOxxxO)TS7 MS_Class=12
Mass test: TS0(xxOOxxxO)TS7 MS_Class=13
Mass test: TS0(xxOOxxxO)TS7 MS_Class=14
Mass test: TS0(xxOOxxxO)TS7 MS_Class=15
Mass test: TS0(xxOOxxxO)TS7 MS_Class=16
Mass test: TS0(xxOOxxxO)TS7 MS_Class=17
Mass test: TS0(xxOOxxxO)TS7 MS_Class=18
Mass test: TS0(xxOOxxxO)TS7 MS_Class=19
Mass test: TS0(xxOOxxxO)TS7 MS_Class=20
Mass test: TS0(xxOOxxxO)TS7 MS_Class=21
Mass test: TS0(xxOOxxxO)TS7 MS_Class=22
Mass test: TS0(xxOOxxxO)TS7 MS_Class=23
Mass test: TS0(xxOOxxxO)TS7 MS_Class=24
Mass test: TS0(xxOOxxxO)TS7 MS_Class=25
Mass test: TS0(xxOOxxxO)TS7 MS_Class=26
Mass test: TS0(xxOOxxxO)TS7 MS_Class=27
Mass test: TS0(xxOOxxxO)TS7 MS_Class=28
Mass test: TS0(xxOOxxxO)TS7 MS_Class=29
Mass test: TS0(xxOOxxxO)TS7 MS_Class=30
Mass test: TS0(xxOOxxxO)TS7 MS_Class=31
Mass test: TS0(xxOOxxxO)TS7 MS_Class=32
Mass test: TS0(xxOOxxxO)TS7 MS_Class=33
Mass test: TS0(xxOOxxxO)TS7 MS_Class=34
Mass test: TS0(xxOOxxxO)TS7 MS_Class=35
Mass test: TS0(xxOOxxxO)TS7 MS_Class=36
Mass test: TS0(xxOOxxxO)TS7 MS_Class=37
Mass test: TS0(xxOOxxxO)TS7 MS_Class=38
Mass test: TS0(xxOOxxxO)TS7 MS_Class=39
Mass test: TS0(xxOOxxxO)TS7 MS_Class=40
Mass test: TS0(xxOOxxxO)TS7 MS_Class=41
Mass test: TS0(xxOOxxxO)TS7 MS_Class=42
Mass test: TS0(xxOOxxxO)TS7 MS_Class=43
Mass test: TS0(xxOOxxxO)TS7 MS_Class=44
Mass test: TS0(xxOOxxxO)TS7 MS_Class=45
Mass test: TS0(xxOOxxOx)TS7 MS_Class=0
Mass test: TS0(xxOOxxOx)TS7 MS_Class=1
Mass test: TS0(xxOOxxOx)TS7 MS_Class=2
Mass test: TS0(xxOOxxOx)TS7 MS_Class=3
Mass test: TS0(xxOOxxOx)TS7 MS_Class=4
Mass test: TS0(xxOOxxOx)TS7 MS_Class=5
Mass test: TS0(xxOOxxOx)TS7 MS_Class=6
Mass test: TS0(xxOOxxOx)TS7 MS_Class=7
Mass test: TS0(xxOOxxOx)TS7 MS_Class=8
Mass test: TS0(xxOOxxOx)TS7 MS_Class=9
Mass test: TS0(xxOOxxOx)TS7 MS_Class=10
Mass test: TS0(xxOOxxOx)TS7 MS_Class=11
Mass test: TS0(xxOOxxOx)TS7 MS_Class=12
Mass test: TS0(xxOOxxOx)TS7 MS_Class=13
Mass test: TS0(xxOOxxOx)TS7 MS_Class=14
Mass test: TS0(xxOOxxOx)TS7 MS_Class=15
Mass test: TS0(xxOOxxOx)TS7 MS_Class=16
Mass test: TS0(xxOOxxOx)TS7 MS_Class=17
Mass test: TS0(xxOOxxOx)TS7 MS_Class=18
Mass test: TS0(xxOOxxOx)TS7 MS_Class=19
Mass test: TS0(xxOOxxOx)TS7 MS_Class=20
Mass test: TS0(xxOOxxOx)TS7 MS_Class=21
Mass test: TS0(xxOOxxOx)TS7 MS_Class=22
Mass test: TS0(xxOOxxOx)TS7 MS_Class=23
Mass test: TS0(xxOOxxOx)TS7 MS_Class=24
Mass test: TS0(xxOOxxOx)TS7 MS_Class=25
Mass test: TS0(xxOOxxOx)TS7 MS_Class=26
Mass test: TS0(xxOOxxOx)TS7 MS_Class=27
Mass test: TS0(xxOOxxOx)TS7 MS_Class=28
Mass test: TS0(xxOOxxOx)TS7 MS_Class=29
Mass test: TS0(xxOOxxOx)TS7 MS_Class=30
Mass test: TS0(xxOOxxOx)TS7 MS_Class=31
Mass test: TS0(xxOOxxOx)TS7 MS_Class=32
Mass test: TS0(xxOOxxOx)TS7 MS_Class=33
Mass test: TS0(xxOOxxOx)TS7 MS_Class=34
Mass test: TS0(xxOOxxOx)TS7 MS_Class=35
Mass test: TS0(xxOOxxOx)TS7 MS_Class=36
Mass test: TS0(xxOOxxOx)TS7 MS_Class=37
Mass test: TS0(xxOOxxOx)TS7 MS_Class=38
Mass test: TS0(xxOOxxOx)TS7 MS_Class=39
Mass test: TS0(xxOOxxOx)TS7 MS_Class=40
Mass test: TS0(xxOOxxOx)TS7 MS_Class=41
Mass test: TS0(xxOOxxOx)TS7 MS_Class=42
Mass test: TS0(xxOOxxOx)TS7 MS_Class=43
Mass test: TS0(xxOOxxOx)TS7 MS_Class=44
Mass test: TS0(xxOOxxOx)TS7 MS_Class=45
Mass test: TS0(xxOOxxOO)TS7 MS_Class=0
Mass test: TS0(xxOOxxOO)TS7 MS_Class=1
Mass test: TS0(xxOOxxOO)TS7 MS_Class=2
Mass test: TS0(xxOOxxOO)TS7 MS_Class=3
Mass test: TS0(xxOOxxOO)TS7 MS_Class=4
Mass test: TS0(xxOOxxOO)TS7 MS_Class=5
Mass test: TS0(xxOOxxOO)TS7 MS_Class=6
Mass test: TS0(xxOOxxOO)TS7 MS_Class=7
Mass test: TS0(xxOOxxOO)TS7 MS_Class=8
Mass test: TS0(xxOOxxOO)TS7 MS_Class=9
Mass test: TS0(xxOOxxOO)TS7 MS_Class=10
Mass test: TS0(xxOOxxOO)TS7 MS_Class=11
Mass test: TS0(xxOOxxOO)TS7 MS_Class=12
Mass test: TS0(xxOOxxOO)TS7 MS_Class=13
Mass test: TS0(xxOOxxOO)TS7 MS_Class=14
Mass test: TS0(xxOOxxOO)TS7 MS_Class=15
Mass test: TS0(xxOOxxOO)TS7 MS_Class=16
Mass test: TS0(xxOOxxOO)TS7 MS_Class=17
Mass test: TS0(xxOOxxOO)TS7 MS_Class=18
Mass test: TS0(xxOOxxOO)TS7 MS_Class=19
Mass test: TS0(xxOOxxOO)TS7 MS_Class=20
Mass test: TS0(xxOOxxOO)TS7 MS_Class=21
Mass test: TS0(xxOOxxOO)TS7 MS_Class=22
Mass test: TS0(xxOOxxOO)TS7 MS_Class=23
Mass test: TS0(xxOOxxOO)TS7 MS_Class=24
Mass test: TS0(xxOOxxOO)TS7 MS_Class=25
Mass test: TS0(xxOOxxOO)TS7 MS_Class=26
Mass test: TS0(xxOOxxOO)TS7 MS_Class=27
Mass test: TS0(xxOOxxOO)TS7 MS_Class=28
Mass test: TS0(xxOOxxOO)TS7 MS_Class=29
Mass test: TS0(xxOOxxOO)TS7 MS_Class=30
Mass test: TS0(xxOOxxOO)TS7 MS_Class=31
Mass test: TS0(xxOOxxOO)TS7 MS_Class=32
Mass test: TS0(xxOOxxOO)TS7 MS_Class=33
Mass test: TS0(xxOOxxOO)TS7 MS_Class=34
Mass test: TS0(xxOOxxOO)TS7 MS_Class=35
Mass test: TS0(xxOOxxOO)TS7 MS_Class=36
Mass test: TS0(xxOOxxOO)TS7 MS_Class=37
Mass test: TS0(xxOOxxOO)TS7 MS_Class=38
Mass test: TS0(xxOOxxOO)TS7 MS_Class=39
Mass test: TS0(xxOOxxOO)TS7 MS_Class=40
Mass test: TS0(xxOOxxOO)TS7 MS_Class=41
Mass test: TS0(xxOOxxOO)TS7 MS_Class=42
Mass test: TS0(xxOOxxOO)TS7 MS_Class=43
Mass test: TS0(xxOOxxOO)TS7 MS_Class=44
Mass test: TS0(xxOOxxOO)TS7 MS_Class=45
Mass test: TS0(xxOOxOxx)TS7 MS_Class=0
Mass test: TS0(xxOOxOxx)TS7 MS_Class=1
Mass test: TS0(xxOOxOxx)TS7 MS_Class=2
Mass test: TS0(xxOOxOxx)TS7 MS_Class=3
Mass test: TS0(xxOOxOxx)TS7 MS_Class=4
Mass test: TS0(xxOOxOxx)TS7 MS_Class=5
Mass test: TS0(xxOOxOxx)TS7 MS_Class=6
Mass test: TS0(xxOOxOxx)TS7 MS_Class=7
Mass test: TS0(xxOOxOxx)TS7 MS_Class=8
Mass test: TS0(xxOOxOxx)TS7 MS_Class=9
Mass test: TS0(xxOOxOxx)TS7 MS_Class=10
Mass test: TS0(xxOOxOxx)TS7 MS_Class=11
Mass test: TS0(xxOOxOxx)TS7 MS_Class=12
Mass test: TS0(xxOOxOxx)TS7 MS_Class=13
Mass test: TS0(xxOOxOxx)TS7 MS_Class=14
Mass test: TS0(xxOOxOxx)TS7 MS_Class=15
Mass test: TS0(xxOOxOxx)TS7 MS_Class=16
Mass test: TS0(xxOOxOxx)TS7 MS_Class=17
Mass test: TS0(xxOOxOxx)TS7 MS_Class=18
Mass test: TS0(xxOOxOxx)TS7 MS_Class=19
Mass test: TS0(xxOOxOxx)TS7 MS_Class=20
Mass test: TS0(xxOOxOxx)TS7 MS_Class=21
Mass test: TS0(xxOOxOxx)TS7 MS_Class=22
Mass test: TS0(xxOOxOxx)TS7 MS_Class=23
Mass test: TS0(xxOOxOxx)TS7 MS_Class=24
Mass test: TS0(xxOOxOxx)TS7 MS_Class=25
Mass test: TS0(xxOOxOxx)TS7 MS_Class=26
Mass test: TS0(xxOOxOxx)TS7 MS_Class=27
Mass test: TS0(xxOOxOxx)TS7 MS_Class=28
Mass test: TS0(xxOOxOxx)TS7 MS_Class=29
Mass test: TS0(xxOOxOxx)TS7 MS_Class=30
Mass test: TS0(xxOOxOxx)TS7 MS_Class=31
Mass test: TS0(xxOOxOxx)TS7 MS_Class=32
Mass test: TS0(xxOOxOxx)TS7 MS_Class=33
Mass test: TS0(xxOOxOxx)TS7 MS_Class=34
Mass test: TS0(xxOOxOxx)TS7 MS_Class=35
Mass test: TS0(xxOOxOxx)TS7 MS_Class=36
Mass test: TS0(xxOOxOxx)TS7 MS_Class=37
Mass test: TS0(xxOOxOxx)TS7 MS_Class=38
Mass test: TS0(xxOOxOxx)TS7 MS_Class=39
Mass test: TS0(xxOOxOxx)TS7 MS_Class=40
Mass test: TS0(xxOOxOxx)TS7 MS_Class=41
Mass test: TS0(xxOOxOxx)TS7 MS_Class=42
Mass test: TS0(xxOOxOxx)TS7 MS_Class=43
Mass test: TS0(xxOOxOxx)TS7 MS_Class=44
Mass test: TS0(xxOOxOxx)TS7 MS_Class=45
Mass test: TS0(xxOOxOxO)TS7 MS_Class=0
Mass test: TS0(xxOOxOxO)TS7 MS_Class=1
Mass test: TS0(xxOOxOxO)TS7 MS_Class=2
Mass test: TS0(xxOOxOxO)TS7 MS_Class=3
Mass test: TS0(xxOOxOxO)TS7 MS_Class=4
Mass test: TS0(xxOOxOxO)TS7 MS_Class=5
Mass test: TS0(xxOOxOxO)TS7 MS_Class=6
Mass test: TS0(xxOOxOxO)TS7 MS_Class=7
Mass test: TS0(xxOOxOxO)TS7 MS_Class=8
Mass test: TS0(xxOOxOxO)TS7 MS_Class=9
Mass test: TS0(xxOOxOxO)TS7 MS_Class=10
Mass test: TS0(xxOOxOxO)TS7 MS_Class=11
Mass test: TS0(xxOOxOxO)TS7 MS_Class=12
Mass test: TS0(xxOOxOxO)TS7 MS_Class=13
Mass test: TS0(xxOOxOxO)TS7 MS_Class=14
Mass test: TS0(xxOOxOxO)TS7 MS_Class=15
Mass test: TS0(xxOOxOxO)TS7 MS_Class=16
Mass test: TS0(xxOOxOxO)TS7 MS_Class=17
Mass test: TS0(xxOOxOxO)TS7 MS_Class=18
Mass test: TS0(xxOOxOxO)TS7 MS_Class=19
Mass test: TS0(xxOOxOxO)TS7 MS_Class=20
Mass test: TS0(xxOOxOxO)TS7 MS_Class=21
Mass test: TS0(xxOOxOxO)TS7 MS_Class=22
Mass test: TS0(xxOOxOxO)TS7 MS_Class=23
Mass test: TS0(xxOOxOxO)TS7 MS_Class=24
Mass test: TS0(xxOOxOxO)TS7 MS_Class=25
Mass test: TS0(xxOOxOxO)TS7 MS_Class=26
Mass test: TS0(xxOOxOxO)TS7 MS_Class=27
Mass test: TS0(xxOOxOxO)TS7 MS_Class=28
Mass test: TS0(xxOOxOxO)TS7 MS_Class=29
Mass test: TS0(xxOOxOxO)TS7 MS_Class=30
Mass test: TS0(xxOOxOxO)TS7 MS_Class=31
Mass test: TS0(xxOOxOxO)TS7 MS_Class=32
Mass test: TS0(xxOOxOxO)TS7 MS_Class=33
Mass test: TS0(xxOOxOxO)TS7 MS_Class=34
Mass test: TS0(xxOOxOxO)TS7 MS_Class=35
Mass test: TS0(xxOOxOxO)TS7 MS_Class=36
Mass test: TS0(xxOOxOxO)TS7 MS_Class=37
Mass test: TS0(xxOOxOxO)TS7 MS_Class=38
Mass test: TS0(xxOOxOxO)TS7 MS_Class=39
Mass test: TS0(xxOOxOxO)TS7 MS_Class=40
Mass test: TS0(xxOOxOxO)TS7 MS_Class=41
Mass test: TS0(xxOOxOxO)TS7 MS_Class=42
Mass test: TS0(xxOOxOxO)TS7 MS_Class=43
Mass test: TS0(xxOOxOxO)TS7 MS_Class=44
Mass test: TS0(xxOOxOxO)TS7 MS_Class=45
Mass test: TS0(xxOOxOOx)TS7 MS_Class=0
Mass test: TS0(xxOOxOOx)TS7 MS_Class=1
Mass test: TS0(xxOOxOOx)TS7 MS_Class=2
Mass test: TS0(xxOOxOOx)TS7 MS_Class=3
Mass test: TS0(xxOOxOOx)TS7 MS_Class=4
Mass test: TS0(xxOOxOOx)TS7 MS_Class=5
Mass test: TS0(xxOOxOOx)TS7 MS_Class=6
Mass test: TS0(xxOOxOOx)TS7 MS_Class=7
Mass test: TS0(xxOOxOOx)TS7 MS_Class=8
Mass test: TS0(xxOOxOOx)TS7 MS_Class=9
Mass test: TS0(xxOOxOOx)TS7 MS_Class=10
Mass test: TS0(xxOOxOOx)TS7 MS_Class=11
Mass test: TS0(xxOOxOOx)TS7 MS_Class=12
Mass test: TS0(xxOOxOOx)TS7 MS_Class=13
Mass test: TS0(xxOOxOOx)TS7 MS_Class=14
Mass test: TS0(xxOOxOOx)TS7 MS_Class=15
Mass test: TS0(xxOOxOOx)TS7 MS_Class=16
Mass test: TS0(xxOOxOOx)TS7 MS_Class=17
Mass test: TS0(xxOOxOOx)TS7 MS_Class=18
Mass test: TS0(xxOOxOOx)TS7 MS_Class=19
Mass test: TS0(xxOOxOOx)TS7 MS_Class=20
Mass test: TS0(xxOOxOOx)TS7 MS_Class=21
Mass test: TS0(xxOOxOOx)TS7 MS_Class=22
Mass test: TS0(xxOOxOOx)TS7 MS_Class=23
Mass test: TS0(xxOOxOOx)TS7 MS_Class=24
Mass test: TS0(xxOOxOOx)TS7 MS_Class=25
Mass test: TS0(xxOOxOOx)TS7 MS_Class=26
Mass test: TS0(xxOOxOOx)TS7 MS_Class=27
Mass test: TS0(xxOOxOOx)TS7 MS_Class=28
Mass test: TS0(xxOOxOOx)TS7 MS_Class=29
Mass test: TS0(xxOOxOOx)TS7 MS_Class=30
Mass test: TS0(xxOOxOOx)TS7 MS_Class=31
Mass test: TS0(xxOOxOOx)TS7 MS_Class=32
Mass test: TS0(xxOOxOOx)TS7 MS_Class=33
Mass test: TS0(xxOOxOOx)TS7 MS_Class=34
Mass test: TS0(xxOOxOOx)TS7 MS_Class=35
Mass test: TS0(xxOOxOOx)TS7 MS_Class=36
Mass test: TS0(xxOOxOOx)TS7 MS_Class=37
Mass test: TS0(xxOOxOOx)TS7 MS_Class=38
Mass test: TS0(xxOOxOOx)TS7 MS_Class=39
Mass test: TS0(xxOOxOOx)TS7 MS_Class=40
Mass test: TS0(xxOOxOOx)TS7 MS_Class=41
Mass test: TS0(xxOOxOOx)TS7 MS_Class=42
Mass test: TS0(xxOOxOOx)TS7 MS_Class=43
Mass test: TS0(xxOOxOOx)TS7 MS_Class=44
Mass test: TS0(xxOOxOOx)TS7 MS_Class=45
Mass test: TS0(xxOOxOOO)TS7 MS_Class=0
Mass test: TS0(xxOOxOOO)TS7 MS_Class=1
Mass test: TS0(xxOOxOOO)TS7 MS_Class=2
Mass test: TS0(xxOOxOOO)TS7 MS_Class=3
Mass test: TS0(xxOOxOOO)TS7 MS_Class=4
Mass test: TS0(xxOOxOOO)TS7 MS_Class=5
Mass test: TS0(xxOOxOOO)TS7 MS_Class=6
Mass test: TS0(xxOOxOOO)TS7 MS_Class=7
Mass test: TS0(xxOOxOOO)TS7 MS_Class=8
Mass test: TS0(xxOOxOOO)TS7 MS_Class=9
Mass test: TS0(xxOOxOOO)TS7 MS_Class=10
Mass test: TS0(xxOOxOOO)TS7 MS_Class=11
Mass test: TS0(xxOOxOOO)TS7 MS_Class=12
Mass test: TS0(xxOOxOOO)TS7 MS_Class=13
Mass test: TS0(xxOOxOOO)TS7 MS_Class=14
Mass test: TS0(xxOOxOOO)TS7 MS_Class=15
Mass test: TS0(xxOOxOOO)TS7 MS_Class=16
Mass test: TS0(xxOOxOOO)TS7 MS_Class=17
Mass test: TS0(xxOOxOOO)TS7 MS_Class=18
Mass test: TS0(xxOOxOOO)TS7 MS_Class=19
Mass test: TS0(xxOOxOOO)TS7 MS_Class=20
Mass test: TS0(xxOOxOOO)TS7 MS_Class=21
Mass test: TS0(xxOOxOOO)TS7 MS_Class=22
Mass test: TS0(xxOOxOOO)TS7 MS_Class=23
Mass test: TS0(xxOOxOOO)TS7 MS_Class=24
Mass test: TS0(xxOOxOOO)TS7 MS_Class=25
Mass test: TS0(xxOOxOOO)TS7 MS_Class=26
Mass test: TS0(xxOOxOOO)TS7 MS_Class=27
Mass test: TS0(xxOOxOOO)TS7 MS_Class=28
Mass test: TS0(xxOOxOOO)TS7 MS_Class=29
Mass test: TS0(xxOOxOOO)TS7 MS_Class=30
Mass test: TS0(xxOOxOOO)TS7 MS_Class=31
Mass test: TS0(xxOOxOOO)TS7 MS_Class=32
Mass test: TS0(xxOOxOOO)TS7 MS_Class=33
Mass test: TS0(xxOOxOOO)TS7 MS_Class=34
Mass test: TS0(xxOOxOOO)TS7 MS_Class=35
Mass test: TS0(xxOOxOOO)TS7 MS_Class=36
Mass test: TS0(xxOOxOOO)TS7 MS_Class=37
Mass test: TS0(xxOOxOOO)TS7 MS_Class=38
Mass test: TS0(xxOOxOOO)TS7 MS_Class=39
Mass test: TS0(xxOOxOOO)TS7 MS_Class=40
Mass test: TS0(xxOOxOOO)TS7 MS_Class=41
Mass test: TS0(xxOOxOOO)TS7 MS_Class=42
Mass test: TS0(xxOOxOOO)TS7 MS_Class=43
Mass test: TS0(xxOOxOOO)TS7 MS_Class=44
Mass test: TS0(xxOOxOOO)TS7 MS_Class=45
Mass test: TS0(xxOOOxxx)TS7 MS_Class=0
Mass test: TS0(xxOOOxxx)TS7 MS_Class=1
Mass test: TS0(xxOOOxxx)TS7 MS_Class=2
Mass test: TS0(xxOOOxxx)TS7 MS_Class=3
Mass test: TS0(xxOOOxxx)TS7 MS_Class=4
Mass test: TS0(xxOOOxxx)TS7 MS_Class=5
Mass test: TS0(xxOOOxxx)TS7 MS_Class=6
Mass test: TS0(xxOOOxxx)TS7 MS_Class=7
Mass test: TS0(xxOOOxxx)TS7 MS_Class=8
Mass test: TS0(xxOOOxxx)TS7 MS_Class=9
Mass test: TS0(xxOOOxxx)TS7 MS_Class=10
Mass test: TS0(xxOOOxxx)TS7 MS_Class=11
Mass test: TS0(xxOOOxxx)TS7 MS_Class=12
Mass test: TS0(xxOOOxxx)TS7 MS_Class=13
Mass test: TS0(xxOOOxxx)TS7 MS_Class=14
Mass test: TS0(xxOOOxxx)TS7 MS_Class=15
Mass test: TS0(xxOOOxxx)TS7 MS_Class=16
Mass test: TS0(xxOOOxxx)TS7 MS_Class=17
Mass test: TS0(xxOOOxxx)TS7 MS_Class=18
Mass test: TS0(xxOOOxxx)TS7 MS_Class=19
Mass test: TS0(xxOOOxxx)TS7 MS_Class=20
Mass test: TS0(xxOOOxxx)TS7 MS_Class=21
Mass test: TS0(xxOOOxxx)TS7 MS_Class=22
Mass test: TS0(xxOOOxxx)TS7 MS_Class=23
Mass test: TS0(xxOOOxxx)TS7 MS_Class=24
Mass test: TS0(xxOOOxxx)TS7 MS_Class=25
Mass test: TS0(xxOOOxxx)TS7 MS_Class=26
Mass test: TS0(xxOOOxxx)TS7 MS_Class=27
Mass test: TS0(xxOOOxxx)TS7 MS_Class=28
Mass test: TS0(xxOOOxxx)TS7 MS_Class=29
Mass test: TS0(xxOOOxxx)TS7 MS_Class=30
Mass test: TS0(xxOOOxxx)TS7 MS_Class=31
Mass test: TS0(xxOOOxxx)TS7 MS_Class=32
Mass test: TS0(xxOOOxxx)TS7 MS_Class=33
Mass test: TS0(xxOOOxxx)TS7 MS_Class=34
Mass test: TS0(xxOOOxxx)TS7 MS_Class=35
Mass test: TS0(xxOOOxxx)TS7 MS_Class=36
Mass test: TS0(xxOOOxxx)TS7 MS_Class=37
Mass test: TS0(xxOOOxxx)TS7 MS_Class=38
Mass test: TS0(xxOOOxxx)TS7 MS_Class=39
Mass test: TS0(xxOOOxxx)TS7 MS_Class=40
Mass test: TS0(xxOOOxxx)TS7 MS_Class=41
Mass test: TS0(xxOOOxxx)TS7 MS_Class=42
Mass test: TS0(xxOOOxxx)TS7 MS_Class=43
Mass test: TS0(xxOOOxxx)TS7 MS_Class=44
Mass test: TS0(xxOOOxxx)TS7 MS_Class=45
Mass test: TS0(xxOOOxxO)TS7 MS_Class=0
Mass test: TS0(xxOOOxxO)TS7 MS_Class=1
Mass test: TS0(xxOOOxxO)TS7 MS_Class=2
Mass test: TS0(xxOOOxxO)TS7 MS_Class=3
Mass test: TS0(xxOOOxxO)TS7 MS_Class=4
Mass test: TS0(xxOOOxxO)TS7 MS_Class=5
Mass test: TS0(xxOOOxxO)TS7 MS_Class=6
Mass test: TS0(xxOOOxxO)TS7 MS_Class=7
Mass test: TS0(xxOOOxxO)TS7 MS_Class=8
Mass test: TS0(xxOOOxxO)TS7 MS_Class=9
Mass test: TS0(xxOOOxxO)TS7 MS_Class=10
Mass test: TS0(xxOOOxxO)TS7 MS_Class=11
Mass test: TS0(xxOOOxxO)TS7 MS_Class=12
Mass test: TS0(xxOOOxxO)TS7 MS_Class=13
Mass test: TS0(xxOOOxxO)TS7 MS_Class=14
Mass test: TS0(xxOOOxxO)TS7 MS_Class=15
Mass test: TS0(xxOOOxxO)TS7 MS_Class=16
Mass test: TS0(xxOOOxxO)TS7 MS_Class=17
Mass test: TS0(xxOOOxxO)TS7 MS_Class=18
Mass test: TS0(xxOOOxxO)TS7 MS_Class=19
Mass test: TS0(xxOOOxxO)TS7 MS_Class=20
Mass test: TS0(xxOOOxxO)TS7 MS_Class=21
Mass test: TS0(xxOOOxxO)TS7 MS_Class=22
Mass test: TS0(xxOOOxxO)TS7 MS_Class=23
Mass test: TS0(xxOOOxxO)TS7 MS_Class=24
Mass test: TS0(xxOOOxxO)TS7 MS_Class=25
Mass test: TS0(xxOOOxxO)TS7 MS_Class=26
Mass test: TS0(xxOOOxxO)TS7 MS_Class=27
Mass test: TS0(xxOOOxxO)TS7 MS_Class=28
Mass test: TS0(xxOOOxxO)TS7 MS_Class=29
Mass test: TS0(xxOOOxxO)TS7 MS_Class=30
Mass test: TS0(xxOOOxxO)TS7 MS_Class=31
Mass test: TS0(xxOOOxxO)TS7 MS_Class=32
Mass test: TS0(xxOOOxxO)TS7 MS_Class=33
Mass test: TS0(xxOOOxxO)TS7 MS_Class=34
Mass test: TS0(xxOOOxxO)TS7 MS_Class=35
Mass test: TS0(xxOOOxxO)TS7 MS_Class=36
Mass test: TS0(xxOOOxxO)TS7 MS_Class=37
Mass test: TS0(xxOOOxxO)TS7 MS_Class=38
Mass test: TS0(xxOOOxxO)TS7 MS_Class=39
Mass test: TS0(xxOOOxxO)TS7 MS_Class=40
Mass test: TS0(xxOOOxxO)TS7 MS_Class=41
Mass test: TS0(xxOOOxxO)TS7 MS_Class=42
Mass test: TS0(xxOOOxxO)TS7 MS_Class=43
Mass test: TS0(xxOOOxxO)TS7 MS_Class=44
Mass test: TS0(xxOOOxxO)TS7 MS_Class=45
Mass test: TS0(xxOOOxOx)TS7 MS_Class=0
Mass test: TS0(xxOOOxOx)TS7 MS_Class=1
Mass test: TS0(xxOOOxOx)TS7 MS_Class=2
Mass test: TS0(xxOOOxOx)TS7 MS_Class=3
Mass test: TS0(xxOOOxOx)TS7 MS_Class=4
Mass test: TS0(xxOOOxOx)TS7 MS_Class=5
Mass test: TS0(xxOOOxOx)TS7 MS_Class=6
Mass test: TS0(xxOOOxOx)TS7 MS_Class=7
Mass test: TS0(xxOOOxOx)TS7 MS_Class=8
Mass test: TS0(xxOOOxOx)TS7 MS_Class=9
Mass test: TS0(xxOOOxOx)TS7 MS_Class=10
Mass test: TS0(xxOOOxOx)TS7 MS_Class=11
Mass test: TS0(xxOOOxOx)TS7 MS_Class=12
Mass test: TS0(xxOOOxOx)TS7 MS_Class=13
Mass test: TS0(xxOOOxOx)TS7 MS_Class=14
Mass test: TS0(xxOOOxOx)TS7 MS_Class=15
Mass test: TS0(xxOOOxOx)TS7 MS_Class=16
Mass test: TS0(xxOOOxOx)TS7 MS_Class=17
Mass test: TS0(xxOOOxOx)TS7 MS_Class=18
Mass test: TS0(xxOOOxOx)TS7 MS_Class=19
Mass test: TS0(xxOOOxOx)TS7 MS_Class=20
Mass test: TS0(xxOOOxOx)TS7 MS_Class=21
Mass test: TS0(xxOOOxOx)TS7 MS_Class=22
Mass test: TS0(xxOOOxOx)TS7 MS_Class=23
Mass test: TS0(xxOOOxOx)TS7 MS_Class=24
Mass test: TS0(xxOOOxOx)TS7 MS_Class=25
Mass test: TS0(xxOOOxOx)TS7 MS_Class=26
Mass test: TS0(xxOOOxOx)TS7 MS_Class=27
Mass test: TS0(xxOOOxOx)TS7 MS_Class=28
Mass test: TS0(xxOOOxOx)TS7 MS_Class=29
Mass test: TS0(xxOOOxOx)TS7 MS_Class=30
Mass test: TS0(xxOOOxOx)TS7 MS_Class=31
Mass test: TS0(xxOOOxOx)TS7 MS_Class=32
Mass test: TS0(xxOOOxOx)TS7 MS_Class=33
Mass test: TS0(xxOOOxOx)TS7 MS_Class=34
Mass test: TS0(xxOOOxOx)TS7 MS_Class=35
Mass test: TS0(xxOOOxOx)TS7 MS_Class=36
Mass test: TS0(xxOOOxOx)TS7 MS_Class=37
Mass test: TS0(xxOOOxOx)TS7 MS_Class=38
Mass test: TS0(xxOOOxOx)TS7 MS_Class=39
Mass test: TS0(xxOOOxOx)TS7 MS_Class=40
Mass test: TS0(xxOOOxOx)TS7 MS_Class=41
Mass test: TS0(xxOOOxOx)TS7 MS_Class=42
Mass test: TS0(xxOOOxOx)TS7 MS_Class=43
Mass test: TS0(xxOOOxOx)TS7 MS_Class=44
Mass test: TS0(xxOOOxOx)TS7 MS_Class=45
Mass test: TS0(xxOOOxOO)TS7 MS_Class=0
Mass test: TS0(xxOOOxOO)TS7 MS_Class=1
Mass test: TS0(xxOOOxOO)TS7 MS_Class=2
Mass test: TS0(xxOOOxOO)TS7 MS_Class=3
Mass test: TS0(xxOOOxOO)TS7 MS_Class=4
Mass test: TS0(xxOOOxOO)TS7 MS_Class=5
Mass test: TS0(xxOOOxOO)TS7 MS_Class=6
Mass test: TS0(xxOOOxOO)TS7 MS_Class=7
Mass test: TS0(xxOOOxOO)TS7 MS_Class=8
Mass test: TS0(xxOOOxOO)TS7 MS_Class=9
Mass test: TS0(xxOOOxOO)TS7 MS_Class=10
Mass test: TS0(xxOOOxOO)TS7 MS_Class=11
Mass test: TS0(xxOOOxOO)TS7 MS_Class=12
Mass test: TS0(xxOOOxOO)TS7 MS_Class=13
Mass test: TS0(xxOOOxOO)TS7 MS_Class=14
Mass test: TS0(xxOOOxOO)TS7 MS_Class=15
Mass test: TS0(xxOOOxOO)TS7 MS_Class=16
Mass test: TS0(xxOOOxOO)TS7 MS_Class=17
Mass test: TS0(xxOOOxOO)TS7 MS_Class=18
Mass test: TS0(xxOOOxOO)TS7 MS_Class=19
Mass test: TS0(xxOOOxOO)TS7 MS_Class=20
Mass test: TS0(xxOOOxOO)TS7 MS_Class=21
Mass test: TS0(xxOOOxOO)TS7 MS_Class=22
Mass test: TS0(xxOOOxOO)TS7 MS_Class=23
Mass test: TS0(xxOOOxOO)TS7 MS_Class=24
Mass test: TS0(xxOOOxOO)TS7 MS_Class=25
Mass test: TS0(xxOOOxOO)TS7 MS_Class=26
Mass test: TS0(xxOOOxOO)TS7 MS_Class=27
Mass test: TS0(xxOOOxOO)TS7 MS_Class=28
Mass test: TS0(xxOOOxOO)TS7 MS_Class=29
Mass test: TS0(xxOOOxOO)TS7 MS_Class=30
Mass test: TS0(xxOOOxOO)TS7 MS_Class=31
Mass test: TS0(xxOOOxOO)TS7 MS_Class=32
Mass test: TS0(xxOOOxOO)TS7 MS_Class=33
Mass test: TS0(xxOOOxOO)TS7 MS_Class=34
Mass test: TS0(xxOOOxOO)TS7 MS_Class=35
Mass test: TS0(xxOOOxOO)TS7 MS_Class=36
Mass test: TS0(xxOOOxOO)TS7 MS_Class=37
Mass test: TS0(xxOOOxOO)TS7 MS_Class=38
Mass test: TS0(xxOOOxOO)TS7 MS_Class=39
Mass test: TS0(xxOOOxOO)TS7 MS_Class=40
Mass test: TS0(xxOOOxOO)TS7 MS_Class=41
Mass test: TS0(xxOOOxOO)TS7 MS_Class=42
Mass test: TS0(xxOOOxOO)TS7 MS_Class=43
Mass test: TS0(xxOOOxOO)TS7 MS_Class=44
Mass test: TS0(xxOOOxOO)TS7 MS_Class=45
Mass test: TS0(xxOOOOxx)TS7 MS_Class=0
Mass test: TS0(xxOOOOxx)TS7 MS_Class=1
Mass test: TS0(xxOOOOxx)TS7 MS_Class=2
Mass test: TS0(xxOOOOxx)TS7 MS_Class=3
Mass test: TS0(xxOOOOxx)TS7 MS_Class=4
Mass test: TS0(xxOOOOxx)TS7 MS_Class=5
Mass test: TS0(xxOOOOxx)TS7 MS_Class=6
Mass test: TS0(xxOOOOxx)TS7 MS_Class=7
Mass test: TS0(xxOOOOxx)TS7 MS_Class=8
Mass test: TS0(xxOOOOxx)TS7 MS_Class=9
Mass test: TS0(xxOOOOxx)TS7 MS_Class=10
Mass test: TS0(xxOOOOxx)TS7 MS_Class=11
Mass test: TS0(xxOOOOxx)TS7 MS_Class=12
Mass test: TS0(xxOOOOxx)TS7 MS_Class=13
Mass test: TS0(xxOOOOxx)TS7 MS_Class=14
Mass test: TS0(xxOOOOxx)TS7 MS_Class=15
Mass test: TS0(xxOOOOxx)TS7 MS_Class=16
Mass test: TS0(xxOOOOxx)TS7 MS_Class=17
Mass test: TS0(xxOOOOxx)TS7 MS_Class=18
Mass test: TS0(xxOOOOxx)TS7 MS_Class=19
Mass test: TS0(xxOOOOxx)TS7 MS_Class=20
Mass test: TS0(xxOOOOxx)TS7 MS_Class=21
Mass test: TS0(xxOOOOxx)TS7 MS_Class=22
Mass test: TS0(xxOOOOxx)TS7 MS_Class=23
Mass test: TS0(xxOOOOxx)TS7 MS_Class=24
Mass test: TS0(xxOOOOxx)TS7 MS_Class=25
Mass test: TS0(xxOOOOxx)TS7 MS_Class=26
Mass test: TS0(xxOOOOxx)TS7 MS_Class=27
Mass test: TS0(xxOOOOxx)TS7 MS_Class=28
Mass test: TS0(xxOOOOxx)TS7 MS_Class=29
Mass test: TS0(xxOOOOxx)TS7 MS_Class=30
Mass test: TS0(xxOOOOxx)TS7 MS_Class=31
Mass test: TS0(xxOOOOxx)TS7 MS_Class=32
Mass test: TS0(xxOOOOxx)TS7 MS_Class=33
Mass test: TS0(xxOOOOxx)TS7 MS_Class=34
Mass test: TS0(xxOOOOxx)TS7 MS_Class=35
Mass test: TS0(xxOOOOxx)TS7 MS_Class=36
Mass test: TS0(xxOOOOxx)TS7 MS_Class=37
Mass test: TS0(xxOOOOxx)TS7 MS_Class=38
Mass test: TS0(xxOOOOxx)TS7 MS_Class=39
Mass test: TS0(xxOOOOxx)TS7 MS_Class=40
Mass test: TS0(xxOOOOxx)TS7 MS_Class=41
Mass test: TS0(xxOOOOxx)TS7 MS_Class=42
Mass test: TS0(xxOOOOxx)TS7 MS_Class=43
Mass test: TS0(xxOOOOxx)TS7 MS_Class=44
Mass test: TS0(xxOOOOxx)TS7 MS_Class=45
Mass test: TS0(xxOOOOxO)TS7 MS_Class=0
Mass test: TS0(xxOOOOxO)TS7 MS_Class=1
Mass test: TS0(xxOOOOxO)TS7 MS_Class=2
Mass test: TS0(xxOOOOxO)TS7 MS_Class=3
Mass test: TS0(xxOOOOxO)TS7 MS_Class=4
Mass test: TS0(xxOOOOxO)TS7 MS_Class=5
Mass test: TS0(xxOOOOxO)TS7 MS_Class=6
Mass test: TS0(xxOOOOxO)TS7 MS_Class=7
Mass test: TS0(xxOOOOxO)TS7 MS_Class=8
Mass test: TS0(xxOOOOxO)TS7 MS_Class=9
Mass test: TS0(xxOOOOxO)TS7 MS_Class=10
Mass test: TS0(xxOOOOxO)TS7 MS_Class=11
Mass test: TS0(xxOOOOxO)TS7 MS_Class=12
Mass test: TS0(xxOOOOxO)TS7 MS_Class=13
Mass test: TS0(xxOOOOxO)TS7 MS_Class=14
Mass test: TS0(xxOOOOxO)TS7 MS_Class=15
Mass test: TS0(xxOOOOxO)TS7 MS_Class=16
Mass test: TS0(xxOOOOxO)TS7 MS_Class=17
Mass test: TS0(xxOOOOxO)TS7 MS_Class=18
Mass test: TS0(xxOOOOxO)TS7 MS_Class=19
Mass test: TS0(xxOOOOxO)TS7 MS_Class=20
Mass test: TS0(xxOOOOxO)TS7 MS_Class=21
Mass test: TS0(xxOOOOxO)TS7 MS_Class=22
Mass test: TS0(xxOOOOxO)TS7 MS_Class=23
Mass test: TS0(xxOOOOxO)TS7 MS_Class=24
Mass test: TS0(xxOOOOxO)TS7 MS_Class=25
Mass test: TS0(xxOOOOxO)TS7 MS_Class=26
Mass test: TS0(xxOOOOxO)TS7 MS_Class=27
Mass test: TS0(xxOOOOxO)TS7 MS_Class=28
Mass test: TS0(xxOOOOxO)TS7 MS_Class=29
Mass test: TS0(xxOOOOxO)TS7 MS_Class=30
Mass test: TS0(xxOOOOxO)TS7 MS_Class=31
Mass test: TS0(xxOOOOxO)TS7 MS_Class=32
Mass test: TS0(xxOOOOxO)TS7 MS_Class=33
Mass test: TS0(xxOOOOxO)TS7 MS_Class=34
Mass test: TS0(xxOOOOxO)TS7 MS_Class=35
Mass test: TS0(xxOOOOxO)TS7 MS_Class=36
Mass test: TS0(xxOOOOxO)TS7 MS_Class=37
Mass test: TS0(xxOOOOxO)TS7 MS_Class=38
Mass test: TS0(xxOOOOxO)TS7 MS_Class=39
Mass test: TS0(xxOOOOxO)TS7 MS_Class=40
Mass test: TS0(xxOOOOxO)TS7 MS_Class=41
Mass test: TS0(xxOOOOxO)TS7 MS_Class=42
Mass test: TS0(xxOOOOxO)TS7 MS_Class=43
Mass test: TS0(xxOOOOxO)TS7 MS_Class=44
Mass test: TS0(xxOOOOxO)TS7 MS_Class=45
Mass test: TS0(xxOOOOOx)TS7 MS_Class=0
Mass test: TS0(xxOOOOOx)TS7 MS_Class=1
Mass test: TS0(xxOOOOOx)TS7 MS_Class=2
Mass test: TS0(xxOOOOOx)TS7 MS_Class=3
Mass test: TS0(xxOOOOOx)TS7 MS_Class=4
Mass test: TS0(xxOOOOOx)TS7 MS_Class=5
Mass test: TS0(xxOOOOOx)TS7 MS_Class=6
Mass test: TS0(xxOOOOOx)TS7 MS_Class=7
Mass test: TS0(xxOOOOOx)TS7 MS_Class=8
Mass test: TS0(xxOOOOOx)TS7 MS_Class=9
Mass test: TS0(xxOOOOOx)TS7 MS_Class=10
Mass test: TS0(xxOOOOOx)TS7 MS_Class=11
Mass test: TS0(xxOOOOOx)TS7 MS_Class=12
Mass test: TS0(xxOOOOOx)TS7 MS_Class=13
Mass test: TS0(xxOOOOOx)TS7 MS_Class=14
Mass test: TS0(xxOOOOOx)TS7 MS_Class=15
Mass test: TS0(xxOOOOOx)TS7 MS_Class=16
Mass test: TS0(xxOOOOOx)TS7 MS_Class=17
Mass test: TS0(xxOOOOOx)TS7 MS_Class=18
Mass test: TS0(xxOOOOOx)TS7 MS_Class=19
Mass test: TS0(xxOOOOOx)TS7 MS_Class=20
Mass test: TS0(xxOOOOOx)TS7 MS_Class=21
Mass test: TS0(xxOOOOOx)TS7 MS_Class=22
Mass test: TS0(xxOOOOOx)TS7 MS_Class=23
Mass test: TS0(xxOOOOOx)TS7 MS_Class=24
Mass test: TS0(xxOOOOOx)TS7 MS_Class=25
Mass test: TS0(xxOOOOOx)TS7 MS_Class=26
Mass test: TS0(xxOOOOOx)TS7 MS_Class=27
Mass test: TS0(xxOOOOOx)TS7 MS_Class=28
Mass test: TS0(xxOOOOOx)TS7 MS_Class=29
Mass test: TS0(xxOOOOOx)TS7 MS_Class=30
Mass test: TS0(xxOOOOOx)TS7 MS_Class=31
Mass test: TS0(xxOOOOOx)TS7 MS_Class=32
Mass test: TS0(xxOOOOOx)TS7 MS_Class=33
Mass test: TS0(xxOOOOOx)TS7 MS_Class=34
Mass test: TS0(xxOOOOOx)TS7 MS_Class=35
Mass test: TS0(xxOOOOOx)TS7 MS_Class=36
Mass test: TS0(xxOOOOOx)TS7 MS_Class=37
Mass test: TS0(xxOOOOOx)TS7 MS_Class=38
Mass test: TS0(xxOOOOOx)TS7 MS_Class=39
Mass test: TS0(xxOOOOOx)TS7 MS_Class=40
Mass test: TS0(xxOOOOOx)TS7 MS_Class=41
Mass test: TS0(xxOOOOOx)TS7 MS_Class=42
Mass test: TS0(xxOOOOOx)TS7 MS_Class=43
Mass test: TS0(xxOOOOOx)TS7 MS_Class=44
Mass test: TS0(xxOOOOOx)TS7 MS_Class=45
Mass test: TS0(xxOOOOOO)TS7 MS_Class=0
Mass test: TS0(xxOOOOOO)TS7 MS_Class=1
Mass test: TS0(xxOOOOOO)TS7 MS_Class=2
Mass test: TS0(xxOOOOOO)TS7 MS_Class=3
Mass test: TS0(xxOOOOOO)TS7 MS_Class=4
Mass test: TS0(xxOOOOOO)TS7 MS_Class=5
Mass test: TS0(xxOOOOOO)TS7 MS_Class=6
Mass test: TS0(xxOOOOOO)TS7 MS_Class=7
Mass test: TS0(xxOOOOOO)TS7 MS_Class=8
Mass test: TS0(xxOOOOOO)TS7 MS_Class=9
Mass test: TS0(xxOOOOOO)TS7 MS_Class=10
Mass test: TS0(xxOOOOOO)TS7 MS_Class=11
Mass test: TS0(xxOOOOOO)TS7 MS_Class=12
Mass test: TS0(xxOOOOOO)TS7 MS_Class=13
Mass test: TS0(xxOOOOOO)TS7 MS_Class=14
Mass test: TS0(xxOOOOOO)TS7 MS_Class=15
Mass test: TS0(xxOOOOOO)TS7 MS_Class=16
Mass test: TS0(xxOOOOOO)TS7 MS_Class=17
Mass test: TS0(xxOOOOOO)TS7 MS_Class=18
Mass test: TS0(xxOOOOOO)TS7 MS_Class=19
Mass test: TS0(xxOOOOOO)TS7 MS_Class=20
Mass test: TS0(xxOOOOOO)TS7 MS_Class=21
Mass test: TS0(xxOOOOOO)TS7 MS_Class=22
Mass test: TS0(xxOOOOOO)TS7 MS_Class=23
Mass test: TS0(xxOOOOOO)TS7 MS_Class=24
Mass test: TS0(xxOOOOOO)TS7 MS_Class=25
Mass test: TS0(xxOOOOOO)TS7 MS_Class=26
Mass test: TS0(xxOOOOOO)TS7 MS_Class=27
Mass test: TS0(xxOOOOOO)TS7 MS_Class=28
Mass test: TS0(xxOOOOOO)TS7 MS_Class=29
Mass test: TS0(xxOOOOOO)TS7 MS_Class=30
Mass test: TS0(xxOOOOOO)TS7 MS_Class=31
Mass test: TS0(xxOOOOOO)TS7 MS_Class=32
Mass test: TS0(xxOOOOOO)TS7 MS_Class=33
Mass test: TS0(xxOOOOOO)TS7 MS_Class=34
Mass test: TS0(xxOOOOOO)TS7 MS_Class=35
Mass test: TS0(xxOOOOOO)TS7 MS_Class=36
Mass test: TS0(xxOOOOOO)TS7 MS_Class=37
Mass test: TS0(xxOOOOOO)TS7 MS_Class=38
Mass test: TS0(xxOOOOOO)TS7 MS_Class=39
Mass test: TS0(xxOOOOOO)TS7 MS_Class=40
Mass test: TS0(xxOOOOOO)TS7 MS_Class=41
Mass test: TS0(xxOOOOOO)TS7 MS_Class=42
Mass test: TS0(xxOOOOOO)TS7 MS_Class=43
Mass test: TS0(xxOOOOOO)TS7 MS_Class=44
Mass test: TS0(xxOOOOOO)TS7 MS_Class=45
Mass test: TS0(xOxxxxxx)TS7 MS_Class=0
Mass test: TS0(xOxxxxxx)TS7 MS_Class=1
Mass test: TS0(xOxxxxxx)TS7 MS_Class=2
Mass test: TS0(xOxxxxxx)TS7 MS_Class=3
Mass test: TS0(xOxxxxxx)TS7 MS_Class=4
Mass test: TS0(xOxxxxxx)TS7 MS_Class=5
Mass test: TS0(xOxxxxxx)TS7 MS_Class=6
Mass test: TS0(xOxxxxxx)TS7 MS_Class=7
Mass test: TS0(xOxxxxxx)TS7 MS_Class=8
Mass test: TS0(xOxxxxxx)TS7 MS_Class=9
Mass test: TS0(xOxxxxxx)TS7 MS_Class=10
Mass test: TS0(xOxxxxxx)TS7 MS_Class=11
Mass test: TS0(xOxxxxxx)TS7 MS_Class=12
Mass test: TS0(xOxxxxxx)TS7 MS_Class=13
Mass test: TS0(xOxxxxxx)TS7 MS_Class=14
Mass test: TS0(xOxxxxxx)TS7 MS_Class=15
Mass test: TS0(xOxxxxxx)TS7 MS_Class=16
Mass test: TS0(xOxxxxxx)TS7 MS_Class=17
Mass test: TS0(xOxxxxxx)TS7 MS_Class=18
Mass test: TS0(xOxxxxxx)TS7 MS_Class=19
Mass test: TS0(xOxxxxxx)TS7 MS_Class=20
Mass test: TS0(xOxxxxxx)TS7 MS_Class=21
Mass test: TS0(xOxxxxxx)TS7 MS_Class=22
Mass test: TS0(xOxxxxxx)TS7 MS_Class=23
Mass test: TS0(xOxxxxxx)TS7 MS_Class=24
Mass test: TS0(xOxxxxxx)TS7 MS_Class=25
Mass test: TS0(xOxxxxxx)TS7 MS_Class=26
Mass test: TS0(xOxxxxxx)TS7 MS_Class=27
Mass test: TS0(xOxxxxxx)TS7 MS_Class=28
Mass test: TS0(xOxxxxxx)TS7 MS_Class=29
Mass test: TS0(xOxxxxxx)TS7 MS_Class=30
Mass test: TS0(xOxxxxxx)TS7 MS_Class=31
Mass test: TS0(xOxxxxxx)TS7 MS_Class=32
Mass test: TS0(xOxxxxxx)TS7 MS_Class=33
Mass test: TS0(xOxxxxxx)TS7 MS_Class=34
Mass test: TS0(xOxxxxxx)TS7 MS_Class=35
Mass test: TS0(xOxxxxxx)TS7 MS_Class=36
Mass test: TS0(xOxxxxxx)TS7 MS_Class=37
Mass test: TS0(xOxxxxxx)TS7 MS_Class=38
Mass test: TS0(xOxxxxxx)TS7 MS_Class=39
Mass test: TS0(xOxxxxxx)TS7 MS_Class=40
Mass test: TS0(xOxxxxxx)TS7 MS_Class=41
Mass test: TS0(xOxxxxxx)TS7 MS_Class=42
Mass test: TS0(xOxxxxxx)TS7 MS_Class=43
Mass test: TS0(xOxxxxxx)TS7 MS_Class=44
Mass test: TS0(xOxxxxxx)TS7 MS_Class=45
Mass test: TS0(xOxxxxxO)TS7 MS_Class=0
Mass test: TS0(xOxxxxxO)TS7 MS_Class=1
Mass test: TS0(xOxxxxxO)TS7 MS_Class=2
Mass test: TS0(xOxxxxxO)TS7 MS_Class=3
Mass test: TS0(xOxxxxxO)TS7 MS_Class=4
Mass test: TS0(xOxxxxxO)TS7 MS_Class=5
Mass test: TS0(xOxxxxxO)TS7 MS_Class=6
Mass test: TS0(xOxxxxxO)TS7 MS_Class=7
Mass test: TS0(xOxxxxxO)TS7 MS_Class=8
Mass test: TS0(xOxxxxxO)TS7 MS_Class=9
Mass test: TS0(xOxxxxxO)TS7 MS_Class=10
Mass test: TS0(xOxxxxxO)TS7 MS_Class=11
Mass test: TS0(xOxxxxxO)TS7 MS_Class=12
Mass test: TS0(xOxxxxxO)TS7 MS_Class=13
Mass test: TS0(xOxxxxxO)TS7 MS_Class=14
Mass test: TS0(xOxxxxxO)TS7 MS_Class=15
Mass test: TS0(xOxxxxxO)TS7 MS_Class=16
Mass test: TS0(xOxxxxxO)TS7 MS_Class=17
Mass test: TS0(xOxxxxxO)TS7 MS_Class=18
Mass test: TS0(xOxxxxxO)TS7 MS_Class=19
Mass test: TS0(xOxxxxxO)TS7 MS_Class=20
Mass test: TS0(xOxxxxxO)TS7 MS_Class=21
Mass test: TS0(xOxxxxxO)TS7 MS_Class=22
Mass test: TS0(xOxxxxxO)TS7 MS_Class=23
Mass test: TS0(xOxxxxxO)TS7 MS_Class=24
Mass test: TS0(xOxxxxxO)TS7 MS_Class=25
Mass test: TS0(xOxxxxxO)TS7 MS_Class=26
Mass test: TS0(xOxxxxxO)TS7 MS_Class=27
Mass test: TS0(xOxxxxxO)TS7 MS_Class=28
Mass test: TS0(xOxxxxxO)TS7 MS_Class=29
Mass test: TS0(xOxxxxxO)TS7 MS_Class=30
Mass test: TS0(xOxxxxxO)TS7 MS_Class=31
Mass test: TS0(xOxxxxxO)TS7 MS_Class=32
Mass test: TS0(xOxxxxxO)TS7 MS_Class=33
Mass test: TS0(xOxxxxxO)TS7 MS_Class=34
Mass test: TS0(xOxxxxxO)TS7 MS_Class=35
Mass test: TS0(xOxxxxxO)TS7 MS_Class=36
Mass test: TS0(xOxxxxxO)TS7 MS_Class=37
Mass test: TS0(xOxxxxxO)TS7 MS_Class=38
Mass test: TS0(xOxxxxxO)TS7 MS_Class=39
Mass test: TS0(xOxxxxxO)TS7 MS_Class=40
Mass test: TS0(xOxxxxxO)TS7 MS_Class=41
Mass test: TS0(xOxxxxxO)TS7 MS_Class=42
Mass test: TS0(xOxxxxxO)TS7 MS_Class=43
Mass test: TS0(xOxxxxxO)TS7 MS_Class=44
Mass test: TS0(xOxxxxxO)TS7 MS_Class=45
Mass test: TS0(xOxxxxOx)TS7 MS_Class=0
Mass test: TS0(xOxxxxOx)TS7 MS_Class=1
Mass test: TS0(xOxxxxOx)TS7 MS_Class=2
Mass test: TS0(xOxxxxOx)TS7 MS_Class=3
Mass test: TS0(xOxxxxOx)TS7 MS_Class=4
Mass test: TS0(xOxxxxOx)TS7 MS_Class=5
Mass test: TS0(xOxxxxOx)TS7 MS_Class=6
Mass test: TS0(xOxxxxOx)TS7 MS_Class=7
Mass test: TS0(xOxxxxOx)TS7 MS_Class=8
Mass test: TS0(xOxxxxOx)TS7 MS_Class=9
Mass test: TS0(xOxxxxOx)TS7 MS_Class=10
Mass test: TS0(xOxxxxOx)TS7 MS_Class=11
Mass test: TS0(xOxxxxOx)TS7 MS_Class=12
Mass test: TS0(xOxxxxOx)TS7 MS_Class=13
Mass test: TS0(xOxxxxOx)TS7 MS_Class=14
Mass test: TS0(xOxxxxOx)TS7 MS_Class=15
Mass test: TS0(xOxxxxOx)TS7 MS_Class=16
Mass test: TS0(xOxxxxOx)TS7 MS_Class=17
Mass test: TS0(xOxxxxOx)TS7 MS_Class=18
Mass test: TS0(xOxxxxOx)TS7 MS_Class=19
Mass test: TS0(xOxxxxOx)TS7 MS_Class=20
Mass test: TS0(xOxxxxOx)TS7 MS_Class=21
Mass test: TS0(xOxxxxOx)TS7 MS_Class=22
Mass test: TS0(xOxxxxOx)TS7 MS_Class=23
Mass test: TS0(xOxxxxOx)TS7 MS_Class=24
Mass test: TS0(xOxxxxOx)TS7 MS_Class=25
Mass test: TS0(xOxxxxOx)TS7 MS_Class=26
Mass test: TS0(xOxxxxOx)TS7 MS_Class=27
Mass test: TS0(xOxxxxOx)TS7 MS_Class=28
Mass test: TS0(xOxxxxOx)TS7 MS_Class=29
Mass test: TS0(xOxxxxOx)TS7 MS_Class=30
Mass test: TS0(xOxxxxOx)TS7 MS_Class=31
Mass test: TS0(xOxxxxOx)TS7 MS_Class=32
Mass test: TS0(xOxxxxOx)TS7 MS_Class=33
Mass test: TS0(xOxxxxOx)TS7 MS_Class=34
Mass test: TS0(xOxxxxOx)TS7 MS_Class=35
Mass test: TS0(xOxxxxOx)TS7 MS_Class=36
Mass test: TS0(xOxxxxOx)TS7 MS_Class=37
Mass test: TS0(xOxxxxOx)TS7 MS_Class=38
Mass test: TS0(xOxxxxOx)TS7 MS_Class=39
Mass test: TS0(xOxxxxOx)TS7 MS_Class=40
Mass test: TS0(xOxxxxOx)TS7 MS_Class=41
Mass test: TS0(xOxxxxOx)TS7 MS_Class=42
Mass test: TS0(xOxxxxOx)TS7 MS_Class=43
Mass test: TS0(xOxxxxOx)TS7 MS_Class=44
Mass test: TS0(xOxxxxOx)TS7 MS_Class=45
Mass test: TS0(xOxxxxOO)TS7 MS_Class=0
Mass test: TS0(xOxxxxOO)TS7 MS_Class=1
Mass test: TS0(xOxxxxOO)TS7 MS_Class=2
Mass test: TS0(xOxxxxOO)TS7 MS_Class=3
Mass test: TS0(xOxxxxOO)TS7 MS_Class=4
Mass test: TS0(xOxxxxOO)TS7 MS_Class=5
Mass test: TS0(xOxxxxOO)TS7 MS_Class=6
Mass test: TS0(xOxxxxOO)TS7 MS_Class=7
Mass test: TS0(xOxxxxOO)TS7 MS_Class=8
Mass test: TS0(xOxxxxOO)TS7 MS_Class=9
Mass test: TS0(xOxxxxOO)TS7 MS_Class=10
Mass test: TS0(xOxxxxOO)TS7 MS_Class=11
Mass test: TS0(xOxxxxOO)TS7 MS_Class=12
Mass test: TS0(xOxxxxOO)TS7 MS_Class=13
Mass test: TS0(xOxxxxOO)TS7 MS_Class=14
Mass test: TS0(xOxxxxOO)TS7 MS_Class=15
Mass test: TS0(xOxxxxOO)TS7 MS_Class=16
Mass test: TS0(xOxxxxOO)TS7 MS_Class=17
Mass test: TS0(xOxxxxOO)TS7 MS_Class=18
Mass test: TS0(xOxxxxOO)TS7 MS_Class=19
Mass test: TS0(xOxxxxOO)TS7 MS_Class=20
Mass test: TS0(xOxxxxOO)TS7 MS_Class=21
Mass test: TS0(xOxxxxOO)TS7 MS_Class=22
Mass test: TS0(xOxxxxOO)TS7 MS_Class=23
Mass test: TS0(xOxxxxOO)TS7 MS_Class=24
Mass test: TS0(xOxxxxOO)TS7 MS_Class=25
Mass test: TS0(xOxxxxOO)TS7 MS_Class=26
Mass test: TS0(xOxxxxOO)TS7 MS_Class=27
Mass test: TS0(xOxxxxOO)TS7 MS_Class=28
Mass test: TS0(xOxxxxOO)TS7 MS_Class=29
Mass test: TS0(xOxxxxOO)TS7 MS_Class=30
Mass test: TS0(xOxxxxOO)TS7 MS_Class=31
Mass test: TS0(xOxxxxOO)TS7 MS_Class=32
Mass test: TS0(xOxxxxOO)TS7 MS_Class=33
Mass test: TS0(xOxxxxOO)TS7 MS_Class=34
Mass test: TS0(xOxxxxOO)TS7 MS_Class=35
Mass test: TS0(xOxxxxOO)TS7 MS_Class=36
Mass test: TS0(xOxxxxOO)TS7 MS_Class=37
Mass test: TS0(xOxxxxOO)TS7 MS_Class=38
Mass test: TS0(xOxxxxOO)TS7 MS_Class=39
Mass test: TS0(xOxxxxOO)TS7 MS_Class=40
Mass test: TS0(xOxxxxOO)TS7 MS_Class=41
Mass test: TS0(xOxxxxOO)TS7 MS_Class=42
Mass test: TS0(xOxxxxOO)TS7 MS_Class=43
Mass test: TS0(xOxxxxOO)TS7 MS_Class=44
Mass test: TS0(xOxxxxOO)TS7 MS_Class=45
Mass test: TS0(xOxxxOxx)TS7 MS_Class=0
Mass test: TS0(xOxxxOxx)TS7 MS_Class=1
Mass test: TS0(xOxxxOxx)TS7 MS_Class=2
Mass test: TS0(xOxxxOxx)TS7 MS_Class=3
Mass test: TS0(xOxxxOxx)TS7 MS_Class=4
Mass test: TS0(xOxxxOxx)TS7 MS_Class=5
Mass test: TS0(xOxxxOxx)TS7 MS_Class=6
Mass test: TS0(xOxxxOxx)TS7 MS_Class=7
Mass test: TS0(xOxxxOxx)TS7 MS_Class=8
Mass test: TS0(xOxxxOxx)TS7 MS_Class=9
Mass test: TS0(xOxxxOxx)TS7 MS_Class=10
Mass test: TS0(xOxxxOxx)TS7 MS_Class=11
Mass test: TS0(xOxxxOxx)TS7 MS_Class=12
Mass test: TS0(xOxxxOxx)TS7 MS_Class=13
Mass test: TS0(xOxxxOxx)TS7 MS_Class=14
Mass test: TS0(xOxxxOxx)TS7 MS_Class=15
Mass test: TS0(xOxxxOxx)TS7 MS_Class=16
Mass test: TS0(xOxxxOxx)TS7 MS_Class=17
Mass test: TS0(xOxxxOxx)TS7 MS_Class=18
Mass test: TS0(xOxxxOxx)TS7 MS_Class=19
Mass test: TS0(xOxxxOxx)TS7 MS_Class=20
Mass test: TS0(xOxxxOxx)TS7 MS_Class=21
Mass test: TS0(xOxxxOxx)TS7 MS_Class=22
Mass test: TS0(xOxxxOxx)TS7 MS_Class=23
Mass test: TS0(xOxxxOxx)TS7 MS_Class=24
Mass test: TS0(xOxxxOxx)TS7 MS_Class=25
Mass test: TS0(xOxxxOxx)TS7 MS_Class=26
Mass test: TS0(xOxxxOxx)TS7 MS_Class=27
Mass test: TS0(xOxxxOxx)TS7 MS_Class=28
Mass test: TS0(xOxxxOxx)TS7 MS_Class=29
Mass test: TS0(xOxxxOxx)TS7 MS_Class=30
Mass test: TS0(xOxxxOxx)TS7 MS_Class=31
Mass test: TS0(xOxxxOxx)TS7 MS_Class=32
Mass test: TS0(xOxxxOxx)TS7 MS_Class=33
Mass test: TS0(xOxxxOxx)TS7 MS_Class=34
Mass test: TS0(xOxxxOxx)TS7 MS_Class=35
Mass test: TS0(xOxxxOxx)TS7 MS_Class=36
Mass test: TS0(xOxxxOxx)TS7 MS_Class=37
Mass test: TS0(xOxxxOxx)TS7 MS_Class=38
Mass test: TS0(xOxxxOxx)TS7 MS_Class=39
Mass test: TS0(xOxxxOxx)TS7 MS_Class=40
Mass test: TS0(xOxxxOxx)TS7 MS_Class=41
Mass test: TS0(xOxxxOxx)TS7 MS_Class=42
Mass test: TS0(xOxxxOxx)TS7 MS_Class=43
Mass test: TS0(xOxxxOxx)TS7 MS_Class=44
Mass test: TS0(xOxxxOxx)TS7 MS_Class=45
Mass test: TS0(xOxxxOxO)TS7 MS_Class=0
Mass test: TS0(xOxxxOxO)TS7 MS_Class=1
Mass test: TS0(xOxxxOxO)TS7 MS_Class=2
Mass test: TS0(xOxxxOxO)TS7 MS_Class=3
Mass test: TS0(xOxxxOxO)TS7 MS_Class=4
Mass test: TS0(xOxxxOxO)TS7 MS_Class=5
Mass test: TS0(xOxxxOxO)TS7 MS_Class=6
Mass test: TS0(xOxxxOxO)TS7 MS_Class=7
Mass test: TS0(xOxxxOxO)TS7 MS_Class=8
Mass test: TS0(xOxxxOxO)TS7 MS_Class=9
Mass test: TS0(xOxxxOxO)TS7 MS_Class=10
Mass test: TS0(xOxxxOxO)TS7 MS_Class=11
Mass test: TS0(xOxxxOxO)TS7 MS_Class=12
Mass test: TS0(xOxxxOxO)TS7 MS_Class=13
Mass test: TS0(xOxxxOxO)TS7 MS_Class=14
Mass test: TS0(xOxxxOxO)TS7 MS_Class=15
Mass test: TS0(xOxxxOxO)TS7 MS_Class=16
Mass test: TS0(xOxxxOxO)TS7 MS_Class=17
Mass test: TS0(xOxxxOxO)TS7 MS_Class=18
Mass test: TS0(xOxxxOxO)TS7 MS_Class=19
Mass test: TS0(xOxxxOxO)TS7 MS_Class=20
Mass test: TS0(xOxxxOxO)TS7 MS_Class=21
Mass test: TS0(xOxxxOxO)TS7 MS_Class=22
Mass test: TS0(xOxxxOxO)TS7 MS_Class=23
Mass test: TS0(xOxxxOxO)TS7 MS_Class=24
Mass test: TS0(xOxxxOxO)TS7 MS_Class=25
Mass test: TS0(xOxxxOxO)TS7 MS_Class=26
Mass test: TS0(xOxxxOxO)TS7 MS_Class=27
Mass test: TS0(xOxxxOxO)TS7 MS_Class=28
Mass test: TS0(xOxxxOxO)TS7 MS_Class=29
Mass test: TS0(xOxxxOxO)TS7 MS_Class=30
Mass test: TS0(xOxxxOxO)TS7 MS_Class=31
Mass test: TS0(xOxxxOxO)TS7 MS_Class=32
Mass test: TS0(xOxxxOxO)TS7 MS_Class=33
Mass test: TS0(xOxxxOxO)TS7 MS_Class=34
Mass test: TS0(xOxxxOxO)TS7 MS_Class=35
Mass test: TS0(xOxxxOxO)TS7 MS_Class=36
Mass test: TS0(xOxxxOxO)TS7 MS_Class=37
Mass test: TS0(xOxxxOxO)TS7 MS_Class=38
Mass test: TS0(xOxxxOxO)TS7 MS_Class=39
Mass test: TS0(xOxxxOxO)TS7 MS_Class=40
Mass test: TS0(xOxxxOxO)TS7 MS_Class=41
Mass test: TS0(xOxxxOxO)TS7 MS_Class=42
Mass test: TS0(xOxxxOxO)TS7 MS_Class=43
Mass test: TS0(xOxxxOxO)TS7 MS_Class=44
Mass test: TS0(xOxxxOxO)TS7 MS_Class=45
Mass test: TS0(xOxxxOOx)TS7 MS_Class=0
Mass test: TS0(xOxxxOOx)TS7 MS_Class=1
Mass test: TS0(xOxxxOOx)TS7 MS_Class=2
Mass test: TS0(xOxxxOOx)TS7 MS_Class=3
Mass test: TS0(xOxxxOOx)TS7 MS_Class=4
Mass test: TS0(xOxxxOOx)TS7 MS_Class=5
Mass test: TS0(xOxxxOOx)TS7 MS_Class=6
Mass test: TS0(xOxxxOOx)TS7 MS_Class=7
Mass test: TS0(xOxxxOOx)TS7 MS_Class=8
Mass test: TS0(xOxxxOOx)TS7 MS_Class=9
Mass test: TS0(xOxxxOOx)TS7 MS_Class=10
Mass test: TS0(xOxxxOOx)TS7 MS_Class=11
Mass test: TS0(xOxxxOOx)TS7 MS_Class=12
Mass test: TS0(xOxxxOOx)TS7 MS_Class=13
Mass test: TS0(xOxxxOOx)TS7 MS_Class=14
Mass test: TS0(xOxxxOOx)TS7 MS_Class=15
Mass test: TS0(xOxxxOOx)TS7 MS_Class=16
Mass test: TS0(xOxxxOOx)TS7 MS_Class=17
Mass test: TS0(xOxxxOOx)TS7 MS_Class=18
Mass test: TS0(xOxxxOOx)TS7 MS_Class=19
Mass test: TS0(xOxxxOOx)TS7 MS_Class=20
Mass test: TS0(xOxxxOOx)TS7 MS_Class=21
Mass test: TS0(xOxxxOOx)TS7 MS_Class=22
Mass test: TS0(xOxxxOOx)TS7 MS_Class=23
Mass test: TS0(xOxxxOOx)TS7 MS_Class=24
Mass test: TS0(xOxxxOOx)TS7 MS_Class=25
Mass test: TS0(xOxxxOOx)TS7 MS_Class=26
Mass test: TS0(xOxxxOOx)TS7 MS_Class=27
Mass test: TS0(xOxxxOOx)TS7 MS_Class=28
Mass test: TS0(xOxxxOOx)TS7 MS_Class=29
Mass test: TS0(xOxxxOOx)TS7 MS_Class=30
Mass test: TS0(xOxxxOOx)TS7 MS_Class=31
Mass test: TS0(xOxxxOOx)TS7 MS_Class=32
Mass test: TS0(xOxxxOOx)TS7 MS_Class=33
Mass test: TS0(xOxxxOOx)TS7 MS_Class=34
Mass test: TS0(xOxxxOOx)TS7 MS_Class=35
Mass test: TS0(xOxxxOOx)TS7 MS_Class=36
Mass test: TS0(xOxxxOOx)TS7 MS_Class=37
Mass test: TS0(xOxxxOOx)TS7 MS_Class=38
Mass test: TS0(xOxxxOOx)TS7 MS_Class=39
Mass test: TS0(xOxxxOOx)TS7 MS_Class=40
Mass test: TS0(xOxxxOOx)TS7 MS_Class=41
Mass test: TS0(xOxxxOOx)TS7 MS_Class=42
Mass test: TS0(xOxxxOOx)TS7 MS_Class=43
Mass test: TS0(xOxxxOOx)TS7 MS_Class=44
Mass test: TS0(xOxxxOOx)TS7 MS_Class=45
Mass test: TS0(xOxxxOOO)TS7 MS_Class=0
Mass test: TS0(xOxxxOOO)TS7 MS_Class=1
Mass test: TS0(xOxxxOOO)TS7 MS_Class=2
Mass test: TS0(xOxxxOOO)TS7 MS_Class=3
Mass test: TS0(xOxxxOOO)TS7 MS_Class=4
Mass test: TS0(xOxxxOOO)TS7 MS_Class=5
Mass test: TS0(xOxxxOOO)TS7 MS_Class=6
Mass test: TS0(xOxxxOOO)TS7 MS_Class=7
Mass test: TS0(xOxxxOOO)TS7 MS_Class=8
Mass test: TS0(xOxxxOOO)TS7 MS_Class=9
Mass test: TS0(xOxxxOOO)TS7 MS_Class=10
Mass test: TS0(xOxxxOOO)TS7 MS_Class=11
Mass test: TS0(xOxxxOOO)TS7 MS_Class=12
Mass test: TS0(xOxxxOOO)TS7 MS_Class=13
Mass test: TS0(xOxxxOOO)TS7 MS_Class=14
Mass test: TS0(xOxxxOOO)TS7 MS_Class=15
Mass test: TS0(xOxxxOOO)TS7 MS_Class=16
Mass test: TS0(xOxxxOOO)TS7 MS_Class=17
Mass test: TS0(xOxxxOOO)TS7 MS_Class=18
Mass test: TS0(xOxxxOOO)TS7 MS_Class=19
Mass test: TS0(xOxxxOOO)TS7 MS_Class=20
Mass test: TS0(xOxxxOOO)TS7 MS_Class=21
Mass test: TS0(xOxxxOOO)TS7 MS_Class=22
Mass test: TS0(xOxxxOOO)TS7 MS_Class=23
Mass test: TS0(xOxxxOOO)TS7 MS_Class=24
Mass test: TS0(xOxxxOOO)TS7 MS_Class=25
Mass test: TS0(xOxxxOOO)TS7 MS_Class=26
Mass test: TS0(xOxxxOOO)TS7 MS_Class=27
Mass test: TS0(xOxxxOOO)TS7 MS_Class=28
Mass test: TS0(xOxxxOOO)TS7 MS_Class=29
Mass test: TS0(xOxxxOOO)TS7 MS_Class=30
Mass test: TS0(xOxxxOOO)TS7 MS_Class=31
Mass test: TS0(xOxxxOOO)TS7 MS_Class=32
Mass test: TS0(xOxxxOOO)TS7 MS_Class=33
Mass test: TS0(xOxxxOOO)TS7 MS_Class=34
Mass test: TS0(xOxxxOOO)TS7 MS_Class=35
Mass test: TS0(xOxxxOOO)TS7 MS_Class=36
Mass test: TS0(xOxxxOOO)TS7 MS_Class=37
Mass test: TS0(xOxxxOOO)TS7 MS_Class=38
Mass test: TS0(xOxxxOOO)TS7 MS_Class=39
Mass test: TS0(xOxxxOOO)TS7 MS_Class=40
Mass test: TS0(xOxxxOOO)TS7 MS_Class=41
Mass test: TS0(xOxxxOOO)TS7 MS_Class=42
Mass test: TS0(xOxxxOOO)TS7 MS_Class=43
Mass test: TS0(xOxxxOOO)TS7 MS_Class=44
Mass test: TS0(xOxxxOOO)TS7 MS_Class=45
Mass test: TS0(xOxxOxxx)TS7 MS_Class=0
Mass test: TS0(xOxxOxxx)TS7 MS_Class=1
Mass test: TS0(xOxxOxxx)TS7 MS_Class=2
Mass test: TS0(xOxxOxxx)TS7 MS_Class=3
Mass test: TS0(xOxxOxxx)TS7 MS_Class=4
Mass test: TS0(xOxxOxxx)TS7 MS_Class=5
Mass test: TS0(xOxxOxxx)TS7 MS_Class=6
Mass test: TS0(xOxxOxxx)TS7 MS_Class=7
Mass test: TS0(xOxxOxxx)TS7 MS_Class=8
Mass test: TS0(xOxxOxxx)TS7 MS_Class=9
Mass test: TS0(xOxxOxxx)TS7 MS_Class=10
Mass test: TS0(xOxxOxxx)TS7 MS_Class=11
Mass test: TS0(xOxxOxxx)TS7 MS_Class=12
Mass test: TS0(xOxxOxxx)TS7 MS_Class=13
Mass test: TS0(xOxxOxxx)TS7 MS_Class=14
Mass test: TS0(xOxxOxxx)TS7 MS_Class=15
Mass test: TS0(xOxxOxxx)TS7 MS_Class=16
Mass test: TS0(xOxxOxxx)TS7 MS_Class=17
Mass test: TS0(xOxxOxxx)TS7 MS_Class=18
Mass test: TS0(xOxxOxxx)TS7 MS_Class=19
Mass test: TS0(xOxxOxxx)TS7 MS_Class=20
Mass test: TS0(xOxxOxxx)TS7 MS_Class=21
Mass test: TS0(xOxxOxxx)TS7 MS_Class=22
Mass test: TS0(xOxxOxxx)TS7 MS_Class=23
Mass test: TS0(xOxxOxxx)TS7 MS_Class=24
Mass test: TS0(xOxxOxxx)TS7 MS_Class=25
Mass test: TS0(xOxxOxxx)TS7 MS_Class=26
Mass test: TS0(xOxxOxxx)TS7 MS_Class=27
Mass test: TS0(xOxxOxxx)TS7 MS_Class=28
Mass test: TS0(xOxxOxxx)TS7 MS_Class=29
Mass test: TS0(xOxxOxxx)TS7 MS_Class=30
Mass test: TS0(xOxxOxxx)TS7 MS_Class=31
Mass test: TS0(xOxxOxxx)TS7 MS_Class=32
Mass test: TS0(xOxxOxxx)TS7 MS_Class=33
Mass test: TS0(xOxxOxxx)TS7 MS_Class=34
Mass test: TS0(xOxxOxxx)TS7 MS_Class=35
Mass test: TS0(xOxxOxxx)TS7 MS_Class=36
Mass test: TS0(xOxxOxxx)TS7 MS_Class=37
Mass test: TS0(xOxxOxxx)TS7 MS_Class=38
Mass test: TS0(xOxxOxxx)TS7 MS_Class=39
Mass test: TS0(xOxxOxxx)TS7 MS_Class=40
Mass test: TS0(xOxxOxxx)TS7 MS_Class=41
Mass test: TS0(xOxxOxxx)TS7 MS_Class=42
Mass test: TS0(xOxxOxxx)TS7 MS_Class=43
Mass test: TS0(xOxxOxxx)TS7 MS_Class=44
Mass test: TS0(xOxxOxxx)TS7 MS_Class=45
Mass test: TS0(xOxxOxxO)TS7 MS_Class=0
Mass test: TS0(xOxxOxxO)TS7 MS_Class=1
Mass test: TS0(xOxxOxxO)TS7 MS_Class=2
Mass test: TS0(xOxxOxxO)TS7 MS_Class=3
Mass test: TS0(xOxxOxxO)TS7 MS_Class=4
Mass test: TS0(xOxxOxxO)TS7 MS_Class=5
Mass test: TS0(xOxxOxxO)TS7 MS_Class=6
Mass test: TS0(xOxxOxxO)TS7 MS_Class=7
Mass test: TS0(xOxxOxxO)TS7 MS_Class=8
Mass test: TS0(xOxxOxxO)TS7 MS_Class=9
Mass test: TS0(xOxxOxxO)TS7 MS_Class=10
Mass test: TS0(xOxxOxxO)TS7 MS_Class=11
Mass test: TS0(xOxxOxxO)TS7 MS_Class=12
Mass test: TS0(xOxxOxxO)TS7 MS_Class=13
Mass test: TS0(xOxxOxxO)TS7 MS_Class=14
Mass test: TS0(xOxxOxxO)TS7 MS_Class=15
Mass test: TS0(xOxxOxxO)TS7 MS_Class=16
Mass test: TS0(xOxxOxxO)TS7 MS_Class=17
Mass test: TS0(xOxxOxxO)TS7 MS_Class=18
Mass test: TS0(xOxxOxxO)TS7 MS_Class=19
Mass test: TS0(xOxxOxxO)TS7 MS_Class=20
Mass test: TS0(xOxxOxxO)TS7 MS_Class=21
Mass test: TS0(xOxxOxxO)TS7 MS_Class=22
Mass test: TS0(xOxxOxxO)TS7 MS_Class=23
Mass test: TS0(xOxxOxxO)TS7 MS_Class=24
Mass test: TS0(xOxxOxxO)TS7 MS_Class=25
Mass test: TS0(xOxxOxxO)TS7 MS_Class=26
Mass test: TS0(xOxxOxxO)TS7 MS_Class=27
Mass test: TS0(xOxxOxxO)TS7 MS_Class=28
Mass test: TS0(xOxxOxxO)TS7 MS_Class=29
Mass test: TS0(xOxxOxxO)TS7 MS_Class=30
Mass test: TS0(xOxxOxxO)TS7 MS_Class=31
Mass test: TS0(xOxxOxxO)TS7 MS_Class=32
Mass test: TS0(xOxxOxxO)TS7 MS_Class=33
Mass test: TS0(xOxxOxxO)TS7 MS_Class=34
Mass test: TS0(xOxxOxxO)TS7 MS_Class=35
Mass test: TS0(xOxxOxxO)TS7 MS_Class=36
Mass test: TS0(xOxxOxxO)TS7 MS_Class=37
Mass test: TS0(xOxxOxxO)TS7 MS_Class=38
Mass test: TS0(xOxxOxxO)TS7 MS_Class=39
Mass test: TS0(xOxxOxxO)TS7 MS_Class=40
Mass test: TS0(xOxxOxxO)TS7 MS_Class=41
Mass test: TS0(xOxxOxxO)TS7 MS_Class=42
Mass test: TS0(xOxxOxxO)TS7 MS_Class=43
Mass test: TS0(xOxxOxxO)TS7 MS_Class=44
Mass test: TS0(xOxxOxxO)TS7 MS_Class=45
Mass test: TS0(xOxxOxOx)TS7 MS_Class=0
Mass test: TS0(xOxxOxOx)TS7 MS_Class=1
Mass test: TS0(xOxxOxOx)TS7 MS_Class=2
Mass test: TS0(xOxxOxOx)TS7 MS_Class=3
Mass test: TS0(xOxxOxOx)TS7 MS_Class=4
Mass test: TS0(xOxxOxOx)TS7 MS_Class=5
Mass test: TS0(xOxxOxOx)TS7 MS_Class=6
Mass test: TS0(xOxxOxOx)TS7 MS_Class=7
Mass test: TS0(xOxxOxOx)TS7 MS_Class=8
Mass test: TS0(xOxxOxOx)TS7 MS_Class=9
Mass test: TS0(xOxxOxOx)TS7 MS_Class=10
Mass test: TS0(xOxxOxOx)TS7 MS_Class=11
Mass test: TS0(xOxxOxOx)TS7 MS_Class=12
Mass test: TS0(xOxxOxOx)TS7 MS_Class=13
Mass test: TS0(xOxxOxOx)TS7 MS_Class=14
Mass test: TS0(xOxxOxOx)TS7 MS_Class=15
Mass test: TS0(xOxxOxOx)TS7 MS_Class=16
Mass test: TS0(xOxxOxOx)TS7 MS_Class=17
Mass test: TS0(xOxxOxOx)TS7 MS_Class=18
Mass test: TS0(xOxxOxOx)TS7 MS_Class=19
Mass test: TS0(xOxxOxOx)TS7 MS_Class=20
Mass test: TS0(xOxxOxOx)TS7 MS_Class=21
Mass test: TS0(xOxxOxOx)TS7 MS_Class=22
Mass test: TS0(xOxxOxOx)TS7 MS_Class=23
Mass test: TS0(xOxxOxOx)TS7 MS_Class=24
Mass test: TS0(xOxxOxOx)TS7 MS_Class=25
Mass test: TS0(xOxxOxOx)TS7 MS_Class=26
Mass test: TS0(xOxxOxOx)TS7 MS_Class=27
Mass test: TS0(xOxxOxOx)TS7 MS_Class=28
Mass test: TS0(xOxxOxOx)TS7 MS_Class=29
Mass test: TS0(xOxxOxOx)TS7 MS_Class=30
Mass test: TS0(xOxxOxOx)TS7 MS_Class=31
Mass test: TS0(xOxxOxOx)TS7 MS_Class=32
Mass test: TS0(xOxxOxOx)TS7 MS_Class=33
Mass test: TS0(xOxxOxOx)TS7 MS_Class=34
Mass test: TS0(xOxxOxOx)TS7 MS_Class=35
Mass test: TS0(xOxxOxOx)TS7 MS_Class=36
Mass test: TS0(xOxxOxOx)TS7 MS_Class=37
Mass test: TS0(xOxxOxOx)TS7 MS_Class=38
Mass test: TS0(xOxxOxOx)TS7 MS_Class=39
Mass test: TS0(xOxxOxOx)TS7 MS_Class=40
Mass test: TS0(xOxxOxOx)TS7 MS_Class=41
Mass test: TS0(xOxxOxOx)TS7 MS_Class=42
Mass test: TS0(xOxxOxOx)TS7 MS_Class=43
Mass test: TS0(xOxxOxOx)TS7 MS_Class=44
Mass test: TS0(xOxxOxOx)TS7 MS_Class=45
Mass test: TS0(xOxxOxOO)TS7 MS_Class=0
Mass test: TS0(xOxxOxOO)TS7 MS_Class=1
Mass test: TS0(xOxxOxOO)TS7 MS_Class=2
Mass test: TS0(xOxxOxOO)TS7 MS_Class=3
Mass test: TS0(xOxxOxOO)TS7 MS_Class=4
Mass test: TS0(xOxxOxOO)TS7 MS_Class=5
Mass test: TS0(xOxxOxOO)TS7 MS_Class=6
Mass test: TS0(xOxxOxOO)TS7 MS_Class=7
Mass test: TS0(xOxxOxOO)TS7 MS_Class=8
Mass test: TS0(xOxxOxOO)TS7 MS_Class=9
Mass test: TS0(xOxxOxOO)TS7 MS_Class=10
Mass test: TS0(xOxxOxOO)TS7 MS_Class=11
Mass test: TS0(xOxxOxOO)TS7 MS_Class=12
Mass test: TS0(xOxxOxOO)TS7 MS_Class=13
Mass test: TS0(xOxxOxOO)TS7 MS_Class=14
Mass test: TS0(xOxxOxOO)TS7 MS_Class=15
Mass test: TS0(xOxxOxOO)TS7 MS_Class=16
Mass test: TS0(xOxxOxOO)TS7 MS_Class=17
Mass test: TS0(xOxxOxOO)TS7 MS_Class=18
Mass test: TS0(xOxxOxOO)TS7 MS_Class=19
Mass test: TS0(xOxxOxOO)TS7 MS_Class=20
Mass test: TS0(xOxxOxOO)TS7 MS_Class=21
Mass test: TS0(xOxxOxOO)TS7 MS_Class=22
Mass test: TS0(xOxxOxOO)TS7 MS_Class=23
Mass test: TS0(xOxxOxOO)TS7 MS_Class=24
Mass test: TS0(xOxxOxOO)TS7 MS_Class=25
Mass test: TS0(xOxxOxOO)TS7 MS_Class=26
Mass test: TS0(xOxxOxOO)TS7 MS_Class=27
Mass test: TS0(xOxxOxOO)TS7 MS_Class=28
Mass test: TS0(xOxxOxOO)TS7 MS_Class=29
Mass test: TS0(xOxxOxOO)TS7 MS_Class=30
Mass test: TS0(xOxxOxOO)TS7 MS_Class=31
Mass test: TS0(xOxxOxOO)TS7 MS_Class=32
Mass test: TS0(xOxxOxOO)TS7 MS_Class=33
Mass test: TS0(xOxxOxOO)TS7 MS_Class=34
Mass test: TS0(xOxxOxOO)TS7 MS_Class=35
Mass test: TS0(xOxxOxOO)TS7 MS_Class=36
Mass test: TS0(xOxxOxOO)TS7 MS_Class=37
Mass test: TS0(xOxxOxOO)TS7 MS_Class=38
Mass test: TS0(xOxxOxOO)TS7 MS_Class=39
Mass test: TS0(xOxxOxOO)TS7 MS_Class=40
Mass test: TS0(xOxxOxOO)TS7 MS_Class=41
Mass test: TS0(xOxxOxOO)TS7 MS_Class=42
Mass test: TS0(xOxxOxOO)TS7 MS_Class=43
Mass test: TS0(xOxxOxOO)TS7 MS_Class=44
Mass test: TS0(xOxxOxOO)TS7 MS_Class=45
Mass test: TS0(xOxxOOxx)TS7 MS_Class=0
Mass test: TS0(xOxxOOxx)TS7 MS_Class=1
Mass test: TS0(xOxxOOxx)TS7 MS_Class=2
Mass test: TS0(xOxxOOxx)TS7 MS_Class=3
Mass test: TS0(xOxxOOxx)TS7 MS_Class=4
Mass test: TS0(xOxxOOxx)TS7 MS_Class=5
Mass test: TS0(xOxxOOxx)TS7 MS_Class=6
Mass test: TS0(xOxxOOxx)TS7 MS_Class=7
Mass test: TS0(xOxxOOxx)TS7 MS_Class=8
Mass test: TS0(xOxxOOxx)TS7 MS_Class=9
Mass test: TS0(xOxxOOxx)TS7 MS_Class=10
Mass test: TS0(xOxxOOxx)TS7 MS_Class=11
Mass test: TS0(xOxxOOxx)TS7 MS_Class=12
Mass test: TS0(xOxxOOxx)TS7 MS_Class=13
Mass test: TS0(xOxxOOxx)TS7 MS_Class=14
Mass test: TS0(xOxxOOxx)TS7 MS_Class=15
Mass test: TS0(xOxxOOxx)TS7 MS_Class=16
Mass test: TS0(xOxxOOxx)TS7 MS_Class=17
Mass test: TS0(xOxxOOxx)TS7 MS_Class=18
Mass test: TS0(xOxxOOxx)TS7 MS_Class=19
Mass test: TS0(xOxxOOxx)TS7 MS_Class=20
Mass test: TS0(xOxxOOxx)TS7 MS_Class=21
Mass test: TS0(xOxxOOxx)TS7 MS_Class=22
Mass test: TS0(xOxxOOxx)TS7 MS_Class=23
Mass test: TS0(xOxxOOxx)TS7 MS_Class=24
Mass test: TS0(xOxxOOxx)TS7 MS_Class=25
Mass test: TS0(xOxxOOxx)TS7 MS_Class=26
Mass test: TS0(xOxxOOxx)TS7 MS_Class=27
Mass test: TS0(xOxxOOxx)TS7 MS_Class=28
Mass test: TS0(xOxxOOxx)TS7 MS_Class=29
Mass test: TS0(xOxxOOxx)TS7 MS_Class=30
Mass test: TS0(xOxxOOxx)TS7 MS_Class=31
Mass test: TS0(xOxxOOxx)TS7 MS_Class=32
Mass test: TS0(xOxxOOxx)TS7 MS_Class=33
Mass test: TS0(xOxxOOxx)TS7 MS_Class=34
Mass test: TS0(xOxxOOxx)TS7 MS_Class=35
Mass test: TS0(xOxxOOxx)TS7 MS_Class=36
Mass test: TS0(xOxxOOxx)TS7 MS_Class=37
Mass test: TS0(xOxxOOxx)TS7 MS_Class=38
Mass test: TS0(xOxxOOxx)TS7 MS_Class=39
Mass test: TS0(xOxxOOxx)TS7 MS_Class=40
Mass test: TS0(xOxxOOxx)TS7 MS_Class=41
Mass test: TS0(xOxxOOxx)TS7 MS_Class=42
Mass test: TS0(xOxxOOxx)TS7 MS_Class=43
Mass test: TS0(xOxxOOxx)TS7 MS_Class=44
Mass test: TS0(xOxxOOxx)TS7 MS_Class=45
Mass test: TS0(xOxxOOxO)TS7 MS_Class=0
Mass test: TS0(xOxxOOxO)TS7 MS_Class=1
Mass test: TS0(xOxxOOxO)TS7 MS_Class=2
Mass test: TS0(xOxxOOxO)TS7 MS_Class=3
Mass test: TS0(xOxxOOxO)TS7 MS_Class=4
Mass test: TS0(xOxxOOxO)TS7 MS_Class=5
Mass test: TS0(xOxxOOxO)TS7 MS_Class=6
Mass test: TS0(xOxxOOxO)TS7 MS_Class=7
Mass test: TS0(xOxxOOxO)TS7 MS_Class=8
Mass test: TS0(xOxxOOxO)TS7 MS_Class=9
Mass test: TS0(xOxxOOxO)TS7 MS_Class=10
Mass test: TS0(xOxxOOxO)TS7 MS_Class=11
Mass test: TS0(xOxxOOxO)TS7 MS_Class=12
Mass test: TS0(xOxxOOxO)TS7 MS_Class=13
Mass test: TS0(xOxxOOxO)TS7 MS_Class=14
Mass test: TS0(xOxxOOxO)TS7 MS_Class=15
Mass test: TS0(xOxxOOxO)TS7 MS_Class=16
Mass test: TS0(xOxxOOxO)TS7 MS_Class=17
Mass test: TS0(xOxxOOxO)TS7 MS_Class=18
Mass test: TS0(xOxxOOxO)TS7 MS_Class=19
Mass test: TS0(xOxxOOxO)TS7 MS_Class=20
Mass test: TS0(xOxxOOxO)TS7 MS_Class=21
Mass test: TS0(xOxxOOxO)TS7 MS_Class=22
Mass test: TS0(xOxxOOxO)TS7 MS_Class=23
Mass test: TS0(xOxxOOxO)TS7 MS_Class=24
Mass test: TS0(xOxxOOxO)TS7 MS_Class=25
Mass test: TS0(xOxxOOxO)TS7 MS_Class=26
Mass test: TS0(xOxxOOxO)TS7 MS_Class=27
Mass test: TS0(xOxxOOxO)TS7 MS_Class=28
Mass test: TS0(xOxxOOxO)TS7 MS_Class=29
Mass test: TS0(xOxxOOxO)TS7 MS_Class=30
Mass test: TS0(xOxxOOxO)TS7 MS_Class=31
Mass test: TS0(xOxxOOxO)TS7 MS_Class=32
Mass test: TS0(xOxxOOxO)TS7 MS_Class=33
Mass test: TS0(xOxxOOxO)TS7 MS_Class=34
Mass test: TS0(xOxxOOxO)TS7 MS_Class=35
Mass test: TS0(xOxxOOxO)TS7 MS_Class=36
Mass test: TS0(xOxxOOxO)TS7 MS_Class=37
Mass test: TS0(xOxxOOxO)TS7 MS_Class=38
Mass test: TS0(xOxxOOxO)TS7 MS_Class=39
Mass test: TS0(xOxxOOxO)TS7 MS_Class=40
Mass test: TS0(xOxxOOxO)TS7 MS_Class=41
Mass test: TS0(xOxxOOxO)TS7 MS_Class=42
Mass test: TS0(xOxxOOxO)TS7 MS_Class=43
Mass test: TS0(xOxxOOxO)TS7 MS_Class=44
Mass test: TS0(xOxxOOxO)TS7 MS_Class=45
Mass test: TS0(xOxxOOOx)TS7 MS_Class=0
Mass test: TS0(xOxxOOOx)TS7 MS_Class=1
Mass test: TS0(xOxxOOOx)TS7 MS_Class=2
Mass test: TS0(xOxxOOOx)TS7 MS_Class=3
Mass test: TS0(xOxxOOOx)TS7 MS_Class=4
Mass test: TS0(xOxxOOOx)TS7 MS_Class=5
Mass test: TS0(xOxxOOOx)TS7 MS_Class=6
Mass test: TS0(xOxxOOOx)TS7 MS_Class=7
Mass test: TS0(xOxxOOOx)TS7 MS_Class=8
Mass test: TS0(xOxxOOOx)TS7 MS_Class=9
Mass test: TS0(xOxxOOOx)TS7 MS_Class=10
Mass test: TS0(xOxxOOOx)TS7 MS_Class=11
Mass test: TS0(xOxxOOOx)TS7 MS_Class=12
Mass test: TS0(xOxxOOOx)TS7 MS_Class=13
Mass test: TS0(xOxxOOOx)TS7 MS_Class=14
Mass test: TS0(xOxxOOOx)TS7 MS_Class=15
Mass test: TS0(xOxxOOOx)TS7 MS_Class=16
Mass test: TS0(xOxxOOOx)TS7 MS_Class=17
Mass test: TS0(xOxxOOOx)TS7 MS_Class=18
Mass test: TS0(xOxxOOOx)TS7 MS_Class=19
Mass test: TS0(xOxxOOOx)TS7 MS_Class=20
Mass test: TS0(xOxxOOOx)TS7 MS_Class=21
Mass test: TS0(xOxxOOOx)TS7 MS_Class=22
Mass test: TS0(xOxxOOOx)TS7 MS_Class=23
Mass test: TS0(xOxxOOOx)TS7 MS_Class=24
Mass test: TS0(xOxxOOOx)TS7 MS_Class=25
Mass test: TS0(xOxxOOOx)TS7 MS_Class=26
Mass test: TS0(xOxxOOOx)TS7 MS_Class=27
Mass test: TS0(xOxxOOOx)TS7 MS_Class=28
Mass test: TS0(xOxxOOOx)TS7 MS_Class=29
Mass test: TS0(xOxxOOOx)TS7 MS_Class=30
Mass test: TS0(xOxxOOOx)TS7 MS_Class=31
Mass test: TS0(xOxxOOOx)TS7 MS_Class=32
Mass test: TS0(xOxxOOOx)TS7 MS_Class=33
Mass test: TS0(xOxxOOOx)TS7 MS_Class=34
Mass test: TS0(xOxxOOOx)TS7 MS_Class=35
Mass test: TS0(xOxxOOOx)TS7 MS_Class=36
Mass test: TS0(xOxxOOOx)TS7 MS_Class=37
Mass test: TS0(xOxxOOOx)TS7 MS_Class=38
Mass test: TS0(xOxxOOOx)TS7 MS_Class=39
Mass test: TS0(xOxxOOOx)TS7 MS_Class=40
Mass test: TS0(xOxxOOOx)TS7 MS_Class=41
Mass test: TS0(xOxxOOOx)TS7 MS_Class=42
Mass test: TS0(xOxxOOOx)TS7 MS_Class=43
Mass test: TS0(xOxxOOOx)TS7 MS_Class=44
Mass test: TS0(xOxxOOOx)TS7 MS_Class=45
Mass test: TS0(xOxxOOOO)TS7 MS_Class=0
Mass test: TS0(xOxxOOOO)TS7 MS_Class=1
Mass test: TS0(xOxxOOOO)TS7 MS_Class=2
Mass test: TS0(xOxxOOOO)TS7 MS_Class=3
Mass test: TS0(xOxxOOOO)TS7 MS_Class=4
Mass test: TS0(xOxxOOOO)TS7 MS_Class=5
Mass test: TS0(xOxxOOOO)TS7 MS_Class=6
Mass test: TS0(xOxxOOOO)TS7 MS_Class=7
Mass test: TS0(xOxxOOOO)TS7 MS_Class=8
Mass test: TS0(xOxxOOOO)TS7 MS_Class=9
Mass test: TS0(xOxxOOOO)TS7 MS_Class=10
Mass test: TS0(xOxxOOOO)TS7 MS_Class=11
Mass test: TS0(xOxxOOOO)TS7 MS_Class=12
Mass test: TS0(xOxxOOOO)TS7 MS_Class=13
Mass test: TS0(xOxxOOOO)TS7 MS_Class=14
Mass test: TS0(xOxxOOOO)TS7 MS_Class=15
Mass test: TS0(xOxxOOOO)TS7 MS_Class=16
Mass test: TS0(xOxxOOOO)TS7 MS_Class=17
Mass test: TS0(xOxxOOOO)TS7 MS_Class=18
Mass test: TS0(xOxxOOOO)TS7 MS_Class=19
Mass test: TS0(xOxxOOOO)TS7 MS_Class=20
Mass test: TS0(xOxxOOOO)TS7 MS_Class=21
Mass test: TS0(xOxxOOOO)TS7 MS_Class=22
Mass test: TS0(xOxxOOOO)TS7 MS_Class=23
Mass test: TS0(xOxxOOOO)TS7 MS_Class=24
Mass test: TS0(xOxxOOOO)TS7 MS_Class=25
Mass test: TS0(xOxxOOOO)TS7 MS_Class=26
Mass test: TS0(xOxxOOOO)TS7 MS_Class=27
Mass test: TS0(xOxxOOOO)TS7 MS_Class=28
Mass test: TS0(xOxxOOOO)TS7 MS_Class=29
Mass test: TS0(xOxxOOOO)TS7 MS_Class=30
Mass test: TS0(xOxxOOOO)TS7 MS_Class=31
Mass test: TS0(xOxxOOOO)TS7 MS_Class=32
Mass test: TS0(xOxxOOOO)TS7 MS_Class=33
Mass test: TS0(xOxxOOOO)TS7 MS_Class=34
Mass test: TS0(xOxxOOOO)TS7 MS_Class=35
Mass test: TS0(xOxxOOOO)TS7 MS_Class=36
Mass test: TS0(xOxxOOOO)TS7 MS_Class=37
Mass test: TS0(xOxxOOOO)TS7 MS_Class=38
Mass test: TS0(xOxxOOOO)TS7 MS_Class=39
Mass test: TS0(xOxxOOOO)TS7 MS_Class=40
Mass test: TS0(xOxxOOOO)TS7 MS_Class=41
Mass test: TS0(xOxxOOOO)TS7 MS_Class=42
Mass test: TS0(xOxxOOOO)TS7 MS_Class=43
Mass test: TS0(xOxxOOOO)TS7 MS_Class=44
Mass test: TS0(xOxxOOOO)TS7 MS_Class=45
Mass test: TS0(xOxOxxxx)TS7 MS_Class=0
Mass test: TS0(xOxOxxxx)TS7 MS_Class=1
Mass test: TS0(xOxOxxxx)TS7 MS_Class=2
Mass test: TS0(xOxOxxxx)TS7 MS_Class=3
Mass test: TS0(xOxOxxxx)TS7 MS_Class=4
Mass test: TS0(xOxOxxxx)TS7 MS_Class=5
Mass test: TS0(xOxOxxxx)TS7 MS_Class=6
Mass test: TS0(xOxOxxxx)TS7 MS_Class=7
Mass test: TS0(xOxOxxxx)TS7 MS_Class=8
Mass test: TS0(xOxOxxxx)TS7 MS_Class=9
Mass test: TS0(xOxOxxxx)TS7 MS_Class=10
Mass test: TS0(xOxOxxxx)TS7 MS_Class=11
Mass test: TS0(xOxOxxxx)TS7 MS_Class=12
Mass test: TS0(xOxOxxxx)TS7 MS_Class=13
Mass test: TS0(xOxOxxxx)TS7 MS_Class=14
Mass test: TS0(xOxOxxxx)TS7 MS_Class=15
Mass test: TS0(xOxOxxxx)TS7 MS_Class=16
Mass test: TS0(xOxOxxxx)TS7 MS_Class=17
Mass test: TS0(xOxOxxxx)TS7 MS_Class=18
Mass test: TS0(xOxOxxxx)TS7 MS_Class=19
Mass test: TS0(xOxOxxxx)TS7 MS_Class=20
Mass test: TS0(xOxOxxxx)TS7 MS_Class=21
Mass test: TS0(xOxOxxxx)TS7 MS_Class=22
Mass test: TS0(xOxOxxxx)TS7 MS_Class=23
Mass test: TS0(xOxOxxxx)TS7 MS_Class=24
Mass test: TS0(xOxOxxxx)TS7 MS_Class=25
Mass test: TS0(xOxOxxxx)TS7 MS_Class=26
Mass test: TS0(xOxOxxxx)TS7 MS_Class=27
Mass test: TS0(xOxOxxxx)TS7 MS_Class=28
Mass test: TS0(xOxOxxxx)TS7 MS_Class=29
Mass test: TS0(xOxOxxxx)TS7 MS_Class=30
Mass test: TS0(xOxOxxxx)TS7 MS_Class=31
Mass test: TS0(xOxOxxxx)TS7 MS_Class=32
Mass test: TS0(xOxOxxxx)TS7 MS_Class=33
Mass test: TS0(xOxOxxxx)TS7 MS_Class=34
Mass test: TS0(xOxOxxxx)TS7 MS_Class=35
Mass test: TS0(xOxOxxxx)TS7 MS_Class=36
Mass test: TS0(xOxOxxxx)TS7 MS_Class=37
Mass test: TS0(xOxOxxxx)TS7 MS_Class=38
Mass test: TS0(xOxOxxxx)TS7 MS_Class=39
Mass test: TS0(xOxOxxxx)TS7 MS_Class=40
Mass test: TS0(xOxOxxxx)TS7 MS_Class=41
Mass test: TS0(xOxOxxxx)TS7 MS_Class=42
Mass test: TS0(xOxOxxxx)TS7 MS_Class=43
Mass test: TS0(xOxOxxxx)TS7 MS_Class=44
Mass test: TS0(xOxOxxxx)TS7 MS_Class=45
Mass test: TS0(xOxOxxxO)TS7 MS_Class=0
Mass test: TS0(xOxOxxxO)TS7 MS_Class=1
Mass test: TS0(xOxOxxxO)TS7 MS_Class=2
Mass test: TS0(xOxOxxxO)TS7 MS_Class=3
Mass test: TS0(xOxOxxxO)TS7 MS_Class=4
Mass test: TS0(xOxOxxxO)TS7 MS_Class=5
Mass test: TS0(xOxOxxxO)TS7 MS_Class=6
Mass test: TS0(xOxOxxxO)TS7 MS_Class=7
Mass test: TS0(xOxOxxxO)TS7 MS_Class=8
Mass test: TS0(xOxOxxxO)TS7 MS_Class=9
Mass test: TS0(xOxOxxxO)TS7 MS_Class=10
Mass test: TS0(xOxOxxxO)TS7 MS_Class=11
Mass test: TS0(xOxOxxxO)TS7 MS_Class=12
Mass test: TS0(xOxOxxxO)TS7 MS_Class=13
Mass test: TS0(xOxOxxxO)TS7 MS_Class=14
Mass test: TS0(xOxOxxxO)TS7 MS_Class=15
Mass test: TS0(xOxOxxxO)TS7 MS_Class=16
Mass test: TS0(xOxOxxxO)TS7 MS_Class=17
Mass test: TS0(xOxOxxxO)TS7 MS_Class=18
Mass test: TS0(xOxOxxxO)TS7 MS_Class=19
Mass test: TS0(xOxOxxxO)TS7 MS_Class=20
Mass test: TS0(xOxOxxxO)TS7 MS_Class=21
Mass test: TS0(xOxOxxxO)TS7 MS_Class=22
Mass test: TS0(xOxOxxxO)TS7 MS_Class=23
Mass test: TS0(xOxOxxxO)TS7 MS_Class=24
Mass test: TS0(xOxOxxxO)TS7 MS_Class=25
Mass test: TS0(xOxOxxxO)TS7 MS_Class=26
Mass test: TS0(xOxOxxxO)TS7 MS_Class=27
Mass test: TS0(xOxOxxxO)TS7 MS_Class=28
Mass test: TS0(xOxOxxxO)TS7 MS_Class=29
Mass test: TS0(xOxOxxxO)TS7 MS_Class=30
Mass test: TS0(xOxOxxxO)TS7 MS_Class=31
Mass test: TS0(xOxOxxxO)TS7 MS_Class=32
Mass test: TS0(xOxOxxxO)TS7 MS_Class=33
Mass test: TS0(xOxOxxxO)TS7 MS_Class=34
Mass test: TS0(xOxOxxxO)TS7 MS_Class=35
Mass test: TS0(xOxOxxxO)TS7 MS_Class=36
Mass test: TS0(xOxOxxxO)TS7 MS_Class=37
Mass test: TS0(xOxOxxxO)TS7 MS_Class=38
Mass test: TS0(xOxOxxxO)TS7 MS_Class=39
Mass test: TS0(xOxOxxxO)TS7 MS_Class=40
Mass test: TS0(xOxOxxxO)TS7 MS_Class=41
Mass test: TS0(xOxOxxxO)TS7 MS_Class=42
Mass test: TS0(xOxOxxxO)TS7 MS_Class=43
Mass test: TS0(xOxOxxxO)TS7 MS_Class=44
Mass test: TS0(xOxOxxxO)TS7 MS_Class=45
Mass test: TS0(xOxOxxOx)TS7 MS_Class=0
Mass test: TS0(xOxOxxOx)TS7 MS_Class=1
Mass test: TS0(xOxOxxOx)TS7 MS_Class=2
Mass test: TS0(xOxOxxOx)TS7 MS_Class=3
Mass test: TS0(xOxOxxOx)TS7 MS_Class=4
Mass test: TS0(xOxOxxOx)TS7 MS_Class=5
Mass test: TS0(xOxOxxOx)TS7 MS_Class=6
Mass test: TS0(xOxOxxOx)TS7 MS_Class=7
Mass test: TS0(xOxOxxOx)TS7 MS_Class=8
Mass test: TS0(xOxOxxOx)TS7 MS_Class=9
Mass test: TS0(xOxOxxOx)TS7 MS_Class=10
Mass test: TS0(xOxOxxOx)TS7 MS_Class=11
Mass test: TS0(xOxOxxOx)TS7 MS_Class=12
Mass test: TS0(xOxOxxOx)TS7 MS_Class=13
Mass test: TS0(xOxOxxOx)TS7 MS_Class=14
Mass test: TS0(xOxOxxOx)TS7 MS_Class=15
Mass test: TS0(xOxOxxOx)TS7 MS_Class=16
Mass test: TS0(xOxOxxOx)TS7 MS_Class=17
Mass test: TS0(xOxOxxOx)TS7 MS_Class=18
Mass test: TS0(xOxOxxOx)TS7 MS_Class=19
Mass test: TS0(xOxOxxOx)TS7 MS_Class=20
Mass test: TS0(xOxOxxOx)TS7 MS_Class=21
Mass test: TS0(xOxOxxOx)TS7 MS_Class=22
Mass test: TS0(xOxOxxOx)TS7 MS_Class=23
Mass test: TS0(xOxOxxOx)TS7 MS_Class=24
Mass test: TS0(xOxOxxOx)TS7 MS_Class=25
Mass test: TS0(xOxOxxOx)TS7 MS_Class=26
Mass test: TS0(xOxOxxOx)TS7 MS_Class=27
Mass test: TS0(xOxOxxOx)TS7 MS_Class=28
Mass test: TS0(xOxOxxOx)TS7 MS_Class=29
Mass test: TS0(xOxOxxOx)TS7 MS_Class=30
Mass test: TS0(xOxOxxOx)TS7 MS_Class=31
Mass test: TS0(xOxOxxOx)TS7 MS_Class=32
Mass test: TS0(xOxOxxOx)TS7 MS_Class=33
Mass test: TS0(xOxOxxOx)TS7 MS_Class=34
Mass test: TS0(xOxOxxOx)TS7 MS_Class=35
Mass test: TS0(xOxOxxOx)TS7 MS_Class=36
Mass test: TS0(xOxOxxOx)TS7 MS_Class=37
Mass test: TS0(xOxOxxOx)TS7 MS_Class=38
Mass test: TS0(xOxOxxOx)TS7 MS_Class=39
Mass test: TS0(xOxOxxOx)TS7 MS_Class=40
Mass test: TS0(xOxOxxOx)TS7 MS_Class=41
Mass test: TS0(xOxOxxOx)TS7 MS_Class=42
Mass test: TS0(xOxOxxOx)TS7 MS_Class=43
Mass test: TS0(xOxOxxOx)TS7 MS_Class=44
Mass test: TS0(xOxOxxOx)TS7 MS_Class=45
Mass test: TS0(xOxOxxOO)TS7 MS_Class=0
Mass test: TS0(xOxOxxOO)TS7 MS_Class=1
Mass test: TS0(xOxOxxOO)TS7 MS_Class=2
Mass test: TS0(xOxOxxOO)TS7 MS_Class=3
Mass test: TS0(xOxOxxOO)TS7 MS_Class=4
Mass test: TS0(xOxOxxOO)TS7 MS_Class=5
Mass test: TS0(xOxOxxOO)TS7 MS_Class=6
Mass test: TS0(xOxOxxOO)TS7 MS_Class=7
Mass test: TS0(xOxOxxOO)TS7 MS_Class=8
Mass test: TS0(xOxOxxOO)TS7 MS_Class=9
Mass test: TS0(xOxOxxOO)TS7 MS_Class=10
Mass test: TS0(xOxOxxOO)TS7 MS_Class=11
Mass test: TS0(xOxOxxOO)TS7 MS_Class=12
Mass test: TS0(xOxOxxOO)TS7 MS_Class=13
Mass test: TS0(xOxOxxOO)TS7 MS_Class=14
Mass test: TS0(xOxOxxOO)TS7 MS_Class=15
Mass test: TS0(xOxOxxOO)TS7 MS_Class=16
Mass test: TS0(xOxOxxOO)TS7 MS_Class=17
Mass test: TS0(xOxOxxOO)TS7 MS_Class=18
Mass test: TS0(xOxOxxOO)TS7 MS_Class=19
Mass test: TS0(xOxOxxOO)TS7 MS_Class=20
Mass test: TS0(xOxOxxOO)TS7 MS_Class=21
Mass test: TS0(xOxOxxOO)TS7 MS_Class=22
Mass test: TS0(xOxOxxOO)TS7 MS_Class=23
Mass test: TS0(xOxOxxOO)TS7 MS_Class=24
Mass test: TS0(xOxOxxOO)TS7 MS_Class=25
Mass test: TS0(xOxOxxOO)TS7 MS_Class=26
Mass test: TS0(xOxOxxOO)TS7 MS_Class=27
Mass test: TS0(xOxOxxOO)TS7 MS_Class=28
Mass test: TS0(xOxOxxOO)TS7 MS_Class=29
Mass test: TS0(xOxOxxOO)TS7 MS_Class=30
Mass test: TS0(xOxOxxOO)TS7 MS_Class=31
Mass test: TS0(xOxOxxOO)TS7 MS_Class=32
Mass test: TS0(xOxOxxOO)TS7 MS_Class=33
Mass test: TS0(xOxOxxOO)TS7 MS_Class=34
Mass test: TS0(xOxOxxOO)TS7 MS_Class=35
Mass test: TS0(xOxOxxOO)TS7 MS_Class=36
Mass test: TS0(xOxOxxOO)TS7 MS_Class=37
Mass test: TS0(xOxOxxOO)TS7 MS_Class=38
Mass test: TS0(xOxOxxOO)TS7 MS_Class=39
Mass test: TS0(xOxOxxOO)TS7 MS_Class=40
Mass test: TS0(xOxOxxOO)TS7 MS_Class=41
Mass test: TS0(xOxOxxOO)TS7 MS_Class=42
Mass test: TS0(xOxOxxOO)TS7 MS_Class=43
Mass test: TS0(xOxOxxOO)TS7 MS_Class=44
Mass test: TS0(xOxOxxOO)TS7 MS_Class=45
Mass test: TS0(xOxOxOxx)TS7 MS_Class=0
Mass test: TS0(xOxOxOxx)TS7 MS_Class=1
Mass test: TS0(xOxOxOxx)TS7 MS_Class=2
Mass test: TS0(xOxOxOxx)TS7 MS_Class=3
Mass test: TS0(xOxOxOxx)TS7 MS_Class=4
Mass test: TS0(xOxOxOxx)TS7 MS_Class=5
Mass test: TS0(xOxOxOxx)TS7 MS_Class=6
Mass test: TS0(xOxOxOxx)TS7 MS_Class=7
Mass test: TS0(xOxOxOxx)TS7 MS_Class=8
Mass test: TS0(xOxOxOxx)TS7 MS_Class=9
Mass test: TS0(xOxOxOxx)TS7 MS_Class=10
Mass test: TS0(xOxOxOxx)TS7 MS_Class=11
Mass test: TS0(xOxOxOxx)TS7 MS_Class=12
Mass test: TS0(xOxOxOxx)TS7 MS_Class=13
Mass test: TS0(xOxOxOxx)TS7 MS_Class=14
Mass test: TS0(xOxOxOxx)TS7 MS_Class=15
Mass test: TS0(xOxOxOxx)TS7 MS_Class=16
Mass test: TS0(xOxOxOxx)TS7 MS_Class=17
Mass test: TS0(xOxOxOxx)TS7 MS_Class=18
Mass test: TS0(xOxOxOxx)TS7 MS_Class=19
Mass test: TS0(xOxOxOxx)TS7 MS_Class=20
Mass test: TS0(xOxOxOxx)TS7 MS_Class=21
Mass test: TS0(xOxOxOxx)TS7 MS_Class=22
Mass test: TS0(xOxOxOxx)TS7 MS_Class=23
Mass test: TS0(xOxOxOxx)TS7 MS_Class=24
Mass test: TS0(xOxOxOxx)TS7 MS_Class=25
Mass test: TS0(xOxOxOxx)TS7 MS_Class=26
Mass test: TS0(xOxOxOxx)TS7 MS_Class=27
Mass test: TS0(xOxOxOxx)TS7 MS_Class=28
Mass test: TS0(xOxOxOxx)TS7 MS_Class=29
Mass test: TS0(xOxOxOxx)TS7 MS_Class=30
Mass test: TS0(xOxOxOxx)TS7 MS_Class=31
Mass test: TS0(xOxOxOxx)TS7 MS_Class=32
Mass test: TS0(xOxOxOxx)TS7 MS_Class=33
Mass test: TS0(xOxOxOxx)TS7 MS_Class=34
Mass test: TS0(xOxOxOxx)TS7 MS_Class=35
Mass test: TS0(xOxOxOxx)TS7 MS_Class=36
Mass test: TS0(xOxOxOxx)TS7 MS_Class=37
Mass test: TS0(xOxOxOxx)TS7 MS_Class=38
Mass test: TS0(xOxOxOxx)TS7 MS_Class=39
Mass test: TS0(xOxOxOxx)TS7 MS_Class=40
Mass test: TS0(xOxOxOxx)TS7 MS_Class=41
Mass test: TS0(xOxOxOxx)TS7 MS_Class=42
Mass test: TS0(xOxOxOxx)TS7 MS_Class=43
Mass test: TS0(xOxOxOxx)TS7 MS_Class=44
Mass test: TS0(xOxOxOxx)TS7 MS_Class=45
Mass test: TS0(xOxOxOxO)TS7 MS_Class=0
Mass test: TS0(xOxOxOxO)TS7 MS_Class=1
Mass test: TS0(xOxOxOxO)TS7 MS_Class=2
Mass test: TS0(xOxOxOxO)TS7 MS_Class=3
Mass test: TS0(xOxOxOxO)TS7 MS_Class=4
Mass test: TS0(xOxOxOxO)TS7 MS_Class=5
Mass test: TS0(xOxOxOxO)TS7 MS_Class=6
Mass test: TS0(xOxOxOxO)TS7 MS_Class=7
Mass test: TS0(xOxOxOxO)TS7 MS_Class=8
Mass test: TS0(xOxOxOxO)TS7 MS_Class=9
Mass test: TS0(xOxOxOxO)TS7 MS_Class=10
Mass test: TS0(xOxOxOxO)TS7 MS_Class=11
Mass test: TS0(xOxOxOxO)TS7 MS_Class=12
Mass test: TS0(xOxOxOxO)TS7 MS_Class=13
Mass test: TS0(xOxOxOxO)TS7 MS_Class=14
Mass test: TS0(xOxOxOxO)TS7 MS_Class=15
Mass test: TS0(xOxOxOxO)TS7 MS_Class=16
Mass test: TS0(xOxOxOxO)TS7 MS_Class=17
Mass test: TS0(xOxOxOxO)TS7 MS_Class=18
Mass test: TS0(xOxOxOxO)TS7 MS_Class=19
Mass test: TS0(xOxOxOxO)TS7 MS_Class=20
Mass test: TS0(xOxOxOxO)TS7 MS_Class=21
Mass test: TS0(xOxOxOxO)TS7 MS_Class=22
Mass test: TS0(xOxOxOxO)TS7 MS_Class=23
Mass test: TS0(xOxOxOxO)TS7 MS_Class=24
Mass test: TS0(xOxOxOxO)TS7 MS_Class=25
Mass test: TS0(xOxOxOxO)TS7 MS_Class=26
Mass test: TS0(xOxOxOxO)TS7 MS_Class=27
Mass test: TS0(xOxOxOxO)TS7 MS_Class=28
Mass test: TS0(xOxOxOxO)TS7 MS_Class=29
Mass test: TS0(xOxOxOxO)TS7 MS_Class=30
Mass test: TS0(xOxOxOxO)TS7 MS_Class=31
Mass test: TS0(xOxOxOxO)TS7 MS_Class=32
Mass test: TS0(xOxOxOxO)TS7 MS_Class=33
Mass test: TS0(xOxOxOxO)TS7 MS_Class=34
Mass test: TS0(xOxOxOxO)TS7 MS_Class=35
Mass test: TS0(xOxOxOxO)TS7 MS_Class=36
Mass test: TS0(xOxOxOxO)TS7 MS_Class=37
Mass test: TS0(xOxOxOxO)TS7 MS_Class=38
Mass test: TS0(xOxOxOxO)TS7 MS_Class=39
Mass test: TS0(xOxOxOxO)TS7 MS_Class=40
Mass test: TS0(xOxOxOxO)TS7 MS_Class=41
Mass test: TS0(xOxOxOxO)TS7 MS_Class=42
Mass test: TS0(xOxOxOxO)TS7 MS_Class=43
Mass test: TS0(xOxOxOxO)TS7 MS_Class=44
Mass test: TS0(xOxOxOxO)TS7 MS_Class=45
Mass test: TS0(xOxOxOOx)TS7 MS_Class=0
Mass test: TS0(xOxOxOOx)TS7 MS_Class=1
Mass test: TS0(xOxOxOOx)TS7 MS_Class=2
Mass test: TS0(xOxOxOOx)TS7 MS_Class=3
Mass test: TS0(xOxOxOOx)TS7 MS_Class=4
Mass test: TS0(xOxOxOOx)TS7 MS_Class=5
Mass test: TS0(xOxOxOOx)TS7 MS_Class=6
Mass test: TS0(xOxOxOOx)TS7 MS_Class=7
Mass test: TS0(xOxOxOOx)TS7 MS_Class=8
Mass test: TS0(xOxOxOOx)TS7 MS_Class=9
Mass test: TS0(xOxOxOOx)TS7 MS_Class=10
Mass test: TS0(xOxOxOOx)TS7 MS_Class=11
Mass test: TS0(xOxOxOOx)TS7 MS_Class=12
Mass test: TS0(xOxOxOOx)TS7 MS_Class=13
Mass test: TS0(xOxOxOOx)TS7 MS_Class=14
Mass test: TS0(xOxOxOOx)TS7 MS_Class=15
Mass test: TS0(xOxOxOOx)TS7 MS_Class=16
Mass test: TS0(xOxOxOOx)TS7 MS_Class=17
Mass test: TS0(xOxOxOOx)TS7 MS_Class=18
Mass test: TS0(xOxOxOOx)TS7 MS_Class=19
Mass test: TS0(xOxOxOOx)TS7 MS_Class=20
Mass test: TS0(xOxOxOOx)TS7 MS_Class=21
Mass test: TS0(xOxOxOOx)TS7 MS_Class=22
Mass test: TS0(xOxOxOOx)TS7 MS_Class=23
Mass test: TS0(xOxOxOOx)TS7 MS_Class=24
Mass test: TS0(xOxOxOOx)TS7 MS_Class=25
Mass test: TS0(xOxOxOOx)TS7 MS_Class=26
Mass test: TS0(xOxOxOOx)TS7 MS_Class=27
Mass test: TS0(xOxOxOOx)TS7 MS_Class=28
Mass test: TS0(xOxOxOOx)TS7 MS_Class=29
Mass test: TS0(xOxOxOOx)TS7 MS_Class=30
Mass test: TS0(xOxOxOOx)TS7 MS_Class=31
Mass test: TS0(xOxOxOOx)TS7 MS_Class=32
Mass test: TS0(xOxOxOOx)TS7 MS_Class=33
Mass test: TS0(xOxOxOOx)TS7 MS_Class=34
Mass test: TS0(xOxOxOOx)TS7 MS_Class=35
Mass test: TS0(xOxOxOOx)TS7 MS_Class=36
Mass test: TS0(xOxOxOOx)TS7 MS_Class=37
Mass test: TS0(xOxOxOOx)TS7 MS_Class=38
Mass test: TS0(xOxOxOOx)TS7 MS_Class=39
Mass test: TS0(xOxOxOOx)TS7 MS_Class=40
Mass test: TS0(xOxOxOOx)TS7 MS_Class=41
Mass test: TS0(xOxOxOOx)TS7 MS_Class=42
Mass test: TS0(xOxOxOOx)TS7 MS_Class=43
Mass test: TS0(xOxOxOOx)TS7 MS_Class=44
Mass test: TS0(xOxOxOOx)TS7 MS_Class=45
Mass test: TS0(xOxOxOOO)TS7 MS_Class=0
Mass test: TS0(xOxOxOOO)TS7 MS_Class=1
Mass test: TS0(xOxOxOOO)TS7 MS_Class=2
Mass test: TS0(xOxOxOOO)TS7 MS_Class=3
Mass test: TS0(xOxOxOOO)TS7 MS_Class=4
Mass test: TS0(xOxOxOOO)TS7 MS_Class=5
Mass test: TS0(xOxOxOOO)TS7 MS_Class=6
Mass test: TS0(xOxOxOOO)TS7 MS_Class=7
Mass test: TS0(xOxOxOOO)TS7 MS_Class=8
Mass test: TS0(xOxOxOOO)TS7 MS_Class=9
Mass test: TS0(xOxOxOOO)TS7 MS_Class=10
Mass test: TS0(xOxOxOOO)TS7 MS_Class=11
Mass test: TS0(xOxOxOOO)TS7 MS_Class=12
Mass test: TS0(xOxOxOOO)TS7 MS_Class=13
Mass test: TS0(xOxOxOOO)TS7 MS_Class=14
Mass test: TS0(xOxOxOOO)TS7 MS_Class=15
Mass test: TS0(xOxOxOOO)TS7 MS_Class=16
Mass test: TS0(xOxOxOOO)TS7 MS_Class=17
Mass test: TS0(xOxOxOOO)TS7 MS_Class=18
Mass test: TS0(xOxOxOOO)TS7 MS_Class=19
Mass test: TS0(xOxOxOOO)TS7 MS_Class=20
Mass test: TS0(xOxOxOOO)TS7 MS_Class=21
Mass test: TS0(xOxOxOOO)TS7 MS_Class=22
Mass test: TS0(xOxOxOOO)TS7 MS_Class=23
Mass test: TS0(xOxOxOOO)TS7 MS_Class=24
Mass test: TS0(xOxOxOOO)TS7 MS_Class=25
Mass test: TS0(xOxOxOOO)TS7 MS_Class=26
Mass test: TS0(xOxOxOOO)TS7 MS_Class=27
Mass test: TS0(xOxOxOOO)TS7 MS_Class=28
Mass test: TS0(xOxOxOOO)TS7 MS_Class=29
Mass test: TS0(xOxOxOOO)TS7 MS_Class=30
Mass test: TS0(xOxOxOOO)TS7 MS_Class=31
Mass test: TS0(xOxOxOOO)TS7 MS_Class=32
Mass test: TS0(xOxOxOOO)TS7 MS_Class=33
Mass test: TS0(xOxOxOOO)TS7 MS_Class=34
Mass test: TS0(xOxOxOOO)TS7 MS_Class=35
Mass test: TS0(xOxOxOOO)TS7 MS_Class=36
Mass test: TS0(xOxOxOOO)TS7 MS_Class=37
Mass test: TS0(xOxOxOOO)TS7 MS_Class=38
Mass test: TS0(xOxOxOOO)TS7 MS_Class=39
Mass test: TS0(xOxOxOOO)TS7 MS_Class=40
Mass test: TS0(xOxOxOOO)TS7 MS_Class=41
Mass test: TS0(xOxOxOOO)TS7 MS_Class=42
Mass test: TS0(xOxOxOOO)TS7 MS_Class=43
Mass test: TS0(xOxOxOOO)TS7 MS_Class=44
Mass test: TS0(xOxOxOOO)TS7 MS_Class=45
Mass test: TS0(xOxOOxxx)TS7 MS_Class=0
Mass test: TS0(xOxOOxxx)TS7 MS_Class=1
Mass test: TS0(xOxOOxxx)TS7 MS_Class=2
Mass test: TS0(xOxOOxxx)TS7 MS_Class=3
Mass test: TS0(xOxOOxxx)TS7 MS_Class=4
Mass test: TS0(xOxOOxxx)TS7 MS_Class=5
Mass test: TS0(xOxOOxxx)TS7 MS_Class=6
Mass test: TS0(xOxOOxxx)TS7 MS_Class=7
Mass test: TS0(xOxOOxxx)TS7 MS_Class=8
Mass test: TS0(xOxOOxxx)TS7 MS_Class=9
Mass test: TS0(xOxOOxxx)TS7 MS_Class=10
Mass test: TS0(xOxOOxxx)TS7 MS_Class=11
Mass test: TS0(xOxOOxxx)TS7 MS_Class=12
Mass test: TS0(xOxOOxxx)TS7 MS_Class=13
Mass test: TS0(xOxOOxxx)TS7 MS_Class=14
Mass test: TS0(xOxOOxxx)TS7 MS_Class=15
Mass test: TS0(xOxOOxxx)TS7 MS_Class=16
Mass test: TS0(xOxOOxxx)TS7 MS_Class=17
Mass test: TS0(xOxOOxxx)TS7 MS_Class=18
Mass test: TS0(xOxOOxxx)TS7 MS_Class=19
Mass test: TS0(xOxOOxxx)TS7 MS_Class=20
Mass test: TS0(xOxOOxxx)TS7 MS_Class=21
Mass test: TS0(xOxOOxxx)TS7 MS_Class=22
Mass test: TS0(xOxOOxxx)TS7 MS_Class=23
Mass test: TS0(xOxOOxxx)TS7 MS_Class=24
Mass test: TS0(xOxOOxxx)TS7 MS_Class=25
Mass test: TS0(xOxOOxxx)TS7 MS_Class=26
Mass test: TS0(xOxOOxxx)TS7 MS_Class=27
Mass test: TS0(xOxOOxxx)TS7 MS_Class=28
Mass test: TS0(xOxOOxxx)TS7 MS_Class=29
Mass test: TS0(xOxOOxxx)TS7 MS_Class=30
Mass test: TS0(xOxOOxxx)TS7 MS_Class=31
Mass test: TS0(xOxOOxxx)TS7 MS_Class=32
Mass test: TS0(xOxOOxxx)TS7 MS_Class=33
Mass test: TS0(xOxOOxxx)TS7 MS_Class=34
Mass test: TS0(xOxOOxxx)TS7 MS_Class=35
Mass test: TS0(xOxOOxxx)TS7 MS_Class=36
Mass test: TS0(xOxOOxxx)TS7 MS_Class=37
Mass test: TS0(xOxOOxxx)TS7 MS_Class=38
Mass test: TS0(xOxOOxxx)TS7 MS_Class=39
Mass test: TS0(xOxOOxxx)TS7 MS_Class=40
Mass test: TS0(xOxOOxxx)TS7 MS_Class=41
Mass test: TS0(xOxOOxxx)TS7 MS_Class=42
Mass test: TS0(xOxOOxxx)TS7 MS_Class=43
Mass test: TS0(xOxOOxxx)TS7 MS_Class=44
Mass test: TS0(xOxOOxxx)TS7 MS_Class=45
Mass test: TS0(xOxOOxxO)TS7 MS_Class=0
Mass test: TS0(xOxOOxxO)TS7 MS_Class=1
Mass test: TS0(xOxOOxxO)TS7 MS_Class=2
Mass test: TS0(xOxOOxxO)TS7 MS_Class=3
Mass test: TS0(xOxOOxxO)TS7 MS_Class=4
Mass test: TS0(xOxOOxxO)TS7 MS_Class=5
Mass test: TS0(xOxOOxxO)TS7 MS_Class=6
Mass test: TS0(xOxOOxxO)TS7 MS_Class=7
Mass test: TS0(xOxOOxxO)TS7 MS_Class=8
Mass test: TS0(xOxOOxxO)TS7 MS_Class=9
Mass test: TS0(xOxOOxxO)TS7 MS_Class=10
Mass test: TS0(xOxOOxxO)TS7 MS_Class=11
Mass test: TS0(xOxOOxxO)TS7 MS_Class=12
Mass test: TS0(xOxOOxxO)TS7 MS_Class=13
Mass test: TS0(xOxOOxxO)TS7 MS_Class=14
Mass test: TS0(xOxOOxxO)TS7 MS_Class=15
Mass test: TS0(xOxOOxxO)TS7 MS_Class=16
Mass test: TS0(xOxOOxxO)TS7 MS_Class=17
Mass test: TS0(xOxOOxxO)TS7 MS_Class=18
Mass test: TS0(xOxOOxxO)TS7 MS_Class=19
Mass test: TS0(xOxOOxxO)TS7 MS_Class=20
Mass test: TS0(xOxOOxxO)TS7 MS_Class=21
Mass test: TS0(xOxOOxxO)TS7 MS_Class=22
Mass test: TS0(xOxOOxxO)TS7 MS_Class=23
Mass test: TS0(xOxOOxxO)TS7 MS_Class=24
Mass test: TS0(xOxOOxxO)TS7 MS_Class=25
Mass test: TS0(xOxOOxxO)TS7 MS_Class=26
Mass test: TS0(xOxOOxxO)TS7 MS_Class=27
Mass test: TS0(xOxOOxxO)TS7 MS_Class=28
Mass test: TS0(xOxOOxxO)TS7 MS_Class=29
Mass test: TS0(xOxOOxxO)TS7 MS_Class=30
Mass test: TS0(xOxOOxxO)TS7 MS_Class=31
Mass test: TS0(xOxOOxxO)TS7 MS_Class=32
Mass test: TS0(xOxOOxxO)TS7 MS_Class=33
Mass test: TS0(xOxOOxxO)TS7 MS_Class=34
Mass test: TS0(xOxOOxxO)TS7 MS_Class=35
Mass test: TS0(xOxOOxxO)TS7 MS_Class=36
Mass test: TS0(xOxOOxxO)TS7 MS_Class=37
Mass test: TS0(xOxOOxxO)TS7 MS_Class=38
Mass test: TS0(xOxOOxxO)TS7 MS_Class=39
Mass test: TS0(xOxOOxxO)TS7 MS_Class=40
Mass test: TS0(xOxOOxxO)TS7 MS_Class=41
Mass test: TS0(xOxOOxxO)TS7 MS_Class=42
Mass test: TS0(xOxOOxxO)TS7 MS_Class=43
Mass test: TS0(xOxOOxxO)TS7 MS_Class=44
Mass test: TS0(xOxOOxxO)TS7 MS_Class=45
Mass test: TS0(xOxOOxOx)TS7 MS_Class=0
Mass test: TS0(xOxOOxOx)TS7 MS_Class=1
Mass test: TS0(xOxOOxOx)TS7 MS_Class=2
Mass test: TS0(xOxOOxOx)TS7 MS_Class=3
Mass test: TS0(xOxOOxOx)TS7 MS_Class=4
Mass test: TS0(xOxOOxOx)TS7 MS_Class=5
Mass test: TS0(xOxOOxOx)TS7 MS_Class=6
Mass test: TS0(xOxOOxOx)TS7 MS_Class=7
Mass test: TS0(xOxOOxOx)TS7 MS_Class=8
Mass test: TS0(xOxOOxOx)TS7 MS_Class=9
Mass test: TS0(xOxOOxOx)TS7 MS_Class=10
Mass test: TS0(xOxOOxOx)TS7 MS_Class=11
Mass test: TS0(xOxOOxOx)TS7 MS_Class=12
Mass test: TS0(xOxOOxOx)TS7 MS_Class=13
Mass test: TS0(xOxOOxOx)TS7 MS_Class=14
Mass test: TS0(xOxOOxOx)TS7 MS_Class=15
Mass test: TS0(xOxOOxOx)TS7 MS_Class=16
Mass test: TS0(xOxOOxOx)TS7 MS_Class=17
Mass test: TS0(xOxOOxOx)TS7 MS_Class=18
Mass test: TS0(xOxOOxOx)TS7 MS_Class=19
Mass test: TS0(xOxOOxOx)TS7 MS_Class=20
Mass test: TS0(xOxOOxOx)TS7 MS_Class=21
Mass test: TS0(xOxOOxOx)TS7 MS_Class=22
Mass test: TS0(xOxOOxOx)TS7 MS_Class=23
Mass test: TS0(xOxOOxOx)TS7 MS_Class=24
Mass test: TS0(xOxOOxOx)TS7 MS_Class=25
Mass test: TS0(xOxOOxOx)TS7 MS_Class=26
Mass test: TS0(xOxOOxOx)TS7 MS_Class=27
Mass test: TS0(xOxOOxOx)TS7 MS_Class=28
Mass test: TS0(xOxOOxOx)TS7 MS_Class=29
Mass test: TS0(xOxOOxOx)TS7 MS_Class=30
Mass test: TS0(xOxOOxOx)TS7 MS_Class=31
Mass test: TS0(xOxOOxOx)TS7 MS_Class=32
Mass test: TS0(xOxOOxOx)TS7 MS_Class=33
Mass test: TS0(xOxOOxOx)TS7 MS_Class=34
Mass test: TS0(xOxOOxOx)TS7 MS_Class=35
Mass test: TS0(xOxOOxOx)TS7 MS_Class=36
Mass test: TS0(xOxOOxOx)TS7 MS_Class=37
Mass test: TS0(xOxOOxOx)TS7 MS_Class=38
Mass test: TS0(xOxOOxOx)TS7 MS_Class=39
Mass test: TS0(xOxOOxOx)TS7 MS_Class=40
Mass test: TS0(xOxOOxOx)TS7 MS_Class=41
Mass test: TS0(xOxOOxOx)TS7 MS_Class=42
Mass test: TS0(xOxOOxOx)TS7 MS_Class=43
Mass test: TS0(xOxOOxOx)TS7 MS_Class=44
Mass test: TS0(xOxOOxOx)TS7 MS_Class=45
Mass test: TS0(xOxOOxOO)TS7 MS_Class=0
Mass test: TS0(xOxOOxOO)TS7 MS_Class=1
Mass test: TS0(xOxOOxOO)TS7 MS_Class=2
Mass test: TS0(xOxOOxOO)TS7 MS_Class=3
Mass test: TS0(xOxOOxOO)TS7 MS_Class=4
Mass test: TS0(xOxOOxOO)TS7 MS_Class=5
Mass test: TS0(xOxOOxOO)TS7 MS_Class=6
Mass test: TS0(xOxOOxOO)TS7 MS_Class=7
Mass test: TS0(xOxOOxOO)TS7 MS_Class=8
Mass test: TS0(xOxOOxOO)TS7 MS_Class=9
Mass test: TS0(xOxOOxOO)TS7 MS_Class=10
Mass test: TS0(xOxOOxOO)TS7 MS_Class=11
Mass test: TS0(xOxOOxOO)TS7 MS_Class=12
Mass test: TS0(xOxOOxOO)TS7 MS_Class=13
Mass test: TS0(xOxOOxOO)TS7 MS_Class=14
Mass test: TS0(xOxOOxOO)TS7 MS_Class=15
Mass test: TS0(xOxOOxOO)TS7 MS_Class=16
Mass test: TS0(xOxOOxOO)TS7 MS_Class=17
Mass test: TS0(xOxOOxOO)TS7 MS_Class=18
Mass test: TS0(xOxOOxOO)TS7 MS_Class=19
Mass test: TS0(xOxOOxOO)TS7 MS_Class=20
Mass test: TS0(xOxOOxOO)TS7 MS_Class=21
Mass test: TS0(xOxOOxOO)TS7 MS_Class=22
Mass test: TS0(xOxOOxOO)TS7 MS_Class=23
Mass test: TS0(xOxOOxOO)TS7 MS_Class=24
Mass test: TS0(xOxOOxOO)TS7 MS_Class=25
Mass test: TS0(xOxOOxOO)TS7 MS_Class=26
Mass test: TS0(xOxOOxOO)TS7 MS_Class=27
Mass test: TS0(xOxOOxOO)TS7 MS_Class=28
Mass test: TS0(xOxOOxOO)TS7 MS_Class=29
Mass test: TS0(xOxOOxOO)TS7 MS_Class=30
Mass test: TS0(xOxOOxOO)TS7 MS_Class=31
Mass test: TS0(xOxOOxOO)TS7 MS_Class=32
Mass test: TS0(xOxOOxOO)TS7 MS_Class=33
Mass test: TS0(xOxOOxOO)TS7 MS_Class=34
Mass test: TS0(xOxOOxOO)TS7 MS_Class=35
Mass test: TS0(xOxOOxOO)TS7 MS_Class=36
Mass test: TS0(xOxOOxOO)TS7 MS_Class=37
Mass test: TS0(xOxOOxOO)TS7 MS_Class=38
Mass test: TS0(xOxOOxOO)TS7 MS_Class=39
Mass test: TS0(xOxOOxOO)TS7 MS_Class=40
Mass test: TS0(xOxOOxOO)TS7 MS_Class=41
Mass test: TS0(xOxOOxOO)TS7 MS_Class=42
Mass test: TS0(xOxOOxOO)TS7 MS_Class=43
Mass test: TS0(xOxOOxOO)TS7 MS_Class=44
Mass test: TS0(xOxOOxOO)TS7 MS_Class=45
Mass test: TS0(xOxOOOxx)TS7 MS_Class=0
Mass test: TS0(xOxOOOxx)TS7 MS_Class=1
Mass test: TS0(xOxOOOxx)TS7 MS_Class=2
Mass test: TS0(xOxOOOxx)TS7 MS_Class=3
Mass test: TS0(xOxOOOxx)TS7 MS_Class=4
Mass test: TS0(xOxOOOxx)TS7 MS_Class=5
Mass test: TS0(xOxOOOxx)TS7 MS_Class=6
Mass test: TS0(xOxOOOxx)TS7 MS_Class=7
Mass test: TS0(xOxOOOxx)TS7 MS_Class=8
Mass test: TS0(xOxOOOxx)TS7 MS_Class=9
Mass test: TS0(xOxOOOxx)TS7 MS_Class=10
Mass test: TS0(xOxOOOxx)TS7 MS_Class=11
Mass test: TS0(xOxOOOxx)TS7 MS_Class=12
Mass test: TS0(xOxOOOxx)TS7 MS_Class=13
Mass test: TS0(xOxOOOxx)TS7 MS_Class=14
Mass test: TS0(xOxOOOxx)TS7 MS_Class=15
Mass test: TS0(xOxOOOxx)TS7 MS_Class=16
Mass test: TS0(xOxOOOxx)TS7 MS_Class=17
Mass test: TS0(xOxOOOxx)TS7 MS_Class=18
Mass test: TS0(xOxOOOxx)TS7 MS_Class=19
Mass test: TS0(xOxOOOxx)TS7 MS_Class=20
Mass test: TS0(xOxOOOxx)TS7 MS_Class=21
Mass test: TS0(xOxOOOxx)TS7 MS_Class=22
Mass test: TS0(xOxOOOxx)TS7 MS_Class=23
Mass test: TS0(xOxOOOxx)TS7 MS_Class=24
Mass test: TS0(xOxOOOxx)TS7 MS_Class=25
Mass test: TS0(xOxOOOxx)TS7 MS_Class=26
Mass test: TS0(xOxOOOxx)TS7 MS_Class=27
Mass test: TS0(xOxOOOxx)TS7 MS_Class=28
Mass test: TS0(xOxOOOxx)TS7 MS_Class=29
Mass test: TS0(xOxOOOxx)TS7 MS_Class=30
Mass test: TS0(xOxOOOxx)TS7 MS_Class=31
Mass test: TS0(xOxOOOxx)TS7 MS_Class=32
Mass test: TS0(xOxOOOxx)TS7 MS_Class=33
Mass test: TS0(xOxOOOxx)TS7 MS_Class=34
Mass test: TS0(xOxOOOxx)TS7 MS_Class=35
Mass test: TS0(xOxOOOxx)TS7 MS_Class=36
Mass test: TS0(xOxOOOxx)TS7 MS_Class=37
Mass test: TS0(xOxOOOxx)TS7 MS_Class=38
Mass test: TS0(xOxOOOxx)TS7 MS_Class=39
Mass test: TS0(xOxOOOxx)TS7 MS_Class=40
Mass test: TS0(xOxOOOxx)TS7 MS_Class=41
Mass test: TS0(xOxOOOxx)TS7 MS_Class=42
Mass test: TS0(xOxOOOxx)TS7 MS_Class=43
Mass test: TS0(xOxOOOxx)TS7 MS_Class=44
Mass test: TS0(xOxOOOxx)TS7 MS_Class=45
Mass test: TS0(xOxOOOxO)TS7 MS_Class=0
Mass test: TS0(xOxOOOxO)TS7 MS_Class=1
Mass test: TS0(xOxOOOxO)TS7 MS_Class=2
Mass test: TS0(xOxOOOxO)TS7 MS_Class=3
Mass test: TS0(xOxOOOxO)TS7 MS_Class=4
Mass test: TS0(xOxOOOxO)TS7 MS_Class=5
Mass test: TS0(xOxOOOxO)TS7 MS_Class=6
Mass test: TS0(xOxOOOxO)TS7 MS_Class=7
Mass test: TS0(xOxOOOxO)TS7 MS_Class=8
Mass test: TS0(xOxOOOxO)TS7 MS_Class=9
Mass test: TS0(xOxOOOxO)TS7 MS_Class=10
Mass test: TS0(xOxOOOxO)TS7 MS_Class=11
Mass test: TS0(xOxOOOxO)TS7 MS_Class=12
Mass test: TS0(xOxOOOxO)TS7 MS_Class=13
Mass test: TS0(xOxOOOxO)TS7 MS_Class=14
Mass test: TS0(xOxOOOxO)TS7 MS_Class=15
Mass test: TS0(xOxOOOxO)TS7 MS_Class=16
Mass test: TS0(xOxOOOxO)TS7 MS_Class=17
Mass test: TS0(xOxOOOxO)TS7 MS_Class=18
Mass test: TS0(xOxOOOxO)TS7 MS_Class=19
Mass test: TS0(xOxOOOxO)TS7 MS_Class=20
Mass test: TS0(xOxOOOxO)TS7 MS_Class=21
Mass test: TS0(xOxOOOxO)TS7 MS_Class=22
Mass test: TS0(xOxOOOxO)TS7 MS_Class=23
Mass test: TS0(xOxOOOxO)TS7 MS_Class=24
Mass test: TS0(xOxOOOxO)TS7 MS_Class=25
Mass test: TS0(xOxOOOxO)TS7 MS_Class=26
Mass test: TS0(xOxOOOxO)TS7 MS_Class=27
Mass test: TS0(xOxOOOxO)TS7 MS_Class=28
Mass test: TS0(xOxOOOxO)TS7 MS_Class=29
Mass test: TS0(xOxOOOxO)TS7 MS_Class=30
Mass test: TS0(xOxOOOxO)TS7 MS_Class=31
Mass test: TS0(xOxOOOxO)TS7 MS_Class=32
Mass test: TS0(xOxOOOxO)TS7 MS_Class=33
Mass test: TS0(xOxOOOxO)TS7 MS_Class=34
Mass test: TS0(xOxOOOxO)TS7 MS_Class=35
Mass test: TS0(xOxOOOxO)TS7 MS_Class=36
Mass test: TS0(xOxOOOxO)TS7 MS_Class=37
Mass test: TS0(xOxOOOxO)TS7 MS_Class=38
Mass test: TS0(xOxOOOxO)TS7 MS_Class=39
Mass test: TS0(xOxOOOxO)TS7 MS_Class=40
Mass test: TS0(xOxOOOxO)TS7 MS_Class=41
Mass test: TS0(xOxOOOxO)TS7 MS_Class=42
Mass test: TS0(xOxOOOxO)TS7 MS_Class=43
Mass test: TS0(xOxOOOxO)TS7 MS_Class=44
Mass test: TS0(xOxOOOxO)TS7 MS_Class=45
Mass test: TS0(xOxOOOOx)TS7 MS_Class=0
Mass test: TS0(xOxOOOOx)TS7 MS_Class=1
Mass test: TS0(xOxOOOOx)TS7 MS_Class=2
Mass test: TS0(xOxOOOOx)TS7 MS_Class=3
Mass test: TS0(xOxOOOOx)TS7 MS_Class=4
Mass test: TS0(xOxOOOOx)TS7 MS_Class=5
Mass test: TS0(xOxOOOOx)TS7 MS_Class=6
Mass test: TS0(xOxOOOOx)TS7 MS_Class=7
Mass test: TS0(xOxOOOOx)TS7 MS_Class=8
Mass test: TS0(xOxOOOOx)TS7 MS_Class=9
Mass test: TS0(xOxOOOOx)TS7 MS_Class=10
Mass test: TS0(xOxOOOOx)TS7 MS_Class=11
Mass test: TS0(xOxOOOOx)TS7 MS_Class=12
Mass test: TS0(xOxOOOOx)TS7 MS_Class=13
Mass test: TS0(xOxOOOOx)TS7 MS_Class=14
Mass test: TS0(xOxOOOOx)TS7 MS_Class=15
Mass test: TS0(xOxOOOOx)TS7 MS_Class=16
Mass test: TS0(xOxOOOOx)TS7 MS_Class=17
Mass test: TS0(xOxOOOOx)TS7 MS_Class=18
Mass test: TS0(xOxOOOOx)TS7 MS_Class=19
Mass test: TS0(xOxOOOOx)TS7 MS_Class=20
Mass test: TS0(xOxOOOOx)TS7 MS_Class=21
Mass test: TS0(xOxOOOOx)TS7 MS_Class=22
Mass test: TS0(xOxOOOOx)TS7 MS_Class=23
Mass test: TS0(xOxOOOOx)TS7 MS_Class=24
Mass test: TS0(xOxOOOOx)TS7 MS_Class=25
Mass test: TS0(xOxOOOOx)TS7 MS_Class=26
Mass test: TS0(xOxOOOOx)TS7 MS_Class=27
Mass test: TS0(xOxOOOOx)TS7 MS_Class=28
Mass test: TS0(xOxOOOOx)TS7 MS_Class=29
Mass test: TS0(xOxOOOOx)TS7 MS_Class=30
Mass test: TS0(xOxOOOOx)TS7 MS_Class=31
Mass test: TS0(xOxOOOOx)TS7 MS_Class=32
Mass test: TS0(xOxOOOOx)TS7 MS_Class=33
Mass test: TS0(xOxOOOOx)TS7 MS_Class=34
Mass test: TS0(xOxOOOOx)TS7 MS_Class=35
Mass test: TS0(xOxOOOOx)TS7 MS_Class=36
Mass test: TS0(xOxOOOOx)TS7 MS_Class=37
Mass test: TS0(xOxOOOOx)TS7 MS_Class=38
Mass test: TS0(xOxOOOOx)TS7 MS_Class=39
Mass test: TS0(xOxOOOOx)TS7 MS_Class=40
Mass test: TS0(xOxOOOOx)TS7 MS_Class=41
Mass test: TS0(xOxOOOOx)TS7 MS_Class=42
Mass test: TS0(xOxOOOOx)TS7 MS_Class=43
Mass test: TS0(xOxOOOOx)TS7 MS_Class=44
Mass test: TS0(xOxOOOOx)TS7 MS_Class=45
Mass test: TS0(xOxOOOOO)TS7 MS_Class=0
Mass test: TS0(xOxOOOOO)TS7 MS_Class=1
Mass test: TS0(xOxOOOOO)TS7 MS_Class=2
Mass test: TS0(xOxOOOOO)TS7 MS_Class=3
Mass test: TS0(xOxOOOOO)TS7 MS_Class=4
Mass test: TS0(xOxOOOOO)TS7 MS_Class=5
Mass test: TS0(xOxOOOOO)TS7 MS_Class=6
Mass test: TS0(xOxOOOOO)TS7 MS_Class=7
Mass test: TS0(xOxOOOOO)TS7 MS_Class=8
Mass test: TS0(xOxOOOOO)TS7 MS_Class=9
Mass test: TS0(xOxOOOOO)TS7 MS_Class=10
Mass test: TS0(xOxOOOOO)TS7 MS_Class=11
Mass test: TS0(xOxOOOOO)TS7 MS_Class=12
Mass test: TS0(xOxOOOOO)TS7 MS_Class=13
Mass test: TS0(xOxOOOOO)TS7 MS_Class=14
Mass test: TS0(xOxOOOOO)TS7 MS_Class=15
Mass test: TS0(xOxOOOOO)TS7 MS_Class=16
Mass test: TS0(xOxOOOOO)TS7 MS_Class=17
Mass test: TS0(xOxOOOOO)TS7 MS_Class=18
Mass test: TS0(xOxOOOOO)TS7 MS_Class=19
Mass test: TS0(xOxOOOOO)TS7 MS_Class=20
Mass test: TS0(xOxOOOOO)TS7 MS_Class=21
Mass test: TS0(xOxOOOOO)TS7 MS_Class=22
Mass test: TS0(xOxOOOOO)TS7 MS_Class=23
Mass test: TS0(xOxOOOOO)TS7 MS_Class=24
Mass test: TS0(xOxOOOOO)TS7 MS_Class=25
Mass test: TS0(xOxOOOOO)TS7 MS_Class=26
Mass test: TS0(xOxOOOOO)TS7 MS_Class=27
Mass test: TS0(xOxOOOOO)TS7 MS_Class=28
Mass test: TS0(xOxOOOOO)TS7 MS_Class=29
Mass test: TS0(xOxOOOOO)TS7 MS_Class=30
Mass test: TS0(xOxOOOOO)TS7 MS_Class=31
Mass test: TS0(xOxOOOOO)TS7 MS_Class=32
Mass test: TS0(xOxOOOOO)TS7 MS_Class=33
Mass test: TS0(xOxOOOOO)TS7 MS_Class=34
Mass test: TS0(xOxOOOOO)TS7 MS_Class=35
Mass test: TS0(xOxOOOOO)TS7 MS_Class=36
Mass test: TS0(xOxOOOOO)TS7 MS_Class=37
Mass test: TS0(xOxOOOOO)TS7 MS_Class=38
Mass test: TS0(xOxOOOOO)TS7 MS_Class=39
Mass test: TS0(xOxOOOOO)TS7 MS_Class=40
Mass test: TS0(xOxOOOOO)TS7 MS_Class=41
Mass test: TS0(xOxOOOOO)TS7 MS_Class=42
Mass test: TS0(xOxOOOOO)TS7 MS_Class=43
Mass test: TS0(xOxOOOOO)TS7 MS_Class=44
Mass test: TS0(xOxOOOOO)TS7 MS_Class=45
Mass test: TS0(xOOxxxxx)TS7 MS_Class=0
Mass test: TS0(xOOxxxxx)TS7 MS_Class=1
Mass test: TS0(xOOxxxxx)TS7 MS_Class=2
Mass test: TS0(xOOxxxxx)TS7 MS_Class=3
Mass test: TS0(xOOxxxxx)TS7 MS_Class=4
Mass test: TS0(xOOxxxxx)TS7 MS_Class=5
Mass test: TS0(xOOxxxxx)TS7 MS_Class=6
Mass test: TS0(xOOxxxxx)TS7 MS_Class=7
Mass test: TS0(xOOxxxxx)TS7 MS_Class=8
Mass test: TS0(xOOxxxxx)TS7 MS_Class=9
Mass test: TS0(xOOxxxxx)TS7 MS_Class=10
Mass test: TS0(xOOxxxxx)TS7 MS_Class=11
Mass test: TS0(xOOxxxxx)TS7 MS_Class=12
Mass test: TS0(xOOxxxxx)TS7 MS_Class=13
Mass test: TS0(xOOxxxxx)TS7 MS_Class=14
Mass test: TS0(xOOxxxxx)TS7 MS_Class=15
Mass test: TS0(xOOxxxxx)TS7 MS_Class=16
Mass test: TS0(xOOxxxxx)TS7 MS_Class=17
Mass test: TS0(xOOxxxxx)TS7 MS_Class=18
Mass test: TS0(xOOxxxxx)TS7 MS_Class=19
Mass test: TS0(xOOxxxxx)TS7 MS_Class=20
Mass test: TS0(xOOxxxxx)TS7 MS_Class=21
Mass test: TS0(xOOxxxxx)TS7 MS_Class=22
Mass test: TS0(xOOxxxxx)TS7 MS_Class=23
Mass test: TS0(xOOxxxxx)TS7 MS_Class=24
Mass test: TS0(xOOxxxxx)TS7 MS_Class=25
Mass test: TS0(xOOxxxxx)TS7 MS_Class=26
Mass test: TS0(xOOxxxxx)TS7 MS_Class=27
Mass test: TS0(xOOxxxxx)TS7 MS_Class=28
Mass test: TS0(xOOxxxxx)TS7 MS_Class=29
Mass test: TS0(xOOxxxxx)TS7 MS_Class=30
Mass test: TS0(xOOxxxxx)TS7 MS_Class=31
Mass test: TS0(xOOxxxxx)TS7 MS_Class=32
Mass test: TS0(xOOxxxxx)TS7 MS_Class=33
Mass test: TS0(xOOxxxxx)TS7 MS_Class=34
Mass test: TS0(xOOxxxxx)TS7 MS_Class=35
Mass test: TS0(xOOxxxxx)TS7 MS_Class=36
Mass test: TS0(xOOxxxxx)TS7 MS_Class=37
Mass test: TS0(xOOxxxxx)TS7 MS_Class=38
Mass test: TS0(xOOxxxxx)TS7 MS_Class=39
Mass test: TS0(xOOxxxxx)TS7 MS_Class=40
Mass test: TS0(xOOxxxxx)TS7 MS_Class=41
Mass test: TS0(xOOxxxxx)TS7 MS_Class=42
Mass test: TS0(xOOxxxxx)TS7 MS_Class=43
Mass test: TS0(xOOxxxxx)TS7 MS_Class=44
Mass test: TS0(xOOxxxxx)TS7 MS_Class=45
Mass test: TS0(xOOxxxxO)TS7 MS_Class=0
Mass test: TS0(xOOxxxxO)TS7 MS_Class=1
Mass test: TS0(xOOxxxxO)TS7 MS_Class=2
Mass test: TS0(xOOxxxxO)TS7 MS_Class=3
Mass test: TS0(xOOxxxxO)TS7 MS_Class=4
Mass test: TS0(xOOxxxxO)TS7 MS_Class=5
Mass test: TS0(xOOxxxxO)TS7 MS_Class=6
Mass test: TS0(xOOxxxxO)TS7 MS_Class=7
Mass test: TS0(xOOxxxxO)TS7 MS_Class=8
Mass test: TS0(xOOxxxxO)TS7 MS_Class=9
Mass test: TS0(xOOxxxxO)TS7 MS_Class=10
Mass test: TS0(xOOxxxxO)TS7 MS_Class=11
Mass test: TS0(xOOxxxxO)TS7 MS_Class=12
Mass test: TS0(xOOxxxxO)TS7 MS_Class=13
Mass test: TS0(xOOxxxxO)TS7 MS_Class=14
Mass test: TS0(xOOxxxxO)TS7 MS_Class=15
Mass test: TS0(xOOxxxxO)TS7 MS_Class=16
Mass test: TS0(xOOxxxxO)TS7 MS_Class=17
Mass test: TS0(xOOxxxxO)TS7 MS_Class=18
Mass test: TS0(xOOxxxxO)TS7 MS_Class=19
Mass test: TS0(xOOxxxxO)TS7 MS_Class=20
Mass test: TS0(xOOxxxxO)TS7 MS_Class=21
Mass test: TS0(xOOxxxxO)TS7 MS_Class=22
Mass test: TS0(xOOxxxxO)TS7 MS_Class=23
Mass test: TS0(xOOxxxxO)TS7 MS_Class=24
Mass test: TS0(xOOxxxxO)TS7 MS_Class=25
Mass test: TS0(xOOxxxxO)TS7 MS_Class=26
Mass test: TS0(xOOxxxxO)TS7 MS_Class=27
Mass test: TS0(xOOxxxxO)TS7 MS_Class=28
Mass test: TS0(xOOxxxxO)TS7 MS_Class=29
Mass test: TS0(xOOxxxxO)TS7 MS_Class=30
Mass test: TS0(xOOxxxxO)TS7 MS_Class=31
Mass test: TS0(xOOxxxxO)TS7 MS_Class=32
Mass test: TS0(xOOxxxxO)TS7 MS_Class=33
Mass test: TS0(xOOxxxxO)TS7 MS_Class=34
Mass test: TS0(xOOxxxxO)TS7 MS_Class=35
Mass test: TS0(xOOxxxxO)TS7 MS_Class=36
Mass test: TS0(xOOxxxxO)TS7 MS_Class=37
Mass test: TS0(xOOxxxxO)TS7 MS_Class=38
Mass test: TS0(xOOxxxxO)TS7 MS_Class=39
Mass test: TS0(xOOxxxxO)TS7 MS_Class=40
Mass test: TS0(xOOxxxxO)TS7 MS_Class=41
Mass test: TS0(xOOxxxxO)TS7 MS_Class=42
Mass test: TS0(xOOxxxxO)TS7 MS_Class=43
Mass test: TS0(xOOxxxxO)TS7 MS_Class=44
Mass test: TS0(xOOxxxxO)TS7 MS_Class=45
Mass test: TS0(xOOxxxOx)TS7 MS_Class=0
Mass test: TS0(xOOxxxOx)TS7 MS_Class=1
Mass test: TS0(xOOxxxOx)TS7 MS_Class=2
Mass test: TS0(xOOxxxOx)TS7 MS_Class=3
Mass test: TS0(xOOxxxOx)TS7 MS_Class=4
Mass test: TS0(xOOxxxOx)TS7 MS_Class=5
Mass test: TS0(xOOxxxOx)TS7 MS_Class=6
Mass test: TS0(xOOxxxOx)TS7 MS_Class=7
Mass test: TS0(xOOxxxOx)TS7 MS_Class=8
Mass test: TS0(xOOxxxOx)TS7 MS_Class=9
Mass test: TS0(xOOxxxOx)TS7 MS_Class=10
Mass test: TS0(xOOxxxOx)TS7 MS_Class=11
Mass test: TS0(xOOxxxOx)TS7 MS_Class=12
Mass test: TS0(xOOxxxOx)TS7 MS_Class=13
Mass test: TS0(xOOxxxOx)TS7 MS_Class=14
Mass test: TS0(xOOxxxOx)TS7 MS_Class=15
Mass test: TS0(xOOxxxOx)TS7 MS_Class=16
Mass test: TS0(xOOxxxOx)TS7 MS_Class=17
Mass test: TS0(xOOxxxOx)TS7 MS_Class=18
Mass test: TS0(xOOxxxOx)TS7 MS_Class=19
Mass test: TS0(xOOxxxOx)TS7 MS_Class=20
Mass test: TS0(xOOxxxOx)TS7 MS_Class=21
Mass test: TS0(xOOxxxOx)TS7 MS_Class=22
Mass test: TS0(xOOxxxOx)TS7 MS_Class=23
Mass test: TS0(xOOxxxOx)TS7 MS_Class=24
Mass test: TS0(xOOxxxOx)TS7 MS_Class=25
Mass test: TS0(xOOxxxOx)TS7 MS_Class=26
Mass test: TS0(xOOxxxOx)TS7 MS_Class=27
Mass test: TS0(xOOxxxOx)TS7 MS_Class=28
Mass test: TS0(xOOxxxOx)TS7 MS_Class=29
Mass test: TS0(xOOxxxOx)TS7 MS_Class=30
Mass test: TS0(xOOxxxOx)TS7 MS_Class=31
Mass test: TS0(xOOxxxOx)TS7 MS_Class=32
Mass test: TS0(xOOxxxOx)TS7 MS_Class=33
Mass test: TS0(xOOxxxOx)TS7 MS_Class=34
Mass test: TS0(xOOxxxOx)TS7 MS_Class=35
Mass test: TS0(xOOxxxOx)TS7 MS_Class=36
Mass test: TS0(xOOxxxOx)TS7 MS_Class=37
Mass test: TS0(xOOxxxOx)TS7 MS_Class=38
Mass test: TS0(xOOxxxOx)TS7 MS_Class=39
Mass test: TS0(xOOxxxOx)TS7 MS_Class=40
Mass test: TS0(xOOxxxOx)TS7 MS_Class=41
Mass test: TS0(xOOxxxOx)TS7 MS_Class=42
Mass test: TS0(xOOxxxOx)TS7 MS_Class=43
Mass test: TS0(xOOxxxOx)TS7 MS_Class=44
Mass test: TS0(xOOxxxOx)TS7 MS_Class=45
Mass test: TS0(xOOxxxOO)TS7 MS_Class=0
Mass test: TS0(xOOxxxOO)TS7 MS_Class=1
Mass test: TS0(xOOxxxOO)TS7 MS_Class=2
Mass test: TS0(xOOxxxOO)TS7 MS_Class=3
Mass test: TS0(xOOxxxOO)TS7 MS_Class=4
Mass test: TS0(xOOxxxOO)TS7 MS_Class=5
Mass test: TS0(xOOxxxOO)TS7 MS_Class=6
Mass test: TS0(xOOxxxOO)TS7 MS_Class=7
Mass test: TS0(xOOxxxOO)TS7 MS_Class=8
Mass test: TS0(xOOxxxOO)TS7 MS_Class=9
Mass test: TS0(xOOxxxOO)TS7 MS_Class=10
Mass test: TS0(xOOxxxOO)TS7 MS_Class=11
Mass test: TS0(xOOxxxOO)TS7 MS_Class=12
Mass test: TS0(xOOxxxOO)TS7 MS_Class=13
Mass test: TS0(xOOxxxOO)TS7 MS_Class=14
Mass test: TS0(xOOxxxOO)TS7 MS_Class=15
Mass test: TS0(xOOxxxOO)TS7 MS_Class=16
Mass test: TS0(xOOxxxOO)TS7 MS_Class=17
Mass test: TS0(xOOxxxOO)TS7 MS_Class=18
Mass test: TS0(xOOxxxOO)TS7 MS_Class=19
Mass test: TS0(xOOxxxOO)TS7 MS_Class=20
Mass test: TS0(xOOxxxOO)TS7 MS_Class=21
Mass test: TS0(xOOxxxOO)TS7 MS_Class=22
Mass test: TS0(xOOxxxOO)TS7 MS_Class=23
Mass test: TS0(xOOxxxOO)TS7 MS_Class=24
Mass test: TS0(xOOxxxOO)TS7 MS_Class=25
Mass test: TS0(xOOxxxOO)TS7 MS_Class=26
Mass test: TS0(xOOxxxOO)TS7 MS_Class=27
Mass test: TS0(xOOxxxOO)TS7 MS_Class=28
Mass test: TS0(xOOxxxOO)TS7 MS_Class=29
Mass test: TS0(xOOxxxOO)TS7 MS_Class=30
Mass test: TS0(xOOxxxOO)TS7 MS_Class=31
Mass test: TS0(xOOxxxOO)TS7 MS_Class=32
Mass test: TS0(xOOxxxOO)TS7 MS_Class=33
Mass test: TS0(xOOxxxOO)TS7 MS_Class=34
Mass test: TS0(xOOxxxOO)TS7 MS_Class=35
Mass test: TS0(xOOxxxOO)TS7 MS_Class=36
Mass test: TS0(xOOxxxOO)TS7 MS_Class=37
Mass test: TS0(xOOxxxOO)TS7 MS_Class=38
Mass test: TS0(xOOxxxOO)TS7 MS_Class=39
Mass test: TS0(xOOxxxOO)TS7 MS_Class=40
Mass test: TS0(xOOxxxOO)TS7 MS_Class=41
Mass test: TS0(xOOxxxOO)TS7 MS_Class=42
Mass test: TS0(xOOxxxOO)TS7 MS_Class=43
Mass test: TS0(xOOxxxOO)TS7 MS_Class=44
Mass test: TS0(xOOxxxOO)TS7 MS_Class=45
Mass test: TS0(xOOxxOxx)TS7 MS_Class=0
Mass test: TS0(xOOxxOxx)TS7 MS_Class=1
Mass test: TS0(xOOxxOxx)TS7 MS_Class=2
Mass test: TS0(xOOxxOxx)TS7 MS_Class=3
Mass test: TS0(xOOxxOxx)TS7 MS_Class=4
Mass test: TS0(xOOxxOxx)TS7 MS_Class=5
Mass test: TS0(xOOxxOxx)TS7 MS_Class=6
Mass test: TS0(xOOxxOxx)TS7 MS_Class=7
Mass test: TS0(xOOxxOxx)TS7 MS_Class=8
Mass test: TS0(xOOxxOxx)TS7 MS_Class=9
Mass test: TS0(xOOxxOxx)TS7 MS_Class=10
Mass test: TS0(xOOxxOxx)TS7 MS_Class=11
Mass test: TS0(xOOxxOxx)TS7 MS_Class=12
Mass test: TS0(xOOxxOxx)TS7 MS_Class=13
Mass test: TS0(xOOxxOxx)TS7 MS_Class=14
Mass test: TS0(xOOxxOxx)TS7 MS_Class=15
Mass test: TS0(xOOxxOxx)TS7 MS_Class=16
Mass test: TS0(xOOxxOxx)TS7 MS_Class=17
Mass test: TS0(xOOxxOxx)TS7 MS_Class=18
Mass test: TS0(xOOxxOxx)TS7 MS_Class=19
Mass test: TS0(xOOxxOxx)TS7 MS_Class=20
Mass test: TS0(xOOxxOxx)TS7 MS_Class=21
Mass test: TS0(xOOxxOxx)TS7 MS_Class=22
Mass test: TS0(xOOxxOxx)TS7 MS_Class=23
Mass test: TS0(xOOxxOxx)TS7 MS_Class=24
Mass test: TS0(xOOxxOxx)TS7 MS_Class=25
Mass test: TS0(xOOxxOxx)TS7 MS_Class=26
Mass test: TS0(xOOxxOxx)TS7 MS_Class=27
Mass test: TS0(xOOxxOxx)TS7 MS_Class=28
Mass test: TS0(xOOxxOxx)TS7 MS_Class=29
Mass test: TS0(xOOxxOxx)TS7 MS_Class=30
Mass test: TS0(xOOxxOxx)TS7 MS_Class=31
Mass test: TS0(xOOxxOxx)TS7 MS_Class=32
Mass test: TS0(xOOxxOxx)TS7 MS_Class=33
Mass test: TS0(xOOxxOxx)TS7 MS_Class=34
Mass test: TS0(xOOxxOxx)TS7 MS_Class=35
Mass test: TS0(xOOxxOxx)TS7 MS_Class=36
Mass test: TS0(xOOxxOxx)TS7 MS_Class=37
Mass test: TS0(xOOxxOxx)TS7 MS_Class=38
Mass test: TS0(xOOxxOxx)TS7 MS_Class=39
Mass test: TS0(xOOxxOxx)TS7 MS_Class=40
Mass test: TS0(xOOxxOxx)TS7 MS_Class=41
Mass test: TS0(xOOxxOxx)TS7 MS_Class=42
Mass test: TS0(xOOxxOxx)TS7 MS_Class=43
Mass test: TS0(xOOxxOxx)TS7 MS_Class=44
Mass test: TS0(xOOxxOxx)TS7 MS_Class=45
Mass test: TS0(xOOxxOxO)TS7 MS_Class=0
Mass test: TS0(xOOxxOxO)TS7 MS_Class=1
Mass test: TS0(xOOxxOxO)TS7 MS_Class=2
Mass test: TS0(xOOxxOxO)TS7 MS_Class=3
Mass test: TS0(xOOxxOxO)TS7 MS_Class=4
Mass test: TS0(xOOxxOxO)TS7 MS_Class=5
Mass test: TS0(xOOxxOxO)TS7 MS_Class=6
Mass test: TS0(xOOxxOxO)TS7 MS_Class=7
Mass test: TS0(xOOxxOxO)TS7 MS_Class=8
Mass test: TS0(xOOxxOxO)TS7 MS_Class=9
Mass test: TS0(xOOxxOxO)TS7 MS_Class=10
Mass test: TS0(xOOxxOxO)TS7 MS_Class=11
Mass test: TS0(xOOxxOxO)TS7 MS_Class=12
Mass test: TS0(xOOxxOxO)TS7 MS_Class=13
Mass test: TS0(xOOxxOxO)TS7 MS_Class=14
Mass test: TS0(xOOxxOxO)TS7 MS_Class=15
Mass test: TS0(xOOxxOxO)TS7 MS_Class=16
Mass test: TS0(xOOxxOxO)TS7 MS_Class=17
Mass test: TS0(xOOxxOxO)TS7 MS_Class=18
Mass test: TS0(xOOxxOxO)TS7 MS_Class=19
Mass test: TS0(xOOxxOxO)TS7 MS_Class=20
Mass test: TS0(xOOxxOxO)TS7 MS_Class=21
Mass test: TS0(xOOxxOxO)TS7 MS_Class=22
Mass test: TS0(xOOxxOxO)TS7 MS_Class=23
Mass test: TS0(xOOxxOxO)TS7 MS_Class=24
Mass test: TS0(xOOxxOxO)TS7 MS_Class=25
Mass test: TS0(xOOxxOxO)TS7 MS_Class=26
Mass test: TS0(xOOxxOxO)TS7 MS_Class=27
Mass test: TS0(xOOxxOxO)TS7 MS_Class=28
Mass test: TS0(xOOxxOxO)TS7 MS_Class=29
Mass test: TS0(xOOxxOxO)TS7 MS_Class=30
Mass test: TS0(xOOxxOxO)TS7 MS_Class=31
Mass test: TS0(xOOxxOxO)TS7 MS_Class=32
Mass test: TS0(xOOxxOxO)TS7 MS_Class=33
Mass test: TS0(xOOxxOxO)TS7 MS_Class=34
Mass test: TS0(xOOxxOxO)TS7 MS_Class=35
Mass test: TS0(xOOxxOxO)TS7 MS_Class=36
Mass test: TS0(xOOxxOxO)TS7 MS_Class=37
Mass test: TS0(xOOxxOxO)TS7 MS_Class=38
Mass test: TS0(xOOxxOxO)TS7 MS_Class=39
Mass test: TS0(xOOxxOxO)TS7 MS_Class=40
Mass test: TS0(xOOxxOxO)TS7 MS_Class=41
Mass test: TS0(xOOxxOxO)TS7 MS_Class=42
Mass test: TS0(xOOxxOxO)TS7 MS_Class=43
Mass test: TS0(xOOxxOxO)TS7 MS_Class=44
Mass test: TS0(xOOxxOxO)TS7 MS_Class=45
Mass test: TS0(xOOxxOOx)TS7 MS_Class=0
Mass test: TS0(xOOxxOOx)TS7 MS_Class=1
Mass test: TS0(xOOxxOOx)TS7 MS_Class=2
Mass test: TS0(xOOxxOOx)TS7 MS_Class=3
Mass test: TS0(xOOxxOOx)TS7 MS_Class=4
Mass test: TS0(xOOxxOOx)TS7 MS_Class=5
Mass test: TS0(xOOxxOOx)TS7 MS_Class=6
Mass test: TS0(xOOxxOOx)TS7 MS_Class=7
Mass test: TS0(xOOxxOOx)TS7 MS_Class=8
Mass test: TS0(xOOxxOOx)TS7 MS_Class=9
Mass test: TS0(xOOxxOOx)TS7 MS_Class=10
Mass test: TS0(xOOxxOOx)TS7 MS_Class=11
Mass test: TS0(xOOxxOOx)TS7 MS_Class=12
Mass test: TS0(xOOxxOOx)TS7 MS_Class=13
Mass test: TS0(xOOxxOOx)TS7 MS_Class=14
Mass test: TS0(xOOxxOOx)TS7 MS_Class=15
Mass test: TS0(xOOxxOOx)TS7 MS_Class=16
Mass test: TS0(xOOxxOOx)TS7 MS_Class=17
Mass test: TS0(xOOxxOOx)TS7 MS_Class=18
Mass test: TS0(xOOxxOOx)TS7 MS_Class=19
Mass test: TS0(xOOxxOOx)TS7 MS_Class=20
Mass test: TS0(xOOxxOOx)TS7 MS_Class=21
Mass test: TS0(xOOxxOOx)TS7 MS_Class=22
Mass test: TS0(xOOxxOOx)TS7 MS_Class=23
Mass test: TS0(xOOxxOOx)TS7 MS_Class=24
Mass test: TS0(xOOxxOOx)TS7 MS_Class=25
Mass test: TS0(xOOxxOOx)TS7 MS_Class=26
Mass test: TS0(xOOxxOOx)TS7 MS_Class=27
Mass test: TS0(xOOxxOOx)TS7 MS_Class=28
Mass test: TS0(xOOxxOOx)TS7 MS_Class=29
Mass test: TS0(xOOxxOOx)TS7 MS_Class=30
Mass test: TS0(xOOxxOOx)TS7 MS_Class=31
Mass test: TS0(xOOxxOOx)TS7 MS_Class=32
Mass test: TS0(xOOxxOOx)TS7 MS_Class=33
Mass test: TS0(xOOxxOOx)TS7 MS_Class=34
Mass test: TS0(xOOxxOOx)TS7 MS_Class=35
Mass test: TS0(xOOxxOOx)TS7 MS_Class=36
Mass test: TS0(xOOxxOOx)TS7 MS_Class=37
Mass test: TS0(xOOxxOOx)TS7 MS_Class=38
Mass test: TS0(xOOxxOOx)TS7 MS_Class=39
Mass test: TS0(xOOxxOOx)TS7 MS_Class=40
Mass test: TS0(xOOxxOOx)TS7 MS_Class=41
Mass test: TS0(xOOxxOOx)TS7 MS_Class=42
Mass test: TS0(xOOxxOOx)TS7 MS_Class=43
Mass test: TS0(xOOxxOOx)TS7 MS_Class=44
Mass test: TS0(xOOxxOOx)TS7 MS_Class=45
Mass test: TS0(xOOxxOOO)TS7 MS_Class=0
Mass test: TS0(xOOxxOOO)TS7 MS_Class=1
Mass test: TS0(xOOxxOOO)TS7 MS_Class=2
Mass test: TS0(xOOxxOOO)TS7 MS_Class=3
Mass test: TS0(xOOxxOOO)TS7 MS_Class=4
Mass test: TS0(xOOxxOOO)TS7 MS_Class=5
Mass test: TS0(xOOxxOOO)TS7 MS_Class=6
Mass test: TS0(xOOxxOOO)TS7 MS_Class=7
Mass test: TS0(xOOxxOOO)TS7 MS_Class=8
Mass test: TS0(xOOxxOOO)TS7 MS_Class=9
Mass test: TS0(xOOxxOOO)TS7 MS_Class=10
Mass test: TS0(xOOxxOOO)TS7 MS_Class=11
Mass test: TS0(xOOxxOOO)TS7 MS_Class=12
Mass test: TS0(xOOxxOOO)TS7 MS_Class=13
Mass test: TS0(xOOxxOOO)TS7 MS_Class=14
Mass test: TS0(xOOxxOOO)TS7 MS_Class=15
Mass test: TS0(xOOxxOOO)TS7 MS_Class=16
Mass test: TS0(xOOxxOOO)TS7 MS_Class=17
Mass test: TS0(xOOxxOOO)TS7 MS_Class=18
Mass test: TS0(xOOxxOOO)TS7 MS_Class=19
Mass test: TS0(xOOxxOOO)TS7 MS_Class=20
Mass test: TS0(xOOxxOOO)TS7 MS_Class=21
Mass test: TS0(xOOxxOOO)TS7 MS_Class=22
Mass test: TS0(xOOxxOOO)TS7 MS_Class=23
Mass test: TS0(xOOxxOOO)TS7 MS_Class=24
Mass test: TS0(xOOxxOOO)TS7 MS_Class=25
Mass test: TS0(xOOxxOOO)TS7 MS_Class=26
Mass test: TS0(xOOxxOOO)TS7 MS_Class=27
Mass test: TS0(xOOxxOOO)TS7 MS_Class=28
Mass test: TS0(xOOxxOOO)TS7 MS_Class=29
Mass test: TS0(xOOxxOOO)TS7 MS_Class=30
Mass test: TS0(xOOxxOOO)TS7 MS_Class=31
Mass test: TS0(xOOxxOOO)TS7 MS_Class=32
Mass test: TS0(xOOxxOOO)TS7 MS_Class=33
Mass test: TS0(xOOxxOOO)TS7 MS_Class=34
Mass test: TS0(xOOxxOOO)TS7 MS_Class=35
Mass test: TS0(xOOxxOOO)TS7 MS_Class=36
Mass test: TS0(xOOxxOOO)TS7 MS_Class=37
Mass test: TS0(xOOxxOOO)TS7 MS_Class=38
Mass test: TS0(xOOxxOOO)TS7 MS_Class=39
Mass test: TS0(xOOxxOOO)TS7 MS_Class=40
Mass test: TS0(xOOxxOOO)TS7 MS_Class=41
Mass test: TS0(xOOxxOOO)TS7 MS_Class=42
Mass test: TS0(xOOxxOOO)TS7 MS_Class=43
Mass test: TS0(xOOxxOOO)TS7 MS_Class=44
Mass test: TS0(xOOxxOOO)TS7 MS_Class=45
Mass test: TS0(xOOxOxxx)TS7 MS_Class=0
Mass test: TS0(xOOxOxxx)TS7 MS_Class=1
Mass test: TS0(xOOxOxxx)TS7 MS_Class=2
Mass test: TS0(xOOxOxxx)TS7 MS_Class=3
Mass test: TS0(xOOxOxxx)TS7 MS_Class=4
Mass test: TS0(xOOxOxxx)TS7 MS_Class=5
Mass test: TS0(xOOxOxxx)TS7 MS_Class=6
Mass test: TS0(xOOxOxxx)TS7 MS_Class=7
Mass test: TS0(xOOxOxxx)TS7 MS_Class=8
Mass test: TS0(xOOxOxxx)TS7 MS_Class=9
Mass test: TS0(xOOxOxxx)TS7 MS_Class=10
Mass test: TS0(xOOxOxxx)TS7 MS_Class=11
Mass test: TS0(xOOxOxxx)TS7 MS_Class=12
Mass test: TS0(xOOxOxxx)TS7 MS_Class=13
Mass test: TS0(xOOxOxxx)TS7 MS_Class=14
Mass test: TS0(xOOxOxxx)TS7 MS_Class=15
Mass test: TS0(xOOxOxxx)TS7 MS_Class=16
Mass test: TS0(xOOxOxxx)TS7 MS_Class=17
Mass test: TS0(xOOxOxxx)TS7 MS_Class=18
Mass test: TS0(xOOxOxxx)TS7 MS_Class=19
Mass test: TS0(xOOxOxxx)TS7 MS_Class=20
Mass test: TS0(xOOxOxxx)TS7 MS_Class=21
Mass test: TS0(xOOxOxxx)TS7 MS_Class=22
Mass test: TS0(xOOxOxxx)TS7 MS_Class=23
Mass test: TS0(xOOxOxxx)TS7 MS_Class=24
Mass test: TS0(xOOxOxxx)TS7 MS_Class=25
Mass test: TS0(xOOxOxxx)TS7 MS_Class=26
Mass test: TS0(xOOxOxxx)TS7 MS_Class=27
Mass test: TS0(xOOxOxxx)TS7 MS_Class=28
Mass test: TS0(xOOxOxxx)TS7 MS_Class=29
Mass test: TS0(xOOxOxxx)TS7 MS_Class=30
Mass test: TS0(xOOxOxxx)TS7 MS_Class=31
Mass test: TS0(xOOxOxxx)TS7 MS_Class=32
Mass test: TS0(xOOxOxxx)TS7 MS_Class=33
Mass test: TS0(xOOxOxxx)TS7 MS_Class=34
Mass test: TS0(xOOxOxxx)TS7 MS_Class=35
Mass test: TS0(xOOxOxxx)TS7 MS_Class=36
Mass test: TS0(xOOxOxxx)TS7 MS_Class=37
Mass test: TS0(xOOxOxxx)TS7 MS_Class=38
Mass test: TS0(xOOxOxxx)TS7 MS_Class=39
Mass test: TS0(xOOxOxxx)TS7 MS_Class=40
Mass test: TS0(xOOxOxxx)TS7 MS_Class=41
Mass test: TS0(xOOxOxxx)TS7 MS_Class=42
Mass test: TS0(xOOxOxxx)TS7 MS_Class=43
Mass test: TS0(xOOxOxxx)TS7 MS_Class=44
Mass test: TS0(xOOxOxxx)TS7 MS_Class=45
Mass test: TS0(xOOxOxxO)TS7 MS_Class=0
Mass test: TS0(xOOxOxxO)TS7 MS_Class=1
Mass test: TS0(xOOxOxxO)TS7 MS_Class=2
Mass test: TS0(xOOxOxxO)TS7 MS_Class=3
Mass test: TS0(xOOxOxxO)TS7 MS_Class=4
Mass test: TS0(xOOxOxxO)TS7 MS_Class=5
Mass test: TS0(xOOxOxxO)TS7 MS_Class=6
Mass test: TS0(xOOxOxxO)TS7 MS_Class=7
Mass test: TS0(xOOxOxxO)TS7 MS_Class=8
Mass test: TS0(xOOxOxxO)TS7 MS_Class=9
Mass test: TS0(xOOxOxxO)TS7 MS_Class=10
Mass test: TS0(xOOxOxxO)TS7 MS_Class=11
Mass test: TS0(xOOxOxxO)TS7 MS_Class=12
Mass test: TS0(xOOxOxxO)TS7 MS_Class=13
Mass test: TS0(xOOxOxxO)TS7 MS_Class=14
Mass test: TS0(xOOxOxxO)TS7 MS_Class=15
Mass test: TS0(xOOxOxxO)TS7 MS_Class=16
Mass test: TS0(xOOxOxxO)TS7 MS_Class=17
Mass test: TS0(xOOxOxxO)TS7 MS_Class=18
Mass test: TS0(xOOxOxxO)TS7 MS_Class=19
Mass test: TS0(xOOxOxxO)TS7 MS_Class=20
Mass test: TS0(xOOxOxxO)TS7 MS_Class=21
Mass test: TS0(xOOxOxxO)TS7 MS_Class=22
Mass test: TS0(xOOxOxxO)TS7 MS_Class=23
Mass test: TS0(xOOxOxxO)TS7 MS_Class=24
Mass test: TS0(xOOxOxxO)TS7 MS_Class=25
Mass test: TS0(xOOxOxxO)TS7 MS_Class=26
Mass test: TS0(xOOxOxxO)TS7 MS_Class=27
Mass test: TS0(xOOxOxxO)TS7 MS_Class=28
Mass test: TS0(xOOxOxxO)TS7 MS_Class=29
Mass test: TS0(xOOxOxxO)TS7 MS_Class=30
Mass test: TS0(xOOxOxxO)TS7 MS_Class=31
Mass test: TS0(xOOxOxxO)TS7 MS_Class=32
Mass test: TS0(xOOxOxxO)TS7 MS_Class=33
Mass test: TS0(xOOxOxxO)TS7 MS_Class=34
Mass test: TS0(xOOxOxxO)TS7 MS_Class=35
Mass test: TS0(xOOxOxxO)TS7 MS_Class=36
Mass test: TS0(xOOxOxxO)TS7 MS_Class=37
Mass test: TS0(xOOxOxxO)TS7 MS_Class=38
Mass test: TS0(xOOxOxxO)TS7 MS_Class=39
Mass test: TS0(xOOxOxxO)TS7 MS_Class=40
Mass test: TS0(xOOxOxxO)TS7 MS_Class=41
Mass test: TS0(xOOxOxxO)TS7 MS_Class=42
Mass test: TS0(xOOxOxxO)TS7 MS_Class=43
Mass test: TS0(xOOxOxxO)TS7 MS_Class=44
Mass test: TS0(xOOxOxxO)TS7 MS_Class=45
Mass test: TS0(xOOxOxOx)TS7 MS_Class=0
Mass test: TS0(xOOxOxOx)TS7 MS_Class=1
Mass test: TS0(xOOxOxOx)TS7 MS_Class=2
Mass test: TS0(xOOxOxOx)TS7 MS_Class=3
Mass test: TS0(xOOxOxOx)TS7 MS_Class=4
Mass test: TS0(xOOxOxOx)TS7 MS_Class=5
Mass test: TS0(xOOxOxOx)TS7 MS_Class=6
Mass test: TS0(xOOxOxOx)TS7 MS_Class=7
Mass test: TS0(xOOxOxOx)TS7 MS_Class=8
Mass test: TS0(xOOxOxOx)TS7 MS_Class=9
Mass test: TS0(xOOxOxOx)TS7 MS_Class=10
Mass test: TS0(xOOxOxOx)TS7 MS_Class=11
Mass test: TS0(xOOxOxOx)TS7 MS_Class=12
Mass test: TS0(xOOxOxOx)TS7 MS_Class=13
Mass test: TS0(xOOxOxOx)TS7 MS_Class=14
Mass test: TS0(xOOxOxOx)TS7 MS_Class=15
Mass test: TS0(xOOxOxOx)TS7 MS_Class=16
Mass test: TS0(xOOxOxOx)TS7 MS_Class=17
Mass test: TS0(xOOxOxOx)TS7 MS_Class=18
Mass test: TS0(xOOxOxOx)TS7 MS_Class=19
Mass test: TS0(xOOxOxOx)TS7 MS_Class=20
Mass test: TS0(xOOxOxOx)TS7 MS_Class=21
Mass test: TS0(xOOxOxOx)TS7 MS_Class=22
Mass test: TS0(xOOxOxOx)TS7 MS_Class=23
Mass test: TS0(xOOxOxOx)TS7 MS_Class=24
Mass test: TS0(xOOxOxOx)TS7 MS_Class=25
Mass test: TS0(xOOxOxOx)TS7 MS_Class=26
Mass test: TS0(xOOxOxOx)TS7 MS_Class=27
Mass test: TS0(xOOxOxOx)TS7 MS_Class=28
Mass test: TS0(xOOxOxOx)TS7 MS_Class=29
Mass test: TS0(xOOxOxOx)TS7 MS_Class=30
Mass test: TS0(xOOxOxOx)TS7 MS_Class=31
Mass test: TS0(xOOxOxOx)TS7 MS_Class=32
Mass test: TS0(xOOxOxOx)TS7 MS_Class=33
Mass test: TS0(xOOxOxOx)TS7 MS_Class=34
Mass test: TS0(xOOxOxOx)TS7 MS_Class=35
Mass test: TS0(xOOxOxOx)TS7 MS_Class=36
Mass test: TS0(xOOxOxOx)TS7 MS_Class=37
Mass test: TS0(xOOxOxOx)TS7 MS_Class=38
Mass test: TS0(xOOxOxOx)TS7 MS_Class=39
Mass test: TS0(xOOxOxOx)TS7 MS_Class=40
Mass test: TS0(xOOxOxOx)TS7 MS_Class=41
Mass test: TS0(xOOxOxOx)TS7 MS_Class=42
Mass test: TS0(xOOxOxOx)TS7 MS_Class=43
Mass test: TS0(xOOxOxOx)TS7 MS_Class=44
Mass test: TS0(xOOxOxOx)TS7 MS_Class=45
Mass test: TS0(xOOxOxOO)TS7 MS_Class=0
Mass test: TS0(xOOxOxOO)TS7 MS_Class=1
Mass test: TS0(xOOxOxOO)TS7 MS_Class=2
Mass test: TS0(xOOxOxOO)TS7 MS_Class=3
Mass test: TS0(xOOxOxOO)TS7 MS_Class=4
Mass test: TS0(xOOxOxOO)TS7 MS_Class=5
Mass test: TS0(xOOxOxOO)TS7 MS_Class=6
Mass test: TS0(xOOxOxOO)TS7 MS_Class=7
Mass test: TS0(xOOxOxOO)TS7 MS_Class=8
Mass test: TS0(xOOxOxOO)TS7 MS_Class=9
Mass test: TS0(xOOxOxOO)TS7 MS_Class=10
Mass test: TS0(xOOxOxOO)TS7 MS_Class=11
Mass test: TS0(xOOxOxOO)TS7 MS_Class=12
Mass test: TS0(xOOxOxOO)TS7 MS_Class=13
Mass test: TS0(xOOxOxOO)TS7 MS_Class=14
Mass test: TS0(xOOxOxOO)TS7 MS_Class=15
Mass test: TS0(xOOxOxOO)TS7 MS_Class=16
Mass test: TS0(xOOxOxOO)TS7 MS_Class=17
Mass test: TS0(xOOxOxOO)TS7 MS_Class=18
Mass test: TS0(xOOxOxOO)TS7 MS_Class=19
Mass test: TS0(xOOxOxOO)TS7 MS_Class=20
Mass test: TS0(xOOxOxOO)TS7 MS_Class=21
Mass test: TS0(xOOxOxOO)TS7 MS_Class=22
Mass test: TS0(xOOxOxOO)TS7 MS_Class=23
Mass test: TS0(xOOxOxOO)TS7 MS_Class=24
Mass test: TS0(xOOxOxOO)TS7 MS_Class=25
Mass test: TS0(xOOxOxOO)TS7 MS_Class=26
Mass test: TS0(xOOxOxOO)TS7 MS_Class=27
Mass test: TS0(xOOxOxOO)TS7 MS_Class=28
Mass test: TS0(xOOxOxOO)TS7 MS_Class=29
Mass test: TS0(xOOxOxOO)TS7 MS_Class=30
Mass test: TS0(xOOxOxOO)TS7 MS_Class=31
Mass test: TS0(xOOxOxOO)TS7 MS_Class=32
Mass test: TS0(xOOxOxOO)TS7 MS_Class=33
Mass test: TS0(xOOxOxOO)TS7 MS_Class=34
Mass test: TS0(xOOxOxOO)TS7 MS_Class=35
Mass test: TS0(xOOxOxOO)TS7 MS_Class=36
Mass test: TS0(xOOxOxOO)TS7 MS_Class=37
Mass test: TS0(xOOxOxOO)TS7 MS_Class=38
Mass test: TS0(xOOxOxOO)TS7 MS_Class=39
Mass test: TS0(xOOxOxOO)TS7 MS_Class=40
Mass test: TS0(xOOxOxOO)TS7 MS_Class=41
Mass test: TS0(xOOxOxOO)TS7 MS_Class=42
Mass test: TS0(xOOxOxOO)TS7 MS_Class=43
Mass test: TS0(xOOxOxOO)TS7 MS_Class=44
Mass test: TS0(xOOxOxOO)TS7 MS_Class=45
Mass test: TS0(xOOxOOxx)TS7 MS_Class=0
Mass test: TS0(xOOxOOxx)TS7 MS_Class=1
Mass test: TS0(xOOxOOxx)TS7 MS_Class=2
Mass test: TS0(xOOxOOxx)TS7 MS_Class=3
Mass test: TS0(xOOxOOxx)TS7 MS_Class=4
Mass test: TS0(xOOxOOxx)TS7 MS_Class=5
Mass test: TS0(xOOxOOxx)TS7 MS_Class=6
Mass test: TS0(xOOxOOxx)TS7 MS_Class=7
Mass test: TS0(xOOxOOxx)TS7 MS_Class=8
Mass test: TS0(xOOxOOxx)TS7 MS_Class=9
Mass test: TS0(xOOxOOxx)TS7 MS_Class=10
Mass test: TS0(xOOxOOxx)TS7 MS_Class=11
Mass test: TS0(xOOxOOxx)TS7 MS_Class=12
Mass test: TS0(xOOxOOxx)TS7 MS_Class=13
Mass test: TS0(xOOxOOxx)TS7 MS_Class=14
Mass test: TS0(xOOxOOxx)TS7 MS_Class=15
Mass test: TS0(xOOxOOxx)TS7 MS_Class=16
Mass test: TS0(xOOxOOxx)TS7 MS_Class=17
Mass test: TS0(xOOxOOxx)TS7 MS_Class=18
Mass test: TS0(xOOxOOxx)TS7 MS_Class=19
Mass test: TS0(xOOxOOxx)TS7 MS_Class=20
Mass test: TS0(xOOxOOxx)TS7 MS_Class=21
Mass test: TS0(xOOxOOxx)TS7 MS_Class=22
Mass test: TS0(xOOxOOxx)TS7 MS_Class=23
Mass test: TS0(xOOxOOxx)TS7 MS_Class=24
Mass test: TS0(xOOxOOxx)TS7 MS_Class=25
Mass test: TS0(xOOxOOxx)TS7 MS_Class=26
Mass test: TS0(xOOxOOxx)TS7 MS_Class=27
Mass test: TS0(xOOxOOxx)TS7 MS_Class=28
Mass test: TS0(xOOxOOxx)TS7 MS_Class=29
Mass test: TS0(xOOxOOxx)TS7 MS_Class=30
Mass test: TS0(xOOxOOxx)TS7 MS_Class=31
Mass test: TS0(xOOxOOxx)TS7 MS_Class=32
Mass test: TS0(xOOxOOxx)TS7 MS_Class=33
Mass test: TS0(xOOxOOxx)TS7 MS_Class=34
Mass test: TS0(xOOxOOxx)TS7 MS_Class=35
Mass test: TS0(xOOxOOxx)TS7 MS_Class=36
Mass test: TS0(xOOxOOxx)TS7 MS_Class=37
Mass test: TS0(xOOxOOxx)TS7 MS_Class=38
Mass test: TS0(xOOxOOxx)TS7 MS_Class=39
Mass test: TS0(xOOxOOxx)TS7 MS_Class=40
Mass test: TS0(xOOxOOxx)TS7 MS_Class=41
Mass test: TS0(xOOxOOxx)TS7 MS_Class=42
Mass test: TS0(xOOxOOxx)TS7 MS_Class=43
Mass test: TS0(xOOxOOxx)TS7 MS_Class=44
Mass test: TS0(xOOxOOxx)TS7 MS_Class=45
Mass test: TS0(xOOxOOxO)TS7 MS_Class=0
Mass test: TS0(xOOxOOxO)TS7 MS_Class=1
Mass test: TS0(xOOxOOxO)TS7 MS_Class=2
Mass test: TS0(xOOxOOxO)TS7 MS_Class=3
Mass test: TS0(xOOxOOxO)TS7 MS_Class=4
Mass test: TS0(xOOxOOxO)TS7 MS_Class=5
Mass test: TS0(xOOxOOxO)TS7 MS_Class=6
Mass test: TS0(xOOxOOxO)TS7 MS_Class=7
Mass test: TS0(xOOxOOxO)TS7 MS_Class=8
Mass test: TS0(xOOxOOxO)TS7 MS_Class=9
Mass test: TS0(xOOxOOxO)TS7 MS_Class=10
Mass test: TS0(xOOxOOxO)TS7 MS_Class=11
Mass test: TS0(xOOxOOxO)TS7 MS_Class=12
Mass test: TS0(xOOxOOxO)TS7 MS_Class=13
Mass test: TS0(xOOxOOxO)TS7 MS_Class=14
Mass test: TS0(xOOxOOxO)TS7 MS_Class=15
Mass test: TS0(xOOxOOxO)TS7 MS_Class=16
Mass test: TS0(xOOxOOxO)TS7 MS_Class=17
Mass test: TS0(xOOxOOxO)TS7 MS_Class=18
Mass test: TS0(xOOxOOxO)TS7 MS_Class=19
Mass test: TS0(xOOxOOxO)TS7 MS_Class=20
Mass test: TS0(xOOxOOxO)TS7 MS_Class=21
Mass test: TS0(xOOxOOxO)TS7 MS_Class=22
Mass test: TS0(xOOxOOxO)TS7 MS_Class=23
Mass test: TS0(xOOxOOxO)TS7 MS_Class=24
Mass test: TS0(xOOxOOxO)TS7 MS_Class=25
Mass test: TS0(xOOxOOxO)TS7 MS_Class=26
Mass test: TS0(xOOxOOxO)TS7 MS_Class=27
Mass test: TS0(xOOxOOxO)TS7 MS_Class=28
Mass test: TS0(xOOxOOxO)TS7 MS_Class=29
Mass test: TS0(xOOxOOxO)TS7 MS_Class=30
Mass test: TS0(xOOxOOxO)TS7 MS_Class=31
Mass test: TS0(xOOxOOxO)TS7 MS_Class=32
Mass test: TS0(xOOxOOxO)TS7 MS_Class=33
Mass test: TS0(xOOxOOxO)TS7 MS_Class=34
Mass test: TS0(xOOxOOxO)TS7 MS_Class=35
Mass test: TS0(xOOxOOxO)TS7 MS_Class=36
Mass test: TS0(xOOxOOxO)TS7 MS_Class=37
Mass test: TS0(xOOxOOxO)TS7 MS_Class=38
Mass test: TS0(xOOxOOxO)TS7 MS_Class=39
Mass test: TS0(xOOxOOxO)TS7 MS_Class=40
Mass test: TS0(xOOxOOxO)TS7 MS_Class=41
Mass test: TS0(xOOxOOxO)TS7 MS_Class=42
Mass test: TS0(xOOxOOxO)TS7 MS_Class=43
Mass test: TS0(xOOxOOxO)TS7 MS_Class=44
Mass test: TS0(xOOxOOxO)TS7 MS_Class=45
Mass test: TS0(xOOxOOOx)TS7 MS_Class=0
Mass test: TS0(xOOxOOOx)TS7 MS_Class=1
Mass test: TS0(xOOxOOOx)TS7 MS_Class=2
Mass test: TS0(xOOxOOOx)TS7 MS_Class=3
Mass test: TS0(xOOxOOOx)TS7 MS_Class=4
Mass test: TS0(xOOxOOOx)TS7 MS_Class=5
Mass test: TS0(xOOxOOOx)TS7 MS_Class=6
Mass test: TS0(xOOxOOOx)TS7 MS_Class=7
Mass test: TS0(xOOxOOOx)TS7 MS_Class=8
Mass test: TS0(xOOxOOOx)TS7 MS_Class=9
Mass test: TS0(xOOxOOOx)TS7 MS_Class=10
Mass test: TS0(xOOxOOOx)TS7 MS_Class=11
Mass test: TS0(xOOxOOOx)TS7 MS_Class=12
Mass test: TS0(xOOxOOOx)TS7 MS_Class=13
Mass test: TS0(xOOxOOOx)TS7 MS_Class=14
Mass test: TS0(xOOxOOOx)TS7 MS_Class=15
Mass test: TS0(xOOxOOOx)TS7 MS_Class=16
Mass test: TS0(xOOxOOOx)TS7 MS_Class=17
Mass test: TS0(xOOxOOOx)TS7 MS_Class=18
Mass test: TS0(xOOxOOOx)TS7 MS_Class=19
Mass test: TS0(xOOxOOOx)TS7 MS_Class=20
Mass test: TS0(xOOxOOOx)TS7 MS_Class=21
Mass test: TS0(xOOxOOOx)TS7 MS_Class=22
Mass test: TS0(xOOxOOOx)TS7 MS_Class=23
Mass test: TS0(xOOxOOOx)TS7 MS_Class=24
Mass test: TS0(xOOxOOOx)TS7 MS_Class=25
Mass test: TS0(xOOxOOOx)TS7 MS_Class=26
Mass test: TS0(xOOxOOOx)TS7 MS_Class=27
Mass test: TS0(xOOxOOOx)TS7 MS_Class=28
Mass test: TS0(xOOxOOOx)TS7 MS_Class=29
Mass test: TS0(xOOxOOOx)TS7 MS_Class=30
Mass test: TS0(xOOxOOOx)TS7 MS_Class=31
Mass test: TS0(xOOxOOOx)TS7 MS_Class=32
Mass test: TS0(xOOxOOOx)TS7 MS_Class=33
Mass test: TS0(xOOxOOOx)TS7 MS_Class=34
Mass test: TS0(xOOxOOOx)TS7 MS_Class=35
Mass test: TS0(xOOxOOOx)TS7 MS_Class=36
Mass test: TS0(xOOxOOOx)TS7 MS_Class=37
Mass test: TS0(xOOxOOOx)TS7 MS_Class=38
Mass test: TS0(xOOxOOOx)TS7 MS_Class=39
Mass test: TS0(xOOxOOOx)TS7 MS_Class=40
Mass test: TS0(xOOxOOOx)TS7 MS_Class=41
Mass test: TS0(xOOxOOOx)TS7 MS_Class=42
Mass test: TS0(xOOxOOOx)TS7 MS_Class=43
Mass test: TS0(xOOxOOOx)TS7 MS_Class=44
Mass test: TS0(xOOxOOOx)TS7 MS_Class=45
Mass test: TS0(xOOxOOOO)TS7 MS_Class=0
Mass test: TS0(xOOxOOOO)TS7 MS_Class=1
Mass test: TS0(xOOxOOOO)TS7 MS_Class=2
Mass test: TS0(xOOxOOOO)TS7 MS_Class=3
Mass test: TS0(xOOxOOOO)TS7 MS_Class=4
Mass test: TS0(xOOxOOOO)TS7 MS_Class=5
Mass test: TS0(xOOxOOOO)TS7 MS_Class=6
Mass test: TS0(xOOxOOOO)TS7 MS_Class=7
Mass test: TS0(xOOxOOOO)TS7 MS_Class=8
Mass test: TS0(xOOxOOOO)TS7 MS_Class=9
Mass test: TS0(xOOxOOOO)TS7 MS_Class=10
Mass test: TS0(xOOxOOOO)TS7 MS_Class=11
Mass test: TS0(xOOxOOOO)TS7 MS_Class=12
Mass test: TS0(xOOxOOOO)TS7 MS_Class=13
Mass test: TS0(xOOxOOOO)TS7 MS_Class=14
Mass test: TS0(xOOxOOOO)TS7 MS_Class=15
Mass test: TS0(xOOxOOOO)TS7 MS_Class=16
Mass test: TS0(xOOxOOOO)TS7 MS_Class=17
Mass test: TS0(xOOxOOOO)TS7 MS_Class=18
Mass test: TS0(xOOxOOOO)TS7 MS_Class=19
Mass test: TS0(xOOxOOOO)TS7 MS_Class=20
Mass test: TS0(xOOxOOOO)TS7 MS_Class=21
Mass test: TS0(xOOxOOOO)TS7 MS_Class=22
Mass test: TS0(xOOxOOOO)TS7 MS_Class=23
Mass test: TS0(xOOxOOOO)TS7 MS_Class=24
Mass test: TS0(xOOxOOOO)TS7 MS_Class=25
Mass test: TS0(xOOxOOOO)TS7 MS_Class=26
Mass test: TS0(xOOxOOOO)TS7 MS_Class=27
Mass test: TS0(xOOxOOOO)TS7 MS_Class=28
Mass test: TS0(xOOxOOOO)TS7 MS_Class=29
Mass test: TS0(xOOxOOOO)TS7 MS_Class=30
Mass test: TS0(xOOxOOOO)TS7 MS_Class=31
Mass test: TS0(xOOxOOOO)TS7 MS_Class=32
Mass test: TS0(xOOxOOOO)TS7 MS_Class=33
Mass test: TS0(xOOxOOOO)TS7 MS_Class=34
Mass test: TS0(xOOxOOOO)TS7 MS_Class=35
Mass test: TS0(xOOxOOOO)TS7 MS_Class=36
Mass test: TS0(xOOxOOOO)TS7 MS_Class=37
Mass test: TS0(xOOxOOOO)TS7 MS_Class=38
Mass test: TS0(xOOxOOOO)TS7 MS_Class=39
Mass test: TS0(xOOxOOOO)TS7 MS_Class=40
Mass test: TS0(xOOxOOOO)TS7 MS_Class=41
Mass test: TS0(xOOxOOOO)TS7 MS_Class=42
Mass test: TS0(xOOxOOOO)TS7 MS_Class=43
Mass test: TS0(xOOxOOOO)TS7 MS_Class=44
Mass test: TS0(xOOxOOOO)TS7 MS_Class=45
Mass test: TS0(xOOOxxxx)TS7 MS_Class=0
Mass test: TS0(xOOOxxxx)TS7 MS_Class=1
Mass test: TS0(xOOOxxxx)TS7 MS_Class=2
Mass test: TS0(xOOOxxxx)TS7 MS_Class=3
Mass test: TS0(xOOOxxxx)TS7 MS_Class=4
Mass test: TS0(xOOOxxxx)TS7 MS_Class=5
Mass test: TS0(xOOOxxxx)TS7 MS_Class=6
Mass test: TS0(xOOOxxxx)TS7 MS_Class=7
Mass test: TS0(xOOOxxxx)TS7 MS_Class=8
Mass test: TS0(xOOOxxxx)TS7 MS_Class=9
Mass test: TS0(xOOOxxxx)TS7 MS_Class=10
Mass test: TS0(xOOOxxxx)TS7 MS_Class=11
Mass test: TS0(xOOOxxxx)TS7 MS_Class=12
Mass test: TS0(xOOOxxxx)TS7 MS_Class=13
Mass test: TS0(xOOOxxxx)TS7 MS_Class=14
Mass test: TS0(xOOOxxxx)TS7 MS_Class=15
Mass test: TS0(xOOOxxxx)TS7 MS_Class=16
Mass test: TS0(xOOOxxxx)TS7 MS_Class=17
Mass test: TS0(xOOOxxxx)TS7 MS_Class=18
Mass test: TS0(xOOOxxxx)TS7 MS_Class=19
Mass test: TS0(xOOOxxxx)TS7 MS_Class=20
Mass test: TS0(xOOOxxxx)TS7 MS_Class=21
Mass test: TS0(xOOOxxxx)TS7 MS_Class=22
Mass test: TS0(xOOOxxxx)TS7 MS_Class=23
Mass test: TS0(xOOOxxxx)TS7 MS_Class=24
Mass test: TS0(xOOOxxxx)TS7 MS_Class=25
Mass test: TS0(xOOOxxxx)TS7 MS_Class=26
Mass test: TS0(xOOOxxxx)TS7 MS_Class=27
Mass test: TS0(xOOOxxxx)TS7 MS_Class=28
Mass test: TS0(xOOOxxxx)TS7 MS_Class=29
Mass test: TS0(xOOOxxxx)TS7 MS_Class=30
Mass test: TS0(xOOOxxxx)TS7 MS_Class=31
Mass test: TS0(xOOOxxxx)TS7 MS_Class=32
Mass test: TS0(xOOOxxxx)TS7 MS_Class=33
Mass test: TS0(xOOOxxxx)TS7 MS_Class=34
Mass test: TS0(xOOOxxxx)TS7 MS_Class=35
Mass test: TS0(xOOOxxxx)TS7 MS_Class=36
Mass test: TS0(xOOOxxxx)TS7 MS_Class=37
Mass test: TS0(xOOOxxxx)TS7 MS_Class=38
Mass test: TS0(xOOOxxxx)TS7 MS_Class=39
Mass test: TS0(xOOOxxxx)TS7 MS_Class=40
Mass test: TS0(xOOOxxxx)TS7 MS_Class=41
Mass test: TS0(xOOOxxxx)TS7 MS_Class=42
Mass test: TS0(xOOOxxxx)TS7 MS_Class=43
Mass test: TS0(xOOOxxxx)TS7 MS_Class=44
Mass test: TS0(xOOOxxxx)TS7 MS_Class=45
Mass test: TS0(xOOOxxxO)TS7 MS_Class=0
Mass test: TS0(xOOOxxxO)TS7 MS_Class=1
Mass test: TS0(xOOOxxxO)TS7 MS_Class=2
Mass test: TS0(xOOOxxxO)TS7 MS_Class=3
Mass test: TS0(xOOOxxxO)TS7 MS_Class=4
Mass test: TS0(xOOOxxxO)TS7 MS_Class=5
Mass test: TS0(xOOOxxxO)TS7 MS_Class=6
Mass test: TS0(xOOOxxxO)TS7 MS_Class=7
Mass test: TS0(xOOOxxxO)TS7 MS_Class=8
Mass test: TS0(xOOOxxxO)TS7 MS_Class=9
Mass test: TS0(xOOOxxxO)TS7 MS_Class=10
Mass test: TS0(xOOOxxxO)TS7 MS_Class=11
Mass test: TS0(xOOOxxxO)TS7 MS_Class=12
Mass test: TS0(xOOOxxxO)TS7 MS_Class=13
Mass test: TS0(xOOOxxxO)TS7 MS_Class=14
Mass test: TS0(xOOOxxxO)TS7 MS_Class=15
Mass test: TS0(xOOOxxxO)TS7 MS_Class=16
Mass test: TS0(xOOOxxxO)TS7 MS_Class=17
Mass test: TS0(xOOOxxxO)TS7 MS_Class=18
Mass test: TS0(xOOOxxxO)TS7 MS_Class=19
Mass test: TS0(xOOOxxxO)TS7 MS_Class=20
Mass test: TS0(xOOOxxxO)TS7 MS_Class=21
Mass test: TS0(xOOOxxxO)TS7 MS_Class=22
Mass test: TS0(xOOOxxxO)TS7 MS_Class=23
Mass test: TS0(xOOOxxxO)TS7 MS_Class=24
Mass test: TS0(xOOOxxxO)TS7 MS_Class=25
Mass test: TS0(xOOOxxxO)TS7 MS_Class=26
Mass test: TS0(xOOOxxxO)TS7 MS_Class=27
Mass test: TS0(xOOOxxxO)TS7 MS_Class=28
Mass test: TS0(xOOOxxxO)TS7 MS_Class=29
Mass test: TS0(xOOOxxxO)TS7 MS_Class=30
Mass test: TS0(xOOOxxxO)TS7 MS_Class=31
Mass test: TS0(xOOOxxxO)TS7 MS_Class=32
Mass test: TS0(xOOOxxxO)TS7 MS_Class=33
Mass test: TS0(xOOOxxxO)TS7 MS_Class=34
Mass test: TS0(xOOOxxxO)TS7 MS_Class=35
Mass test: TS0(xOOOxxxO)TS7 MS_Class=36
Mass test: TS0(xOOOxxxO)TS7 MS_Class=37
Mass test: TS0(xOOOxxxO)TS7 MS_Class=38
Mass test: TS0(xOOOxxxO)TS7 MS_Class=39
Mass test: TS0(xOOOxxxO)TS7 MS_Class=40
Mass test: TS0(xOOOxxxO)TS7 MS_Class=41
Mass test: TS0(xOOOxxxO)TS7 MS_Class=42
Mass test: TS0(xOOOxxxO)TS7 MS_Class=43
Mass test: TS0(xOOOxxxO)TS7 MS_Class=44
Mass test: TS0(xOOOxxxO)TS7 MS_Class=45
Mass test: TS0(xOOOxxOx)TS7 MS_Class=0
Mass test: TS0(xOOOxxOx)TS7 MS_Class=1
Mass test: TS0(xOOOxxOx)TS7 MS_Class=2
Mass test: TS0(xOOOxxOx)TS7 MS_Class=3
Mass test: TS0(xOOOxxOx)TS7 MS_Class=4
Mass test: TS0(xOOOxxOx)TS7 MS_Class=5
Mass test: TS0(xOOOxxOx)TS7 MS_Class=6
Mass test: TS0(xOOOxxOx)TS7 MS_Class=7
Mass test: TS0(xOOOxxOx)TS7 MS_Class=8
Mass test: TS0(xOOOxxOx)TS7 MS_Class=9
Mass test: TS0(xOOOxxOx)TS7 MS_Class=10
Mass test: TS0(xOOOxxOx)TS7 MS_Class=11
Mass test: TS0(xOOOxxOx)TS7 MS_Class=12
Mass test: TS0(xOOOxxOx)TS7 MS_Class=13
Mass test: TS0(xOOOxxOx)TS7 MS_Class=14
Mass test: TS0(xOOOxxOx)TS7 MS_Class=15
Mass test: TS0(xOOOxxOx)TS7 MS_Class=16
Mass test: TS0(xOOOxxOx)TS7 MS_Class=17
Mass test: TS0(xOOOxxOx)TS7 MS_Class=18
Mass test: TS0(xOOOxxOx)TS7 MS_Class=19
Mass test: TS0(xOOOxxOx)TS7 MS_Class=20
Mass test: TS0(xOOOxxOx)TS7 MS_Class=21
Mass test: TS0(xOOOxxOx)TS7 MS_Class=22
Mass test: TS0(xOOOxxOx)TS7 MS_Class=23
Mass test: TS0(xOOOxxOx)TS7 MS_Class=24
Mass test: TS0(xOOOxxOx)TS7 MS_Class=25
Mass test: TS0(xOOOxxOx)TS7 MS_Class=26
Mass test: TS0(xOOOxxOx)TS7 MS_Class=27
Mass test: TS0(xOOOxxOx)TS7 MS_Class=28
Mass test: TS0(xOOOxxOx)TS7 MS_Class=29
Mass test: TS0(xOOOxxOx)TS7 MS_Class=30
Mass test: TS0(xOOOxxOx)TS7 MS_Class=31
Mass test: TS0(xOOOxxOx)TS7 MS_Class=32
Mass test: TS0(xOOOxxOx)TS7 MS_Class=33
Mass test: TS0(xOOOxxOx)TS7 MS_Class=34
Mass test: TS0(xOOOxxOx)TS7 MS_Class=35
Mass test: TS0(xOOOxxOx)TS7 MS_Class=36
Mass test: TS0(xOOOxxOx)TS7 MS_Class=37
Mass test: TS0(xOOOxxOx)TS7 MS_Class=38
Mass test: TS0(xOOOxxOx)TS7 MS_Class=39
Mass test: TS0(xOOOxxOx)TS7 MS_Class=40
Mass test: TS0(xOOOxxOx)TS7 MS_Class=41
Mass test: TS0(xOOOxxOx)TS7 MS_Class=42
Mass test: TS0(xOOOxxOx)TS7 MS_Class=43
Mass test: TS0(xOOOxxOx)TS7 MS_Class=44
Mass test: TS0(xOOOxxOx)TS7 MS_Class=45
Mass test: TS0(xOOOxxOO)TS7 MS_Class=0
Mass test: TS0(xOOOxxOO)TS7 MS_Class=1
Mass test: TS0(xOOOxxOO)TS7 MS_Class=2
Mass test: TS0(xOOOxxOO)TS7 MS_Class=3
Mass test: TS0(xOOOxxOO)TS7 MS_Class=4
Mass test: TS0(xOOOxxOO)TS7 MS_Class=5
Mass test: TS0(xOOOxxOO)TS7 MS_Class=6
Mass test: TS0(xOOOxxOO)TS7 MS_Class=7
Mass test: TS0(xOOOxxOO)TS7 MS_Class=8
Mass test: TS0(xOOOxxOO)TS7 MS_Class=9
Mass test: TS0(xOOOxxOO)TS7 MS_Class=10
Mass test: TS0(xOOOxxOO)TS7 MS_Class=11
Mass test: TS0(xOOOxxOO)TS7 MS_Class=12
Mass test: TS0(xOOOxxOO)TS7 MS_Class=13
Mass test: TS0(xOOOxxOO)TS7 MS_Class=14
Mass test: TS0(xOOOxxOO)TS7 MS_Class=15
Mass test: TS0(xOOOxxOO)TS7 MS_Class=16
Mass test: TS0(xOOOxxOO)TS7 MS_Class=17
Mass test: TS0(xOOOxxOO)TS7 MS_Class=18
Mass test: TS0(xOOOxxOO)TS7 MS_Class=19
Mass test: TS0(xOOOxxOO)TS7 MS_Class=20
Mass test: TS0(xOOOxxOO)TS7 MS_Class=21
Mass test: TS0(xOOOxxOO)TS7 MS_Class=22
Mass test: TS0(xOOOxxOO)TS7 MS_Class=23
Mass test: TS0(xOOOxxOO)TS7 MS_Class=24
Mass test: TS0(xOOOxxOO)TS7 MS_Class=25
Mass test: TS0(xOOOxxOO)TS7 MS_Class=26
Mass test: TS0(xOOOxxOO)TS7 MS_Class=27
Mass test: TS0(xOOOxxOO)TS7 MS_Class=28
Mass test: TS0(xOOOxxOO)TS7 MS_Class=29
Mass test: TS0(xOOOxxOO)TS7 MS_Class=30
Mass test: TS0(xOOOxxOO)TS7 MS_Class=31
Mass test: TS0(xOOOxxOO)TS7 MS_Class=32
Mass test: TS0(xOOOxxOO)TS7 MS_Class=33
Mass test: TS0(xOOOxxOO)TS7 MS_Class=34
Mass test: TS0(xOOOxxOO)TS7 MS_Class=35
Mass test: TS0(xOOOxxOO)TS7 MS_Class=36
Mass test: TS0(xOOOxxOO)TS7 MS_Class=37
Mass test: TS0(xOOOxxOO)TS7 MS_Class=38
Mass test: TS0(xOOOxxOO)TS7 MS_Class=39
Mass test: TS0(xOOOxxOO)TS7 MS_Class=40
Mass test: TS0(xOOOxxOO)TS7 MS_Class=41
Mass test: TS0(xOOOxxOO)TS7 MS_Class=42
Mass test: TS0(xOOOxxOO)TS7 MS_Class=43
Mass test: TS0(xOOOxxOO)TS7 MS_Class=44
Mass test: TS0(xOOOxxOO)TS7 MS_Class=45
Mass test: TS0(xOOOxOxx)TS7 MS_Class=0
Mass test: TS0(xOOOxOxx)TS7 MS_Class=1
Mass test: TS0(xOOOxOxx)TS7 MS_Class=2
Mass test: TS0(xOOOxOxx)TS7 MS_Class=3
Mass test: TS0(xOOOxOxx)TS7 MS_Class=4
Mass test: TS0(xOOOxOxx)TS7 MS_Class=5
Mass test: TS0(xOOOxOxx)TS7 MS_Class=6
Mass test: TS0(xOOOxOxx)TS7 MS_Class=7
Mass test: TS0(xOOOxOxx)TS7 MS_Class=8
Mass test: TS0(xOOOxOxx)TS7 MS_Class=9
Mass test: TS0(xOOOxOxx)TS7 MS_Class=10
Mass test: TS0(xOOOxOxx)TS7 MS_Class=11
Mass test: TS0(xOOOxOxx)TS7 MS_Class=12
Mass test: TS0(xOOOxOxx)TS7 MS_Class=13
Mass test: TS0(xOOOxOxx)TS7 MS_Class=14
Mass test: TS0(xOOOxOxx)TS7 MS_Class=15
Mass test: TS0(xOOOxOxx)TS7 MS_Class=16
Mass test: TS0(xOOOxOxx)TS7 MS_Class=17
Mass test: TS0(xOOOxOxx)TS7 MS_Class=18
Mass test: TS0(xOOOxOxx)TS7 MS_Class=19
Mass test: TS0(xOOOxOxx)TS7 MS_Class=20
Mass test: TS0(xOOOxOxx)TS7 MS_Class=21
Mass test: TS0(xOOOxOxx)TS7 MS_Class=22
Mass test: TS0(xOOOxOxx)TS7 MS_Class=23
Mass test: TS0(xOOOxOxx)TS7 MS_Class=24
Mass test: TS0(xOOOxOxx)TS7 MS_Class=25
Mass test: TS0(xOOOxOxx)TS7 MS_Class=26
Mass test: TS0(xOOOxOxx)TS7 MS_Class=27
Mass test: TS0(xOOOxOxx)TS7 MS_Class=28
Mass test: TS0(xOOOxOxx)TS7 MS_Class=29
Mass test: TS0(xOOOxOxx)TS7 MS_Class=30
Mass test: TS0(xOOOxOxx)TS7 MS_Class=31
Mass test: TS0(xOOOxOxx)TS7 MS_Class=32
Mass test: TS0(xOOOxOxx)TS7 MS_Class=33
Mass test: TS0(xOOOxOxx)TS7 MS_Class=34
Mass test: TS0(xOOOxOxx)TS7 MS_Class=35
Mass test: TS0(xOOOxOxx)TS7 MS_Class=36
Mass test: TS0(xOOOxOxx)TS7 MS_Class=37
Mass test: TS0(xOOOxOxx)TS7 MS_Class=38
Mass test: TS0(xOOOxOxx)TS7 MS_Class=39
Mass test: TS0(xOOOxOxx)TS7 MS_Class=40
Mass test: TS0(xOOOxOxx)TS7 MS_Class=41
Mass test: TS0(xOOOxOxx)TS7 MS_Class=42
Mass test: TS0(xOOOxOxx)TS7 MS_Class=43
Mass test: TS0(xOOOxOxx)TS7 MS_Class=44
Mass test: TS0(xOOOxOxx)TS7 MS_Class=45
Mass test: TS0(xOOOxOxO)TS7 MS_Class=0
Mass test: TS0(xOOOxOxO)TS7 MS_Class=1
Mass test: TS0(xOOOxOxO)TS7 MS_Class=2
Mass test: TS0(xOOOxOxO)TS7 MS_Class=3
Mass test: TS0(xOOOxOxO)TS7 MS_Class=4
Mass test: TS0(xOOOxOxO)TS7 MS_Class=5
Mass test: TS0(xOOOxOxO)TS7 MS_Class=6
Mass test: TS0(xOOOxOxO)TS7 MS_Class=7
Mass test: TS0(xOOOxOxO)TS7 MS_Class=8
Mass test: TS0(xOOOxOxO)TS7 MS_Class=9
Mass test: TS0(xOOOxOxO)TS7 MS_Class=10
Mass test: TS0(xOOOxOxO)TS7 MS_Class=11
Mass test: TS0(xOOOxOxO)TS7 MS_Class=12
Mass test: TS0(xOOOxOxO)TS7 MS_Class=13
Mass test: TS0(xOOOxOxO)TS7 MS_Class=14
Mass test: TS0(xOOOxOxO)TS7 MS_Class=15
Mass test: TS0(xOOOxOxO)TS7 MS_Class=16
Mass test: TS0(xOOOxOxO)TS7 MS_Class=17
Mass test: TS0(xOOOxOxO)TS7 MS_Class=18
Mass test: TS0(xOOOxOxO)TS7 MS_Class=19
Mass test: TS0(xOOOxOxO)TS7 MS_Class=20
Mass test: TS0(xOOOxOxO)TS7 MS_Class=21
Mass test: TS0(xOOOxOxO)TS7 MS_Class=22
Mass test: TS0(xOOOxOxO)TS7 MS_Class=23
Mass test: TS0(xOOOxOxO)TS7 MS_Class=24
Mass test: TS0(xOOOxOxO)TS7 MS_Class=25
Mass test: TS0(xOOOxOxO)TS7 MS_Class=26
Mass test: TS0(xOOOxOxO)TS7 MS_Class=27
Mass test: TS0(xOOOxOxO)TS7 MS_Class=28
Mass test: TS0(xOOOxOxO)TS7 MS_Class=29
Mass test: TS0(xOOOxOxO)TS7 MS_Class=30
Mass test: TS0(xOOOxOxO)TS7 MS_Class=31
Mass test: TS0(xOOOxOxO)TS7 MS_Class=32
Mass test: TS0(xOOOxOxO)TS7 MS_Class=33
Mass test: TS0(xOOOxOxO)TS7 MS_Class=34
Mass test: TS0(xOOOxOxO)TS7 MS_Class=35
Mass test: TS0(xOOOxOxO)TS7 MS_Class=36
Mass test: TS0(xOOOxOxO)TS7 MS_Class=37
Mass test: TS0(xOOOxOxO)TS7 MS_Class=38
Mass test: TS0(xOOOxOxO)TS7 MS_Class=39
Mass test: TS0(xOOOxOxO)TS7 MS_Class=40
Mass test: TS0(xOOOxOxO)TS7 MS_Class=41
Mass test: TS0(xOOOxOxO)TS7 MS_Class=42
Mass test: TS0(xOOOxOxO)TS7 MS_Class=43
Mass test: TS0(xOOOxOxO)TS7 MS_Class=44
Mass test: TS0(xOOOxOxO)TS7 MS_Class=45
Mass test: TS0(xOOOxOOx)TS7 MS_Class=0
Mass test: TS0(xOOOxOOx)TS7 MS_Class=1
Mass test: TS0(xOOOxOOx)TS7 MS_Class=2
Mass test: TS0(xOOOxOOx)TS7 MS_Class=3
Mass test: TS0(xOOOxOOx)TS7 MS_Class=4
Mass test: TS0(xOOOxOOx)TS7 MS_Class=5
Mass test: TS0(xOOOxOOx)TS7 MS_Class=6
Mass test: TS0(xOOOxOOx)TS7 MS_Class=7
Mass test: TS0(xOOOxOOx)TS7 MS_Class=8
Mass test: TS0(xOOOxOOx)TS7 MS_Class=9
Mass test: TS0(xOOOxOOx)TS7 MS_Class=10
Mass test: TS0(xOOOxOOx)TS7 MS_Class=11
Mass test: TS0(xOOOxOOx)TS7 MS_Class=12
Mass test: TS0(xOOOxOOx)TS7 MS_Class=13
Mass test: TS0(xOOOxOOx)TS7 MS_Class=14
Mass test: TS0(xOOOxOOx)TS7 MS_Class=15
Mass test: TS0(xOOOxOOx)TS7 MS_Class=16
Mass test: TS0(xOOOxOOx)TS7 MS_Class=17
Mass test: TS0(xOOOxOOx)TS7 MS_Class=18
Mass test: TS0(xOOOxOOx)TS7 MS_Class=19
Mass test: TS0(xOOOxOOx)TS7 MS_Class=20
Mass test: TS0(xOOOxOOx)TS7 MS_Class=21
Mass test: TS0(xOOOxOOx)TS7 MS_Class=22
Mass test: TS0(xOOOxOOx)TS7 MS_Class=23
Mass test: TS0(xOOOxOOx)TS7 MS_Class=24
Mass test: TS0(xOOOxOOx)TS7 MS_Class=25
Mass test: TS0(xOOOxOOx)TS7 MS_Class=26
Mass test: TS0(xOOOxOOx)TS7 MS_Class=27
Mass test: TS0(xOOOxOOx)TS7 MS_Class=28
Mass test: TS0(xOOOxOOx)TS7 MS_Class=29
Mass test: TS0(xOOOxOOx)TS7 MS_Class=30
Mass test: TS0(xOOOxOOx)TS7 MS_Class=31
Mass test: TS0(xOOOxOOx)TS7 MS_Class=32
Mass test: TS0(xOOOxOOx)TS7 MS_Class=33
Mass test: TS0(xOOOxOOx)TS7 MS_Class=34
Mass test: TS0(xOOOxOOx)TS7 MS_Class=35
Mass test: TS0(xOOOxOOx)TS7 MS_Class=36
Mass test: TS0(xOOOxOOx)TS7 MS_Class=37
Mass test: TS0(xOOOxOOx)TS7 MS_Class=38
Mass test: TS0(xOOOxOOx)TS7 MS_Class=39
Mass test: TS0(xOOOxOOx)TS7 MS_Class=40
Mass test: TS0(xOOOxOOx)TS7 MS_Class=41
Mass test: TS0(xOOOxOOx)TS7 MS_Class=42
Mass test: TS0(xOOOxOOx)TS7 MS_Class=43
Mass test: TS0(xOOOxOOx)TS7 MS_Class=44
Mass test: TS0(xOOOxOOx)TS7 MS_Class=45
Mass test: TS0(xOOOxOOO)TS7 MS_Class=0
Mass test: TS0(xOOOxOOO)TS7 MS_Class=1
Mass test: TS0(xOOOxOOO)TS7 MS_Class=2
Mass test: TS0(xOOOxOOO)TS7 MS_Class=3
Mass test: TS0(xOOOxOOO)TS7 MS_Class=4
Mass test: TS0(xOOOxOOO)TS7 MS_Class=5
Mass test: TS0(xOOOxOOO)TS7 MS_Class=6
Mass test: TS0(xOOOxOOO)TS7 MS_Class=7
Mass test: TS0(xOOOxOOO)TS7 MS_Class=8
Mass test: TS0(xOOOxOOO)TS7 MS_Class=9
Mass test: TS0(xOOOxOOO)TS7 MS_Class=10
Mass test: TS0(xOOOxOOO)TS7 MS_Class=11
Mass test: TS0(xOOOxOOO)TS7 MS_Class=12
Mass test: TS0(xOOOxOOO)TS7 MS_Class=13
Mass test: TS0(xOOOxOOO)TS7 MS_Class=14
Mass test: TS0(xOOOxOOO)TS7 MS_Class=15
Mass test: TS0(xOOOxOOO)TS7 MS_Class=16
Mass test: TS0(xOOOxOOO)TS7 MS_Class=17
Mass test: TS0(xOOOxOOO)TS7 MS_Class=18
Mass test: TS0(xOOOxOOO)TS7 MS_Class=19
Mass test: TS0(xOOOxOOO)TS7 MS_Class=20
Mass test: TS0(xOOOxOOO)TS7 MS_Class=21
Mass test: TS0(xOOOxOOO)TS7 MS_Class=22
Mass test: TS0(xOOOxOOO)TS7 MS_Class=23
Mass test: TS0(xOOOxOOO)TS7 MS_Class=24
Mass test: TS0(xOOOxOOO)TS7 MS_Class=25
Mass test: TS0(xOOOxOOO)TS7 MS_Class=26
Mass test: TS0(xOOOxOOO)TS7 MS_Class=27
Mass test: TS0(xOOOxOOO)TS7 MS_Class=28
Mass test: TS0(xOOOxOOO)TS7 MS_Class=29
Mass test: TS0(xOOOxOOO)TS7 MS_Class=30
Mass test: TS0(xOOOxOOO)TS7 MS_Class=31
Mass test: TS0(xOOOxOOO)TS7 MS_Class=32
Mass test: TS0(xOOOxOOO)TS7 MS_Class=33
Mass test: TS0(xOOOxOOO)TS7 MS_Class=34
Mass test: TS0(xOOOxOOO)TS7 MS_Class=35
Mass test: TS0(xOOOxOOO)TS7 MS_Class=36
Mass test: TS0(xOOOxOOO)TS7 MS_Class=37
Mass test: TS0(xOOOxOOO)TS7 MS_Class=38
Mass test: TS0(xOOOxOOO)TS7 MS_Class=39
Mass test: TS0(xOOOxOOO)TS7 MS_Class=40
Mass test: TS0(xOOOxOOO)TS7 MS_Class=41
Mass test: TS0(xOOOxOOO)TS7 MS_Class=42
Mass test: TS0(xOOOxOOO)TS7 MS_Class=43
Mass test: TS0(xOOOxOOO)TS7 MS_Class=44
Mass test: TS0(xOOOxOOO)TS7 MS_Class=45
Mass test: TS0(xOOOOxxx)TS7 MS_Class=0
Mass test: TS0(xOOOOxxx)TS7 MS_Class=1
Mass test: TS0(xOOOOxxx)TS7 MS_Class=2
Mass test: TS0(xOOOOxxx)TS7 MS_Class=3
Mass test: TS0(xOOOOxxx)TS7 MS_Class=4
Mass test: TS0(xOOOOxxx)TS7 MS_Class=5
Mass test: TS0(xOOOOxxx)TS7 MS_Class=6
Mass test: TS0(xOOOOxxx)TS7 MS_Class=7
Mass test: TS0(xOOOOxxx)TS7 MS_Class=8
Mass test: TS0(xOOOOxxx)TS7 MS_Class=9
Mass test: TS0(xOOOOxxx)TS7 MS_Class=10
Mass test: TS0(xOOOOxxx)TS7 MS_Class=11
Mass test: TS0(xOOOOxxx)TS7 MS_Class=12
Mass test: TS0(xOOOOxxx)TS7 MS_Class=13
Mass test: TS0(xOOOOxxx)TS7 MS_Class=14
Mass test: TS0(xOOOOxxx)TS7 MS_Class=15
Mass test: TS0(xOOOOxxx)TS7 MS_Class=16
Mass test: TS0(xOOOOxxx)TS7 MS_Class=17
Mass test: TS0(xOOOOxxx)TS7 MS_Class=18
Mass test: TS0(xOOOOxxx)TS7 MS_Class=19
Mass test: TS0(xOOOOxxx)TS7 MS_Class=20
Mass test: TS0(xOOOOxxx)TS7 MS_Class=21
Mass test: TS0(xOOOOxxx)TS7 MS_Class=22
Mass test: TS0(xOOOOxxx)TS7 MS_Class=23
Mass test: TS0(xOOOOxxx)TS7 MS_Class=24
Mass test: TS0(xOOOOxxx)TS7 MS_Class=25
Mass test: TS0(xOOOOxxx)TS7 MS_Class=26
Mass test: TS0(xOOOOxxx)TS7 MS_Class=27
Mass test: TS0(xOOOOxxx)TS7 MS_Class=28
Mass test: TS0(xOOOOxxx)TS7 MS_Class=29
Mass test: TS0(xOOOOxxx)TS7 MS_Class=30
Mass test: TS0(xOOOOxxx)TS7 MS_Class=31
Mass test: TS0(xOOOOxxx)TS7 MS_Class=32
Mass test: TS0(xOOOOxxx)TS7 MS_Class=33
Mass test: TS0(xOOOOxxx)TS7 MS_Class=34
Mass test: TS0(xOOOOxxx)TS7 MS_Class=35
Mass test: TS0(xOOOOxxx)TS7 MS_Class=36
Mass test: TS0(xOOOOxxx)TS7 MS_Class=37
Mass test: TS0(xOOOOxxx)TS7 MS_Class=38
Mass test: TS0(xOOOOxxx)TS7 MS_Class=39
Mass test: TS0(xOOOOxxx)TS7 MS_Class=40
Mass test: TS0(xOOOOxxx)TS7 MS_Class=41
Mass test: TS0(xOOOOxxx)TS7 MS_Class=42
Mass test: TS0(xOOOOxxx)TS7 MS_Class=43
Mass test: TS0(xOOOOxxx)TS7 MS_Class=44
Mass test: TS0(xOOOOxxx)TS7 MS_Class=45
Mass test: TS0(xOOOOxxO)TS7 MS_Class=0
Mass test: TS0(xOOOOxxO)TS7 MS_Class=1
Mass test: TS0(xOOOOxxO)TS7 MS_Class=2
Mass test: TS0(xOOOOxxO)TS7 MS_Class=3
Mass test: TS0(xOOOOxxO)TS7 MS_Class=4
Mass test: TS0(xOOOOxxO)TS7 MS_Class=5
Mass test: TS0(xOOOOxxO)TS7 MS_Class=6
Mass test: TS0(xOOOOxxO)TS7 MS_Class=7
Mass test: TS0(xOOOOxxO)TS7 MS_Class=8
Mass test: TS0(xOOOOxxO)TS7 MS_Class=9
Mass test: TS0(xOOOOxxO)TS7 MS_Class=10
Mass test: TS0(xOOOOxxO)TS7 MS_Class=11
Mass test: TS0(xOOOOxxO)TS7 MS_Class=12
Mass test: TS0(xOOOOxxO)TS7 MS_Class=13
Mass test: TS0(xOOOOxxO)TS7 MS_Class=14
Mass test: TS0(xOOOOxxO)TS7 MS_Class=15
Mass test: TS0(xOOOOxxO)TS7 MS_Class=16
Mass test: TS0(xOOOOxxO)TS7 MS_Class=17
Mass test: TS0(xOOOOxxO)TS7 MS_Class=18
Mass test: TS0(xOOOOxxO)TS7 MS_Class=19
Mass test: TS0(xOOOOxxO)TS7 MS_Class=20
Mass test: TS0(xOOOOxxO)TS7 MS_Class=21
Mass test: TS0(xOOOOxxO)TS7 MS_Class=22
Mass test: TS0(xOOOOxxO)TS7 MS_Class=23
Mass test: TS0(xOOOOxxO)TS7 MS_Class=24
Mass test: TS0(xOOOOxxO)TS7 MS_Class=25
Mass test: TS0(xOOOOxxO)TS7 MS_Class=26
Mass test: TS0(xOOOOxxO)TS7 MS_Class=27
Mass test: TS0(xOOOOxxO)TS7 MS_Class=28
Mass test: TS0(xOOOOxxO)TS7 MS_Class=29
Mass test: TS0(xOOOOxxO)TS7 MS_Class=30
Mass test: TS0(xOOOOxxO)TS7 MS_Class=31
Mass test: TS0(xOOOOxxO)TS7 MS_Class=32
Mass test: TS0(xOOOOxxO)TS7 MS_Class=33
Mass test: TS0(xOOOOxxO)TS7 MS_Class=34
Mass test: TS0(xOOOOxxO)TS7 MS_Class=35
Mass test: TS0(xOOOOxxO)TS7 MS_Class=36
Mass test: TS0(xOOOOxxO)TS7 MS_Class=37
Mass test: TS0(xOOOOxxO)TS7 MS_Class=38
Mass test: TS0(xOOOOxxO)TS7 MS_Class=39
Mass test: TS0(xOOOOxxO)TS7 MS_Class=40
Mass test: TS0(xOOOOxxO)TS7 MS_Class=41
Mass test: TS0(xOOOOxxO)TS7 MS_Class=42
Mass test: TS0(xOOOOxxO)TS7 MS_Class=43
Mass test: TS0(xOOOOxxO)TS7 MS_Class=44
Mass test: TS0(xOOOOxxO)TS7 MS_Class=45
Mass test: TS0(xOOOOxOx)TS7 MS_Class=0
Mass test: TS0(xOOOOxOx)TS7 MS_Class=1
Mass test: TS0(xOOOOxOx)TS7 MS_Class=2
Mass test: TS0(xOOOOxOx)TS7 MS_Class=3
Mass test: TS0(xOOOOxOx)TS7 MS_Class=4
Mass test: TS0(xOOOOxOx)TS7 MS_Class=5
Mass test: TS0(xOOOOxOx)TS7 MS_Class=6
Mass test: TS0(xOOOOxOx)TS7 MS_Class=7
Mass test: TS0(xOOOOxOx)TS7 MS_Class=8
Mass test: TS0(xOOOOxOx)TS7 MS_Class=9
Mass test: TS0(xOOOOxOx)TS7 MS_Class=10
Mass test: TS0(xOOOOxOx)TS7 MS_Class=11
Mass test: TS0(xOOOOxOx)TS7 MS_Class=12
Mass test: TS0(xOOOOxOx)TS7 MS_Class=13
Mass test: TS0(xOOOOxOx)TS7 MS_Class=14
Mass test: TS0(xOOOOxOx)TS7 MS_Class=15
Mass test: TS0(xOOOOxOx)TS7 MS_Class=16
Mass test: TS0(xOOOOxOx)TS7 MS_Class=17
Mass test: TS0(xOOOOxOx)TS7 MS_Class=18
Mass test: TS0(xOOOOxOx)TS7 MS_Class=19
Mass test: TS0(xOOOOxOx)TS7 MS_Class=20
Mass test: TS0(xOOOOxOx)TS7 MS_Class=21
Mass test: TS0(xOOOOxOx)TS7 MS_Class=22
Mass test: TS0(xOOOOxOx)TS7 MS_Class=23
Mass test: TS0(xOOOOxOx)TS7 MS_Class=24
Mass test: TS0(xOOOOxOx)TS7 MS_Class=25
Mass test: TS0(xOOOOxOx)TS7 MS_Class=26
Mass test: TS0(xOOOOxOx)TS7 MS_Class=27
Mass test: TS0(xOOOOxOx)TS7 MS_Class=28
Mass test: TS0(xOOOOxOx)TS7 MS_Class=29
Mass test: TS0(xOOOOxOx)TS7 MS_Class=30
Mass test: TS0(xOOOOxOx)TS7 MS_Class=31
Mass test: TS0(xOOOOxOx)TS7 MS_Class=32
Mass test: TS0(xOOOOxOx)TS7 MS_Class=33
Mass test: TS0(xOOOOxOx)TS7 MS_Class=34
Mass test: TS0(xOOOOxOx)TS7 MS_Class=35
Mass test: TS0(xOOOOxOx)TS7 MS_Class=36
Mass test: TS0(xOOOOxOx)TS7 MS_Class=37
Mass test: TS0(xOOOOxOx)TS7 MS_Class=38
Mass test: TS0(xOOOOxOx)TS7 MS_Class=39
Mass test: TS0(xOOOOxOx)TS7 MS_Class=40
Mass test: TS0(xOOOOxOx)TS7 MS_Class=41
Mass test: TS0(xOOOOxOx)TS7 MS_Class=42
Mass test: TS0(xOOOOxOx)TS7 MS_Class=43
Mass test: TS0(xOOOOxOx)TS7 MS_Class=44
Mass test: TS0(xOOOOxOx)TS7 MS_Class=45
Mass test: TS0(xOOOOxOO)TS7 MS_Class=0
Mass test: TS0(xOOOOxOO)TS7 MS_Class=1
Mass test: TS0(xOOOOxOO)TS7 MS_Class=2
Mass test: TS0(xOOOOxOO)TS7 MS_Class=3
Mass test: TS0(xOOOOxOO)TS7 MS_Class=4
Mass test: TS0(xOOOOxOO)TS7 MS_Class=5
Mass test: TS0(xOOOOxOO)TS7 MS_Class=6
Mass test: TS0(xOOOOxOO)TS7 MS_Class=7
Mass test: TS0(xOOOOxOO)TS7 MS_Class=8
Mass test: TS0(xOOOOxOO)TS7 MS_Class=9
Mass test: TS0(xOOOOxOO)TS7 MS_Class=10
Mass test: TS0(xOOOOxOO)TS7 MS_Class=11
Mass test: TS0(xOOOOxOO)TS7 MS_Class=12
Mass test: TS0(xOOOOxOO)TS7 MS_Class=13
Mass test: TS0(xOOOOxOO)TS7 MS_Class=14
Mass test: TS0(xOOOOxOO)TS7 MS_Class=15
Mass test: TS0(xOOOOxOO)TS7 MS_Class=16
Mass test: TS0(xOOOOxOO)TS7 MS_Class=17
Mass test: TS0(xOOOOxOO)TS7 MS_Class=18
Mass test: TS0(xOOOOxOO)TS7 MS_Class=19
Mass test: TS0(xOOOOxOO)TS7 MS_Class=20
Mass test: TS0(xOOOOxOO)TS7 MS_Class=21
Mass test: TS0(xOOOOxOO)TS7 MS_Class=22
Mass test: TS0(xOOOOxOO)TS7 MS_Class=23
Mass test: TS0(xOOOOxOO)TS7 MS_Class=24
Mass test: TS0(xOOOOxOO)TS7 MS_Class=25
Mass test: TS0(xOOOOxOO)TS7 MS_Class=26
Mass test: TS0(xOOOOxOO)TS7 MS_Class=27
Mass test: TS0(xOOOOxOO)TS7 MS_Class=28
Mass test: TS0(xOOOOxOO)TS7 MS_Class=29
Mass test: TS0(xOOOOxOO)TS7 MS_Class=30
Mass test: TS0(xOOOOxOO)TS7 MS_Class=31
Mass test: TS0(xOOOOxOO)TS7 MS_Class=32
Mass test: TS0(xOOOOxOO)TS7 MS_Class=33
Mass test: TS0(xOOOOxOO)TS7 MS_Class=34
Mass test: TS0(xOOOOxOO)TS7 MS_Class=35
Mass test: TS0(xOOOOxOO)TS7 MS_Class=36
Mass test: TS0(xOOOOxOO)TS7 MS_Class=37
Mass test: TS0(xOOOOxOO)TS7 MS_Class=38
Mass test: TS0(xOOOOxOO)TS7 MS_Class=39
Mass test: TS0(xOOOOxOO)TS7 MS_Class=40
Mass test: TS0(xOOOOxOO)TS7 MS_Class=41
Mass test: TS0(xOOOOxOO)TS7 MS_Class=42
Mass test: TS0(xOOOOxOO)TS7 MS_Class=43
Mass test: TS0(xOOOOxOO)TS7 MS_Class=44
Mass test: TS0(xOOOOxOO)TS7 MS_Class=45
Mass test: TS0(xOOOOOxx)TS7 MS_Class=0
Mass test: TS0(xOOOOOxx)TS7 MS_Class=1
Mass test: TS0(xOOOOOxx)TS7 MS_Class=2
Mass test: TS0(xOOOOOxx)TS7 MS_Class=3
Mass test: TS0(xOOOOOxx)TS7 MS_Class=4
Mass test: TS0(xOOOOOxx)TS7 MS_Class=5
Mass test: TS0(xOOOOOxx)TS7 MS_Class=6
Mass test: TS0(xOOOOOxx)TS7 MS_Class=7
Mass test: TS0(xOOOOOxx)TS7 MS_Class=8
Mass test: TS0(xOOOOOxx)TS7 MS_Class=9
Mass test: TS0(xOOOOOxx)TS7 MS_Class=10
Mass test: TS0(xOOOOOxx)TS7 MS_Class=11
Mass test: TS0(xOOOOOxx)TS7 MS_Class=12
Mass test: TS0(xOOOOOxx)TS7 MS_Class=13
Mass test: TS0(xOOOOOxx)TS7 MS_Class=14
Mass test: TS0(xOOOOOxx)TS7 MS_Class=15
Mass test: TS0(xOOOOOxx)TS7 MS_Class=16
Mass test: TS0(xOOOOOxx)TS7 MS_Class=17
Mass test: TS0(xOOOOOxx)TS7 MS_Class=18
Mass test: TS0(xOOOOOxx)TS7 MS_Class=19
Mass test: TS0(xOOOOOxx)TS7 MS_Class=20
Mass test: TS0(xOOOOOxx)TS7 MS_Class=21
Mass test: TS0(xOOOOOxx)TS7 MS_Class=22
Mass test: TS0(xOOOOOxx)TS7 MS_Class=23
Mass test: TS0(xOOOOOxx)TS7 MS_Class=24
Mass test: TS0(xOOOOOxx)TS7 MS_Class=25
Mass test: TS0(xOOOOOxx)TS7 MS_Class=26
Mass test: TS0(xOOOOOxx)TS7 MS_Class=27
Mass test: TS0(xOOOOOxx)TS7 MS_Class=28
Mass test: TS0(xOOOOOxx)TS7 MS_Class=29
Mass test: TS0(xOOOOOxx)TS7 MS_Class=30
Mass test: TS0(xOOOOOxx)TS7 MS_Class=31
Mass test: TS0(xOOOOOxx)TS7 MS_Class=32
Mass test: TS0(xOOOOOxx)TS7 MS_Class=33
Mass test: TS0(xOOOOOxx)TS7 MS_Class=34
Mass test: TS0(xOOOOOxx)TS7 MS_Class=35
Mass test: TS0(xOOOOOxx)TS7 MS_Class=36
Mass test: TS0(xOOOOOxx)TS7 MS_Class=37
Mass test: TS0(xOOOOOxx)TS7 MS_Class=38
Mass test: TS0(xOOOOOxx)TS7 MS_Class=39
Mass test: TS0(xOOOOOxx)TS7 MS_Class=40
Mass test: TS0(xOOOOOxx)TS7 MS_Class=41
Mass test: TS0(xOOOOOxx)TS7 MS_Class=42
Mass test: TS0(xOOOOOxx)TS7 MS_Class=43
Mass test: TS0(xOOOOOxx)TS7 MS_Class=44
Mass test: TS0(xOOOOOxx)TS7 MS_Class=45
Mass test: TS0(xOOOOOxO)TS7 MS_Class=0
Mass test: TS0(xOOOOOxO)TS7 MS_Class=1
Mass test: TS0(xOOOOOxO)TS7 MS_Class=2
Mass test: TS0(xOOOOOxO)TS7 MS_Class=3
Mass test: TS0(xOOOOOxO)TS7 MS_Class=4
Mass test: TS0(xOOOOOxO)TS7 MS_Class=5
Mass test: TS0(xOOOOOxO)TS7 MS_Class=6
Mass test: TS0(xOOOOOxO)TS7 MS_Class=7
Mass test: TS0(xOOOOOxO)TS7 MS_Class=8
Mass test: TS0(xOOOOOxO)TS7 MS_Class=9
Mass test: TS0(xOOOOOxO)TS7 MS_Class=10
Mass test: TS0(xOOOOOxO)TS7 MS_Class=11
Mass test: TS0(xOOOOOxO)TS7 MS_Class=12
Mass test: TS0(xOOOOOxO)TS7 MS_Class=13
Mass test: TS0(xOOOOOxO)TS7 MS_Class=14
Mass test: TS0(xOOOOOxO)TS7 MS_Class=15
Mass test: TS0(xOOOOOxO)TS7 MS_Class=16
Mass test: TS0(xOOOOOxO)TS7 MS_Class=17
Mass test: TS0(xOOOOOxO)TS7 MS_Class=18
Mass test: TS0(xOOOOOxO)TS7 MS_Class=19
Mass test: TS0(xOOOOOxO)TS7 MS_Class=20
Mass test: TS0(xOOOOOxO)TS7 MS_Class=21
Mass test: TS0(xOOOOOxO)TS7 MS_Class=22
Mass test: TS0(xOOOOOxO)TS7 MS_Class=23
Mass test: TS0(xOOOOOxO)TS7 MS_Class=24
Mass test: TS0(xOOOOOxO)TS7 MS_Class=25
Mass test: TS0(xOOOOOxO)TS7 MS_Class=26
Mass test: TS0(xOOOOOxO)TS7 MS_Class=27
Mass test: TS0(xOOOOOxO)TS7 MS_Class=28
Mass test: TS0(xOOOOOxO)TS7 MS_Class=29
Mass test: TS0(xOOOOOxO)TS7 MS_Class=30
Mass test: TS0(xOOOOOxO)TS7 MS_Class=31
Mass test: TS0(xOOOOOxO)TS7 MS_Class=32
Mass test: TS0(xOOOOOxO)TS7 MS_Class=33
Mass test: TS0(xOOOOOxO)TS7 MS_Class=34
Mass test: TS0(xOOOOOxO)TS7 MS_Class=35
Mass test: TS0(xOOOOOxO)TS7 MS_Class=36
Mass test: TS0(xOOOOOxO)TS7 MS_Class=37
Mass test: TS0(xOOOOOxO)TS7 MS_Class=38
Mass test: TS0(xOOOOOxO)TS7 MS_Class=39
Mass test: TS0(xOOOOOxO)TS7 MS_Class=40
Mass test: TS0(xOOOOOxO)TS7 MS_Class=41
Mass test: TS0(xOOOOOxO)TS7 MS_Class=42
Mass test: TS0(xOOOOOxO)TS7 MS_Class=43
Mass test: TS0(xOOOOOxO)TS7 MS_Class=44
Mass test: TS0(xOOOOOxO)TS7 MS_Class=45
Mass test: TS0(xOOOOOOx)TS7 MS_Class=0
Mass test: TS0(xOOOOOOx)TS7 MS_Class=1
Mass test: TS0(xOOOOOOx)TS7 MS_Class=2
Mass test: TS0(xOOOOOOx)TS7 MS_Class=3
Mass test: TS0(xOOOOOOx)TS7 MS_Class=4
Mass test: TS0(xOOOOOOx)TS7 MS_Class=5
Mass test: TS0(xOOOOOOx)TS7 MS_Class=6
Mass test: TS0(xOOOOOOx)TS7 MS_Class=7
Mass test: TS0(xOOOOOOx)TS7 MS_Class=8
Mass test: TS0(xOOOOOOx)TS7 MS_Class=9
Mass test: TS0(xOOOOOOx)TS7 MS_Class=10
Mass test: TS0(xOOOOOOx)TS7 MS_Class=11
Mass test: TS0(xOOOOOOx)TS7 MS_Class=12
Mass test: TS0(xOOOOOOx)TS7 MS_Class=13
Mass test: TS0(xOOOOOOx)TS7 MS_Class=14
Mass test: TS0(xOOOOOOx)TS7 MS_Class=15
Mass test: TS0(xOOOOOOx)TS7 MS_Class=16
Mass test: TS0(xOOOOOOx)TS7 MS_Class=17
Mass test: TS0(xOOOOOOx)TS7 MS_Class=18
Mass test: TS0(xOOOOOOx)TS7 MS_Class=19
Mass test: TS0(xOOOOOOx)TS7 MS_Class=20
Mass test: TS0(xOOOOOOx)TS7 MS_Class=21
Mass test: TS0(xOOOOOOx)TS7 MS_Class=22
Mass test: TS0(xOOOOOOx)TS7 MS_Class=23
Mass test: TS0(xOOOOOOx)TS7 MS_Class=24
Mass test: TS0(xOOOOOOx)TS7 MS_Class=25
Mass test: TS0(xOOOOOOx)TS7 MS_Class=26
Mass test: TS0(xOOOOOOx)TS7 MS_Class=27
Mass test: TS0(xOOOOOOx)TS7 MS_Class=28
Mass test: TS0(xOOOOOOx)TS7 MS_Class=29
Mass test: TS0(xOOOOOOx)TS7 MS_Class=30
Mass test: TS0(xOOOOOOx)TS7 MS_Class=31
Mass test: TS0(xOOOOOOx)TS7 MS_Class=32
Mass test: TS0(xOOOOOOx)TS7 MS_Class=33
Mass test: TS0(xOOOOOOx)TS7 MS_Class=34
Mass test: TS0(xOOOOOOx)TS7 MS_Class=35
Mass test: TS0(xOOOOOOx)TS7 MS_Class=36
Mass test: TS0(xOOOOOOx)TS7 MS_Class=37
Mass test: TS0(xOOOOOOx)TS7 MS_Class=38
Mass test: TS0(xOOOOOOx)TS7 MS_Class=39
Mass test: TS0(xOOOOOOx)TS7 MS_Class=40
Mass test: TS0(xOOOOOOx)TS7 MS_Class=41
Mass test: TS0(xOOOOOOx)TS7 MS_Class=42
Mass test: TS0(xOOOOOOx)TS7 MS_Class=43
Mass test: TS0(xOOOOOOx)TS7 MS_Class=44
Mass test: TS0(xOOOOOOx)TS7 MS_Class=45
Mass test: TS0(xOOOOOOO)TS7 MS_Class=0
Mass test: TS0(xOOOOOOO)TS7 MS_Class=1
Mass test: TS0(xOOOOOOO)TS7 MS_Class=2
Mass test: TS0(xOOOOOOO)TS7 MS_Class=3
Mass test: TS0(xOOOOOOO)TS7 MS_Class=4
Mass test: TS0(xOOOOOOO)TS7 MS_Class=5
Mass test: TS0(xOOOOOOO)TS7 MS_Class=6
Mass test: TS0(xOOOOOOO)TS7 MS_Class=7
Mass test: TS0(xOOOOOOO)TS7 MS_Class=8
Mass test: TS0(xOOOOOOO)TS7 MS_Class=9
Mass test: TS0(xOOOOOOO)TS7 MS_Class=10
Mass test: TS0(xOOOOOOO)TS7 MS_Class=11
Mass test: TS0(xOOOOOOO)TS7 MS_Class=12
Mass test: TS0(xOOOOOOO)TS7 MS_Class=13
Mass test: TS0(xOOOOOOO)TS7 MS_Class=14
Mass test: TS0(xOOOOOOO)TS7 MS_Class=15
Mass test: TS0(xOOOOOOO)TS7 MS_Class=16
Mass test: TS0(xOOOOOOO)TS7 MS_Class=17
Mass test: TS0(xOOOOOOO)TS7 MS_Class=18
Mass test: TS0(xOOOOOOO)TS7 MS_Class=19
Mass test: TS0(xOOOOOOO)TS7 MS_Class=20
Mass test: TS0(xOOOOOOO)TS7 MS_Class=21
Mass test: TS0(xOOOOOOO)TS7 MS_Class=22
Mass test: TS0(xOOOOOOO)TS7 MS_Class=23
Mass test: TS0(xOOOOOOO)TS7 MS_Class=24
Mass test: TS0(xOOOOOOO)TS7 MS_Class=25
Mass test: TS0(xOOOOOOO)TS7 MS_Class=26
Mass test: TS0(xOOOOOOO)TS7 MS_Class=27
Mass test: TS0(xOOOOOOO)TS7 MS_Class=28
Mass test: TS0(xOOOOOOO)TS7 MS_Class=29
Mass test: TS0(xOOOOOOO)TS7 MS_Class=30
Mass test: TS0(xOOOOOOO)TS7 MS_Class=31
Mass test: TS0(xOOOOOOO)TS7 MS_Class=32
Mass test: TS0(xOOOOOOO)TS7 MS_Class=33
Mass test: TS0(xOOOOOOO)TS7 MS_Class=34
Mass test: TS0(xOOOOOOO)TS7 MS_Class=35
Mass test: TS0(xOOOOOOO)TS7 MS_Class=36
Mass test: TS0(xOOOOOOO)TS7 MS_Class=37
Mass test: TS0(xOOOOOOO)TS7 MS_Class=38
Mass test: TS0(xOOOOOOO)TS7 MS_Class=39
Mass test: TS0(xOOOOOOO)TS7 MS_Class=40
Mass test: TS0(xOOOOOOO)TS7 MS_Class=41
Mass test: TS0(xOOOOOOO)TS7 MS_Class=42
Mass test: TS0(xOOOOOOO)TS7 MS_Class=43
Mass test: TS0(xOOOOOOO)TS7 MS_Class=44
Mass test: TS0(xOOOOOOO)TS7 MS_Class=45
Mass test: TS0(Oxxxxxxx)TS7 MS_Class=0
Mass test: TS0(Oxxxxxxx)TS7 MS_Class=1
Mass test: TS0(Oxxxxxxx)TS7 MS_Class=2
Mass test: TS0(Oxxxxxxx)TS7 MS_Class=3
Mass test: TS0(Oxxxxxxx)TS7 MS_Class=4
Mass test: TS0(Oxxxxxxx)TS7 MS_Class=5
Mass test: TS0(Oxxxxxxx)TS7 MS_Class=6
Mass test: TS0(Oxxxxxxx)TS7 MS_Class=7
Mass test: TS0(Oxxxxxxx)TS7 MS_Class=8
Mass test: TS0(Oxxxxxxx)TS7 MS_Class=9
Mass test: TS0(Oxxxxxxx)TS7 MS_Class=10
Mass test: TS0(Oxxxxxxx)TS7 MS_Class=11
Mass test: TS0(Oxxxxxxx)TS7 MS_Class=12
Mass test: TS0(Oxxxxxxx)TS7 MS_Class=13
Mass test: TS0(Oxxxxxxx)TS7 MS_Class=14
Mass test: TS0(Oxxxxxxx)TS7 MS_Class=15
Mass test: TS0(Oxxxxxxx)TS7 MS_Class=16
Mass test: TS0(Oxxxxxxx)TS7 MS_Class=17
Mass test: TS0(Oxxxxxxx)TS7 MS_Class=18
Mass test: TS0(Oxxxxxxx)TS7 MS_Class=19
Mass test: TS0(Oxxxxxxx)TS7 MS_Class=20
Mass test: TS0(Oxxxxxxx)TS7 MS_Class=21
Mass test: TS0(Oxxxxxxx)TS7 MS_Class=22
Mass test: TS0(Oxxxxxxx)TS7 MS_Class=23
Mass test: TS0(Oxxxxxxx)TS7 MS_Class=24
Mass test: TS0(Oxxxxxxx)TS7 MS_Class=25
Mass test: TS0(Oxxxxxxx)TS7 MS_Class=26
Mass test: TS0(Oxxxxxxx)TS7 MS_Class=27
Mass test: TS0(Oxxxxxxx)TS7 MS_Class=28
Mass test: TS0(Oxxxxxxx)TS7 MS_Class=29
Mass test: TS0(Oxxxxxxx)TS7 MS_Class=30
Mass test: TS0(Oxxxxxxx)TS7 MS_Class=31
Mass test: TS0(Oxxxxxxx)TS7 MS_Class=32
Mass test: TS0(Oxxxxxxx)TS7 MS_Class=33
Mass test: TS0(Oxxxxxxx)TS7 MS_Class=34
Mass test: TS0(Oxxxxxxx)TS7 MS_Class=35
Mass test: TS0(Oxxxxxxx)TS7 MS_Class=36
Mass test: TS0(Oxxxxxxx)TS7 MS_Class=37
Mass test: TS0(Oxxxxxxx)TS7 MS_Class=38
Mass test: TS0(Oxxxxxxx)TS7 MS_Class=39
Mass test: TS0(Oxxxxxxx)TS7 MS_Class=40
Mass test: TS0(Oxxxxxxx)TS7 MS_Class=41
Mass test: TS0(Oxxxxxxx)TS7 MS_Class=42
Mass test: TS0(Oxxxxxxx)TS7 MS_Class=43
Mass test: TS0(Oxxxxxxx)TS7 MS_Class=44
Mass test: TS0(Oxxxxxxx)TS7 MS_Class=45
Mass test: TS0(OxxxxxxO)TS7 MS_Class=0
Mass test: TS0(OxxxxxxO)TS7 MS_Class=1
Mass test: TS0(OxxxxxxO)TS7 MS_Class=2
Mass test: TS0(OxxxxxxO)TS7 MS_Class=3
Mass test: TS0(OxxxxxxO)TS7 MS_Class=4
Mass test: TS0(OxxxxxxO)TS7 MS_Class=5
Mass test: TS0(OxxxxxxO)TS7 MS_Class=6
Mass test: TS0(OxxxxxxO)TS7 MS_Class=7
Mass test: TS0(OxxxxxxO)TS7 MS_Class=8
Mass test: TS0(OxxxxxxO)TS7 MS_Class=9
Mass test: TS0(OxxxxxxO)TS7 MS_Class=10
Mass test: TS0(OxxxxxxO)TS7 MS_Class=11
Mass test: TS0(OxxxxxxO)TS7 MS_Class=12
Mass test: TS0(OxxxxxxO)TS7 MS_Class=13
Mass test: TS0(OxxxxxxO)TS7 MS_Class=14
Mass test: TS0(OxxxxxxO)TS7 MS_Class=15
Mass test: TS0(OxxxxxxO)TS7 MS_Class=16
Mass test: TS0(OxxxxxxO)TS7 MS_Class=17
Mass test: TS0(OxxxxxxO)TS7 MS_Class=18
Mass test: TS0(OxxxxxxO)TS7 MS_Class=19
Mass test: TS0(OxxxxxxO)TS7 MS_Class=20
Mass test: TS0(OxxxxxxO)TS7 MS_Class=21
Mass test: TS0(OxxxxxxO)TS7 MS_Class=22
Mass test: TS0(OxxxxxxO)TS7 MS_Class=23
Mass test: TS0(OxxxxxxO)TS7 MS_Class=24
Mass test: TS0(OxxxxxxO)TS7 MS_Class=25
Mass test: TS0(OxxxxxxO)TS7 MS_Class=26
Mass test: TS0(OxxxxxxO)TS7 MS_Class=27
Mass test: TS0(OxxxxxxO)TS7 MS_Class=28
Mass test: TS0(OxxxxxxO)TS7 MS_Class=29
Mass test: TS0(OxxxxxxO)TS7 MS_Class=30
Mass test: TS0(OxxxxxxO)TS7 MS_Class=31
Mass test: TS0(OxxxxxxO)TS7 MS_Class=32
Mass test: TS0(OxxxxxxO)TS7 MS_Class=33
Mass test: TS0(OxxxxxxO)TS7 MS_Class=34
Mass test: TS0(OxxxxxxO)TS7 MS_Class=35
Mass test: TS0(OxxxxxxO)TS7 MS_Class=36
Mass test: TS0(OxxxxxxO)TS7 MS_Class=37
Mass test: TS0(OxxxxxxO)TS7 MS_Class=38
Mass test: TS0(OxxxxxxO)TS7 MS_Class=39
Mass test: TS0(OxxxxxxO)TS7 MS_Class=40
Mass test: TS0(OxxxxxxO)TS7 MS_Class=41
Mass test: TS0(OxxxxxxO)TS7 MS_Class=42
Mass test: TS0(OxxxxxxO)TS7 MS_Class=43
Mass test: TS0(OxxxxxxO)TS7 MS_Class=44
Mass test: TS0(OxxxxxxO)TS7 MS_Class=45
Mass test: TS0(OxxxxxOx)TS7 MS_Class=0
Mass test: TS0(OxxxxxOx)TS7 MS_Class=1
Mass test: TS0(OxxxxxOx)TS7 MS_Class=2
Mass test: TS0(OxxxxxOx)TS7 MS_Class=3
Mass test: TS0(OxxxxxOx)TS7 MS_Class=4
Mass test: TS0(OxxxxxOx)TS7 MS_Class=5
Mass test: TS0(OxxxxxOx)TS7 MS_Class=6
Mass test: TS0(OxxxxxOx)TS7 MS_Class=7
Mass test: TS0(OxxxxxOx)TS7 MS_Class=8
Mass test: TS0(OxxxxxOx)TS7 MS_Class=9
Mass test: TS0(OxxxxxOx)TS7 MS_Class=10
Mass test: TS0(OxxxxxOx)TS7 MS_Class=11
Mass test: TS0(OxxxxxOx)TS7 MS_Class=12
Mass test: TS0(OxxxxxOx)TS7 MS_Class=13
Mass test: TS0(OxxxxxOx)TS7 MS_Class=14
Mass test: TS0(OxxxxxOx)TS7 MS_Class=15
Mass test: TS0(OxxxxxOx)TS7 MS_Class=16
Mass test: TS0(OxxxxxOx)TS7 MS_Class=17
Mass test: TS0(OxxxxxOx)TS7 MS_Class=18
Mass test: TS0(OxxxxxOx)TS7 MS_Class=19
Mass test: TS0(OxxxxxOx)TS7 MS_Class=20
Mass test: TS0(OxxxxxOx)TS7 MS_Class=21
Mass test: TS0(OxxxxxOx)TS7 MS_Class=22
Mass test: TS0(OxxxxxOx)TS7 MS_Class=23
Mass test: TS0(OxxxxxOx)TS7 MS_Class=24
Mass test: TS0(OxxxxxOx)TS7 MS_Class=25
Mass test: TS0(OxxxxxOx)TS7 MS_Class=26
Mass test: TS0(OxxxxxOx)TS7 MS_Class=27
Mass test: TS0(OxxxxxOx)TS7 MS_Class=28
Mass test: TS0(OxxxxxOx)TS7 MS_Class=29
Mass test: TS0(OxxxxxOx)TS7 MS_Class=30
Mass test: TS0(OxxxxxOx)TS7 MS_Class=31
Mass test: TS0(OxxxxxOx)TS7 MS_Class=32
Mass test: TS0(OxxxxxOx)TS7 MS_Class=33
Mass test: TS0(OxxxxxOx)TS7 MS_Class=34
Mass test: TS0(OxxxxxOx)TS7 MS_Class=35
Mass test: TS0(OxxxxxOx)TS7 MS_Class=36
Mass test: TS0(OxxxxxOx)TS7 MS_Class=37
Mass test: TS0(OxxxxxOx)TS7 MS_Class=38
Mass test: TS0(OxxxxxOx)TS7 MS_Class=39
Mass test: TS0(OxxxxxOx)TS7 MS_Class=40
Mass test: TS0(OxxxxxOx)TS7 MS_Class=41
Mass test: TS0(OxxxxxOx)TS7 MS_Class=42
Mass test: TS0(OxxxxxOx)TS7 MS_Class=43
Mass test: TS0(OxxxxxOx)TS7 MS_Class=44
Mass test: TS0(OxxxxxOx)TS7 MS_Class=45
Mass test: TS0(OxxxxxOO)TS7 MS_Class=0
Mass test: TS0(OxxxxxOO)TS7 MS_Class=1
Mass test: TS0(OxxxxxOO)TS7 MS_Class=2
Mass test: TS0(OxxxxxOO)TS7 MS_Class=3
Mass test: TS0(OxxxxxOO)TS7 MS_Class=4
Mass test: TS0(OxxxxxOO)TS7 MS_Class=5
Mass test: TS0(OxxxxxOO)TS7 MS_Class=6
Mass test: TS0(OxxxxxOO)TS7 MS_Class=7
Mass test: TS0(OxxxxxOO)TS7 MS_Class=8
Mass test: TS0(OxxxxxOO)TS7 MS_Class=9
Mass test: TS0(OxxxxxOO)TS7 MS_Class=10
Mass test: TS0(OxxxxxOO)TS7 MS_Class=11
Mass test: TS0(OxxxxxOO)TS7 MS_Class=12
Mass test: TS0(OxxxxxOO)TS7 MS_Class=13
Mass test: TS0(OxxxxxOO)TS7 MS_Class=14
Mass test: TS0(OxxxxxOO)TS7 MS_Class=15
Mass test: TS0(OxxxxxOO)TS7 MS_Class=16
Mass test: TS0(OxxxxxOO)TS7 MS_Class=17
Mass test: TS0(OxxxxxOO)TS7 MS_Class=18
Mass test: TS0(OxxxxxOO)TS7 MS_Class=19
Mass test: TS0(OxxxxxOO)TS7 MS_Class=20
Mass test: TS0(OxxxxxOO)TS7 MS_Class=21
Mass test: TS0(OxxxxxOO)TS7 MS_Class=22
Mass test: TS0(OxxxxxOO)TS7 MS_Class=23
Mass test: TS0(OxxxxxOO)TS7 MS_Class=24
Mass test: TS0(OxxxxxOO)TS7 MS_Class=25
Mass test: TS0(OxxxxxOO)TS7 MS_Class=26
Mass test: TS0(OxxxxxOO)TS7 MS_Class=27
Mass test: TS0(OxxxxxOO)TS7 MS_Class=28
Mass test: TS0(OxxxxxOO)TS7 MS_Class=29
Mass test: TS0(OxxxxxOO)TS7 MS_Class=30
Mass test: TS0(OxxxxxOO)TS7 MS_Class=31
Mass test: TS0(OxxxxxOO)TS7 MS_Class=32
Mass test: TS0(OxxxxxOO)TS7 MS_Class=33
Mass test: TS0(OxxxxxOO)TS7 MS_Class=34
Mass test: TS0(OxxxxxOO)TS7 MS_Class=35
Mass test: TS0(OxxxxxOO)TS7 MS_Class=36
Mass test: TS0(OxxxxxOO)TS7 MS_Class=37
Mass test: TS0(OxxxxxOO)TS7 MS_Class=38
Mass test: TS0(OxxxxxOO)TS7 MS_Class=39
Mass test: TS0(OxxxxxOO)TS7 MS_Class=40
Mass test: TS0(OxxxxxOO)TS7 MS_Class=41
Mass test: TS0(OxxxxxOO)TS7 MS_Class=42
Mass test: TS0(OxxxxxOO)TS7 MS_Class=43
Mass test: TS0(OxxxxxOO)TS7 MS_Class=44
Mass test: TS0(OxxxxxOO)TS7 MS_Class=45
Mass test: TS0(OxxxxOxx)TS7 MS_Class=0
Mass test: TS0(OxxxxOxx)TS7 MS_Class=1
Mass test: TS0(OxxxxOxx)TS7 MS_Class=2
Mass test: TS0(OxxxxOxx)TS7 MS_Class=3
Mass test: TS0(OxxxxOxx)TS7 MS_Class=4
Mass test: TS0(OxxxxOxx)TS7 MS_Class=5
Mass test: TS0(OxxxxOxx)TS7 MS_Class=6
Mass test: TS0(OxxxxOxx)TS7 MS_Class=7
Mass test: TS0(OxxxxOxx)TS7 MS_Class=8
Mass test: TS0(OxxxxOxx)TS7 MS_Class=9
Mass test: TS0(OxxxxOxx)TS7 MS_Class=10
Mass test: TS0(OxxxxOxx)TS7 MS_Class=11
Mass test: TS0(OxxxxOxx)TS7 MS_Class=12
Mass test: TS0(OxxxxOxx)TS7 MS_Class=13
Mass test: TS0(OxxxxOxx)TS7 MS_Class=14
Mass test: TS0(OxxxxOxx)TS7 MS_Class=15
Mass test: TS0(OxxxxOxx)TS7 MS_Class=16
Mass test: TS0(OxxxxOxx)TS7 MS_Class=17
Mass test: TS0(OxxxxOxx)TS7 MS_Class=18
Mass test: TS0(OxxxxOxx)TS7 MS_Class=19
Mass test: TS0(OxxxxOxx)TS7 MS_Class=20
Mass test: TS0(OxxxxOxx)TS7 MS_Class=21
Mass test: TS0(OxxxxOxx)TS7 MS_Class=22
Mass test: TS0(OxxxxOxx)TS7 MS_Class=23
Mass test: TS0(OxxxxOxx)TS7 MS_Class=24
Mass test: TS0(OxxxxOxx)TS7 MS_Class=25
Mass test: TS0(OxxxxOxx)TS7 MS_Class=26
Mass test: TS0(OxxxxOxx)TS7 MS_Class=27
Mass test: TS0(OxxxxOxx)TS7 MS_Class=28
Mass test: TS0(OxxxxOxx)TS7 MS_Class=29
Mass test: TS0(OxxxxOxx)TS7 MS_Class=30
Mass test: TS0(OxxxxOxx)TS7 MS_Class=31
Mass test: TS0(OxxxxOxx)TS7 MS_Class=32
Mass test: TS0(OxxxxOxx)TS7 MS_Class=33
Mass test: TS0(OxxxxOxx)TS7 MS_Class=34
Mass test: TS0(OxxxxOxx)TS7 MS_Class=35
Mass test: TS0(OxxxxOxx)TS7 MS_Class=36
Mass test: TS0(OxxxxOxx)TS7 MS_Class=37
Mass test: TS0(OxxxxOxx)TS7 MS_Class=38
Mass test: TS0(OxxxxOxx)TS7 MS_Class=39
Mass test: TS0(OxxxxOxx)TS7 MS_Class=40
Mass test: TS0(OxxxxOxx)TS7 MS_Class=41
Mass test: TS0(OxxxxOxx)TS7 MS_Class=42
Mass test: TS0(OxxxxOxx)TS7 MS_Class=43
Mass test: TS0(OxxxxOxx)TS7 MS_Class=44
Mass test: TS0(OxxxxOxx)TS7 MS_Class=45
Mass test: TS0(OxxxxOxO)TS7 MS_Class=0
Mass test: TS0(OxxxxOxO)TS7 MS_Class=1
Mass test: TS0(OxxxxOxO)TS7 MS_Class=2
Mass test: TS0(OxxxxOxO)TS7 MS_Class=3
Mass test: TS0(OxxxxOxO)TS7 MS_Class=4
Mass test: TS0(OxxxxOxO)TS7 MS_Class=5
Mass test: TS0(OxxxxOxO)TS7 MS_Class=6
Mass test: TS0(OxxxxOxO)TS7 MS_Class=7
Mass test: TS0(OxxxxOxO)TS7 MS_Class=8
Mass test: TS0(OxxxxOxO)TS7 MS_Class=9
Mass test: TS0(OxxxxOxO)TS7 MS_Class=10
Mass test: TS0(OxxxxOxO)TS7 MS_Class=11
Mass test: TS0(OxxxxOxO)TS7 MS_Class=12
Mass test: TS0(OxxxxOxO)TS7 MS_Class=13
Mass test: TS0(OxxxxOxO)TS7 MS_Class=14
Mass test: TS0(OxxxxOxO)TS7 MS_Class=15
Mass test: TS0(OxxxxOxO)TS7 MS_Class=16
Mass test: TS0(OxxxxOxO)TS7 MS_Class=17
Mass test: TS0(OxxxxOxO)TS7 MS_Class=18
Mass test: TS0(OxxxxOxO)TS7 MS_Class=19
Mass test: TS0(OxxxxOxO)TS7 MS_Class=20
Mass test: TS0(OxxxxOxO)TS7 MS_Class=21
Mass test: TS0(OxxxxOxO)TS7 MS_Class=22
Mass test: TS0(OxxxxOxO)TS7 MS_Class=23
Mass test: TS0(OxxxxOxO)TS7 MS_Class=24
Mass test: TS0(OxxxxOxO)TS7 MS_Class=25
Mass test: TS0(OxxxxOxO)TS7 MS_Class=26
Mass test: TS0(OxxxxOxO)TS7 MS_Class=27
Mass test: TS0(OxxxxOxO)TS7 MS_Class=28
Mass test: TS0(OxxxxOxO)TS7 MS_Class=29
Mass test: TS0(OxxxxOxO)TS7 MS_Class=30
Mass test: TS0(OxxxxOxO)TS7 MS_Class=31
Mass test: TS0(OxxxxOxO)TS7 MS_Class=32
Mass test: TS0(OxxxxOxO)TS7 MS_Class=33
Mass test: TS0(OxxxxOxO)TS7 MS_Class=34
Mass test: TS0(OxxxxOxO)TS7 MS_Class=35
Mass test: TS0(OxxxxOxO)TS7 MS_Class=36
Mass test: TS0(OxxxxOxO)TS7 MS_Class=37
Mass test: TS0(OxxxxOxO)TS7 MS_Class=38
Mass test: TS0(OxxxxOxO)TS7 MS_Class=39
Mass test: TS0(OxxxxOxO)TS7 MS_Class=40
Mass test: TS0(OxxxxOxO)TS7 MS_Class=41
Mass test: TS0(OxxxxOxO)TS7 MS_Class=42
Mass test: TS0(OxxxxOxO)TS7 MS_Class=43
Mass test: TS0(OxxxxOxO)TS7 MS_Class=44
Mass test: TS0(OxxxxOxO)TS7 MS_Class=45
Mass test: TS0(OxxxxOOx)TS7 MS_Class=0
Mass test: TS0(OxxxxOOx)TS7 MS_Class=1
Mass test: TS0(OxxxxOOx)TS7 MS_Class=2
Mass test: TS0(OxxxxOOx)TS7 MS_Class=3
Mass test: TS0(OxxxxOOx)TS7 MS_Class=4
Mass test: TS0(OxxxxOOx)TS7 MS_Class=5
Mass test: TS0(OxxxxOOx)TS7 MS_Class=6
Mass test: TS0(OxxxxOOx)TS7 MS_Class=7
Mass test: TS0(OxxxxOOx)TS7 MS_Class=8
Mass test: TS0(OxxxxOOx)TS7 MS_Class=9
Mass test: TS0(OxxxxOOx)TS7 MS_Class=10
Mass test: TS0(OxxxxOOx)TS7 MS_Class=11
Mass test: TS0(OxxxxOOx)TS7 MS_Class=12
Mass test: TS0(OxxxxOOx)TS7 MS_Class=13
Mass test: TS0(OxxxxOOx)TS7 MS_Class=14
Mass test: TS0(OxxxxOOx)TS7 MS_Class=15
Mass test: TS0(OxxxxOOx)TS7 MS_Class=16
Mass test: TS0(OxxxxOOx)TS7 MS_Class=17
Mass test: TS0(OxxxxOOx)TS7 MS_Class=18
Mass test: TS0(OxxxxOOx)TS7 MS_Class=19
Mass test: TS0(OxxxxOOx)TS7 MS_Class=20
Mass test: TS0(OxxxxOOx)TS7 MS_Class=21
Mass test: TS0(OxxxxOOx)TS7 MS_Class=22
Mass test: TS0(OxxxxOOx)TS7 MS_Class=23
Mass test: TS0(OxxxxOOx)TS7 MS_Class=24
Mass test: TS0(OxxxxOOx)TS7 MS_Class=25
Mass test: TS0(OxxxxOOx)TS7 MS_Class=26
Mass test: TS0(OxxxxOOx)TS7 MS_Class=27
Mass test: TS0(OxxxxOOx)TS7 MS_Class=28
Mass test: TS0(OxxxxOOx)TS7 MS_Class=29
Mass test: TS0(OxxxxOOx)TS7 MS_Class=30
Mass test: TS0(OxxxxOOx)TS7 MS_Class=31
Mass test: TS0(OxxxxOOx)TS7 MS_Class=32
Mass test: TS0(OxxxxOOx)TS7 MS_Class=33
Mass test: TS0(OxxxxOOx)TS7 MS_Class=34
Mass test: TS0(OxxxxOOx)TS7 MS_Class=35
Mass test: TS0(OxxxxOOx)TS7 MS_Class=36
Mass test: TS0(OxxxxOOx)TS7 MS_Class=37
Mass test: TS0(OxxxxOOx)TS7 MS_Class=38
Mass test: TS0(OxxxxOOx)TS7 MS_Class=39
Mass test: TS0(OxxxxOOx)TS7 MS_Class=40
Mass test: TS0(OxxxxOOx)TS7 MS_Class=41
Mass test: TS0(OxxxxOOx)TS7 MS_Class=42
Mass test: TS0(OxxxxOOx)TS7 MS_Class=43
Mass test: TS0(OxxxxOOx)TS7 MS_Class=44
Mass test: TS0(OxxxxOOx)TS7 MS_Class=45
Mass test: TS0(OxxxxOOO)TS7 MS_Class=0
Mass test: TS0(OxxxxOOO)TS7 MS_Class=1
Mass test: TS0(OxxxxOOO)TS7 MS_Class=2
Mass test: TS0(OxxxxOOO)TS7 MS_Class=3
Mass test: TS0(OxxxxOOO)TS7 MS_Class=4
Mass test: TS0(OxxxxOOO)TS7 MS_Class=5
Mass test: TS0(OxxxxOOO)TS7 MS_Class=6
Mass test: TS0(OxxxxOOO)TS7 MS_Class=7
Mass test: TS0(OxxxxOOO)TS7 MS_Class=8
Mass test: TS0(OxxxxOOO)TS7 MS_Class=9
Mass test: TS0(OxxxxOOO)TS7 MS_Class=10
Mass test: TS0(OxxxxOOO)TS7 MS_Class=11
Mass test: TS0(OxxxxOOO)TS7 MS_Class=12
Mass test: TS0(OxxxxOOO)TS7 MS_Class=13
Mass test: TS0(OxxxxOOO)TS7 MS_Class=14
Mass test: TS0(OxxxxOOO)TS7 MS_Class=15
Mass test: TS0(OxxxxOOO)TS7 MS_Class=16
Mass test: TS0(OxxxxOOO)TS7 MS_Class=17
Mass test: TS0(OxxxxOOO)TS7 MS_Class=18
Mass test: TS0(OxxxxOOO)TS7 MS_Class=19
Mass test: TS0(OxxxxOOO)TS7 MS_Class=20
Mass test: TS0(OxxxxOOO)TS7 MS_Class=21
Mass test: TS0(OxxxxOOO)TS7 MS_Class=22
Mass test: TS0(OxxxxOOO)TS7 MS_Class=23
Mass test: TS0(OxxxxOOO)TS7 MS_Class=24
Mass test: TS0(OxxxxOOO)TS7 MS_Class=25
Mass test: TS0(OxxxxOOO)TS7 MS_Class=26
Mass test: TS0(OxxxxOOO)TS7 MS_Class=27
Mass test: TS0(OxxxxOOO)TS7 MS_Class=28
Mass test: TS0(OxxxxOOO)TS7 MS_Class=29
Mass test: TS0(OxxxxOOO)TS7 MS_Class=30
Mass test: TS0(OxxxxOOO)TS7 MS_Class=31
Mass test: TS0(OxxxxOOO)TS7 MS_Class=32
Mass test: TS0(OxxxxOOO)TS7 MS_Class=33
Mass test: TS0(OxxxxOOO)TS7 MS_Class=34
Mass test: TS0(OxxxxOOO)TS7 MS_Class=35
Mass test: TS0(OxxxxOOO)TS7 MS_Class=36
Mass test: TS0(OxxxxOOO)TS7 MS_Class=37
Mass test: TS0(OxxxxOOO)TS7 MS_Class=38
Mass test: TS0(OxxxxOOO)TS7 MS_Class=39
Mass test: TS0(OxxxxOOO)TS7 MS_Class=40
Mass test: TS0(OxxxxOOO)TS7 MS_Class=41
Mass test: TS0(OxxxxOOO)TS7 MS_Class=42
Mass test: TS0(OxxxxOOO)TS7 MS_Class=43
Mass test: TS0(OxxxxOOO)TS7 MS_Class=44
Mass test: TS0(OxxxxOOO)TS7 MS_Class=45
Mass test: TS0(OxxxOxxx)TS7 MS_Class=0
Mass test: TS0(OxxxOxxx)TS7 MS_Class=1
Mass test: TS0(OxxxOxxx)TS7 MS_Class=2
Mass test: TS0(OxxxOxxx)TS7 MS_Class=3
Mass test: TS0(OxxxOxxx)TS7 MS_Class=4
Mass test: TS0(OxxxOxxx)TS7 MS_Class=5
Mass test: TS0(OxxxOxxx)TS7 MS_Class=6
Mass test: TS0(OxxxOxxx)TS7 MS_Class=7
Mass test: TS0(OxxxOxxx)TS7 MS_Class=8
Mass test: TS0(OxxxOxxx)TS7 MS_Class=9
Mass test: TS0(OxxxOxxx)TS7 MS_Class=10
Mass test: TS0(OxxxOxxx)TS7 MS_Class=11
Mass test: TS0(OxxxOxxx)TS7 MS_Class=12
Mass test: TS0(OxxxOxxx)TS7 MS_Class=13
Mass test: TS0(OxxxOxxx)TS7 MS_Class=14
Mass test: TS0(OxxxOxxx)TS7 MS_Class=15
Mass test: TS0(OxxxOxxx)TS7 MS_Class=16
Mass test: TS0(OxxxOxxx)TS7 MS_Class=17
Mass test: TS0(OxxxOxxx)TS7 MS_Class=18
Mass test: TS0(OxxxOxxx)TS7 MS_Class=19
Mass test: TS0(OxxxOxxx)TS7 MS_Class=20
Mass test: TS0(OxxxOxxx)TS7 MS_Class=21
Mass test: TS0(OxxxOxxx)TS7 MS_Class=22
Mass test: TS0(OxxxOxxx)TS7 MS_Class=23
Mass test: TS0(OxxxOxxx)TS7 MS_Class=24
Mass test: TS0(OxxxOxxx)TS7 MS_Class=25
Mass test: TS0(OxxxOxxx)TS7 MS_Class=26
Mass test: TS0(OxxxOxxx)TS7 MS_Class=27
Mass test: TS0(OxxxOxxx)TS7 MS_Class=28
Mass test: TS0(OxxxOxxx)TS7 MS_Class=29
Mass test: TS0(OxxxOxxx)TS7 MS_Class=30
Mass test: TS0(OxxxOxxx)TS7 MS_Class=31
Mass test: TS0(OxxxOxxx)TS7 MS_Class=32
Mass test: TS0(OxxxOxxx)TS7 MS_Class=33
Mass test: TS0(OxxxOxxx)TS7 MS_Class=34
Mass test: TS0(OxxxOxxx)TS7 MS_Class=35
Mass test: TS0(OxxxOxxx)TS7 MS_Class=36
Mass test: TS0(OxxxOxxx)TS7 MS_Class=37
Mass test: TS0(OxxxOxxx)TS7 MS_Class=38
Mass test: TS0(OxxxOxxx)TS7 MS_Class=39
Mass test: TS0(OxxxOxxx)TS7 MS_Class=40
Mass test: TS0(OxxxOxxx)TS7 MS_Class=41
Mass test: TS0(OxxxOxxx)TS7 MS_Class=42
Mass test: TS0(OxxxOxxx)TS7 MS_Class=43
Mass test: TS0(OxxxOxxx)TS7 MS_Class=44
Mass test: TS0(OxxxOxxx)TS7 MS_Class=45
Mass test: TS0(OxxxOxxO)TS7 MS_Class=0
Mass test: TS0(OxxxOxxO)TS7 MS_Class=1
Mass test: TS0(OxxxOxxO)TS7 MS_Class=2
Mass test: TS0(OxxxOxxO)TS7 MS_Class=3
Mass test: TS0(OxxxOxxO)TS7 MS_Class=4
Mass test: TS0(OxxxOxxO)TS7 MS_Class=5
Mass test: TS0(OxxxOxxO)TS7 MS_Class=6
Mass test: TS0(OxxxOxxO)TS7 MS_Class=7
Mass test: TS0(OxxxOxxO)TS7 MS_Class=8
Mass test: TS0(OxxxOxxO)TS7 MS_Class=9
Mass test: TS0(OxxxOxxO)TS7 MS_Class=10
Mass test: TS0(OxxxOxxO)TS7 MS_Class=11
Mass test: TS0(OxxxOxxO)TS7 MS_Class=12
Mass test: TS0(OxxxOxxO)TS7 MS_Class=13
Mass test: TS0(OxxxOxxO)TS7 MS_Class=14
Mass test: TS0(OxxxOxxO)TS7 MS_Class=15
Mass test: TS0(OxxxOxxO)TS7 MS_Class=16
Mass test: TS0(OxxxOxxO)TS7 MS_Class=17
Mass test: TS0(OxxxOxxO)TS7 MS_Class=18
Mass test: TS0(OxxxOxxO)TS7 MS_Class=19
Mass test: TS0(OxxxOxxO)TS7 MS_Class=20
Mass test: TS0(OxxxOxxO)TS7 MS_Class=21
Mass test: TS0(OxxxOxxO)TS7 MS_Class=22
Mass test: TS0(OxxxOxxO)TS7 MS_Class=23
Mass test: TS0(OxxxOxxO)TS7 MS_Class=24
Mass test: TS0(OxxxOxxO)TS7 MS_Class=25
Mass test: TS0(OxxxOxxO)TS7 MS_Class=26
Mass test: TS0(OxxxOxxO)TS7 MS_Class=27
Mass test: TS0(OxxxOxxO)TS7 MS_Class=28
Mass test: TS0(OxxxOxxO)TS7 MS_Class=29
Mass test: TS0(OxxxOxxO)TS7 MS_Class=30
Mass test: TS0(OxxxOxxO)TS7 MS_Class=31
Mass test: TS0(OxxxOxxO)TS7 MS_Class=32
Mass test: TS0(OxxxOxxO)TS7 MS_Class=33
Mass test: TS0(OxxxOxxO)TS7 MS_Class=34
Mass test: TS0(OxxxOxxO)TS7 MS_Class=35
Mass test: TS0(OxxxOxxO)TS7 MS_Class=36
Mass test: TS0(OxxxOxxO)TS7 MS_Class=37
Mass test: TS0(OxxxOxxO)TS7 MS_Class=38
Mass test: TS0(OxxxOxxO)TS7 MS_Class=39
Mass test: TS0(OxxxOxxO)TS7 MS_Class=40
Mass test: TS0(OxxxOxxO)TS7 MS_Class=41
Mass test: TS0(OxxxOxxO)TS7 MS_Class=42
Mass test: TS0(OxxxOxxO)TS7 MS_Class=43
Mass test: TS0(OxxxOxxO)TS7 MS_Class=44
Mass test: TS0(OxxxOxxO)TS7 MS_Class=45
Mass test: TS0(OxxxOxOx)TS7 MS_Class=0
Mass test: TS0(OxxxOxOx)TS7 MS_Class=1
Mass test: TS0(OxxxOxOx)TS7 MS_Class=2
Mass test: TS0(OxxxOxOx)TS7 MS_Class=3
Mass test: TS0(OxxxOxOx)TS7 MS_Class=4
Mass test: TS0(OxxxOxOx)TS7 MS_Class=5
Mass test: TS0(OxxxOxOx)TS7 MS_Class=6
Mass test: TS0(OxxxOxOx)TS7 MS_Class=7
Mass test: TS0(OxxxOxOx)TS7 MS_Class=8
Mass test: TS0(OxxxOxOx)TS7 MS_Class=9
Mass test: TS0(OxxxOxOx)TS7 MS_Class=10
Mass test: TS0(OxxxOxOx)TS7 MS_Class=11
Mass test: TS0(OxxxOxOx)TS7 MS_Class=12
Mass test: TS0(OxxxOxOx)TS7 MS_Class=13
Mass test: TS0(OxxxOxOx)TS7 MS_Class=14
Mass test: TS0(OxxxOxOx)TS7 MS_Class=15
Mass test: TS0(OxxxOxOx)TS7 MS_Class=16
Mass test: TS0(OxxxOxOx)TS7 MS_Class=17
Mass test: TS0(OxxxOxOx)TS7 MS_Class=18
Mass test: TS0(OxxxOxOx)TS7 MS_Class=19
Mass test: TS0(OxxxOxOx)TS7 MS_Class=20
Mass test: TS0(OxxxOxOx)TS7 MS_Class=21
Mass test: TS0(OxxxOxOx)TS7 MS_Class=22
Mass test: TS0(OxxxOxOx)TS7 MS_Class=23
Mass test: TS0(OxxxOxOx)TS7 MS_Class=24
Mass test: TS0(OxxxOxOx)TS7 MS_Class=25
Mass test: TS0(OxxxOxOx)TS7 MS_Class=26
Mass test: TS0(OxxxOxOx)TS7 MS_Class=27
Mass test: TS0(OxxxOxOx)TS7 MS_Class=28
Mass test: TS0(OxxxOxOx)TS7 MS_Class=29
Mass test: TS0(OxxxOxOx)TS7 MS_Class=30
Mass test: TS0(OxxxOxOx)TS7 MS_Class=31
Mass test: TS0(OxxxOxOx)TS7 MS_Class=32
Mass test: TS0(OxxxOxOx)TS7 MS_Class=33
Mass test: TS0(OxxxOxOx)TS7 MS_Class=34
Mass test: TS0(OxxxOxOx)TS7 MS_Class=35
Mass test: TS0(OxxxOxOx)TS7 MS_Class=36
Mass test: TS0(OxxxOxOx)TS7 MS_Class=37
Mass test: TS0(OxxxOxOx)TS7 MS_Class=38
Mass test: TS0(OxxxOxOx)TS7 MS_Class=39
Mass test: TS0(OxxxOxOx)TS7 MS_Class=40
Mass test: TS0(OxxxOxOx)TS7 MS_Class=41
Mass test: TS0(OxxxOxOx)TS7 MS_Class=42
Mass test: TS0(OxxxOxOx)TS7 MS_Class=43
Mass test: TS0(OxxxOxOx)TS7 MS_Class=44
Mass test: TS0(OxxxOxOx)TS7 MS_Class=45
Mass test: TS0(OxxxOxOO)TS7 MS_Class=0
Mass test: TS0(OxxxOxOO)TS7 MS_Class=1
Mass test: TS0(OxxxOxOO)TS7 MS_Class=2
Mass test: TS0(OxxxOxOO)TS7 MS_Class=3
Mass test: TS0(OxxxOxOO)TS7 MS_Class=4
Mass test: TS0(OxxxOxOO)TS7 MS_Class=5
Mass test: TS0(OxxxOxOO)TS7 MS_Class=6
Mass test: TS0(OxxxOxOO)TS7 MS_Class=7
Mass test: TS0(OxxxOxOO)TS7 MS_Class=8
Mass test: TS0(OxxxOxOO)TS7 MS_Class=9
Mass test: TS0(OxxxOxOO)TS7 MS_Class=10
Mass test: TS0(OxxxOxOO)TS7 MS_Class=11
Mass test: TS0(OxxxOxOO)TS7 MS_Class=12
Mass test: TS0(OxxxOxOO)TS7 MS_Class=13
Mass test: TS0(OxxxOxOO)TS7 MS_Class=14
Mass test: TS0(OxxxOxOO)TS7 MS_Class=15
Mass test: TS0(OxxxOxOO)TS7 MS_Class=16
Mass test: TS0(OxxxOxOO)TS7 MS_Class=17
Mass test: TS0(OxxxOxOO)TS7 MS_Class=18
Mass test: TS0(OxxxOxOO)TS7 MS_Class=19
Mass test: TS0(OxxxOxOO)TS7 MS_Class=20
Mass test: TS0(OxxxOxOO)TS7 MS_Class=21
Mass test: TS0(OxxxOxOO)TS7 MS_Class=22
Mass test: TS0(OxxxOxOO)TS7 MS_Class=23
Mass test: TS0(OxxxOxOO)TS7 MS_Class=24
Mass test: TS0(OxxxOxOO)TS7 MS_Class=25
Mass test: TS0(OxxxOxOO)TS7 MS_Class=26
Mass test: TS0(OxxxOxOO)TS7 MS_Class=27
Mass test: TS0(OxxxOxOO)TS7 MS_Class=28
Mass test: TS0(OxxxOxOO)TS7 MS_Class=29
Mass test: TS0(OxxxOxOO)TS7 MS_Class=30
Mass test: TS0(OxxxOxOO)TS7 MS_Class=31
Mass test: TS0(OxxxOxOO)TS7 MS_Class=32
Mass test: TS0(OxxxOxOO)TS7 MS_Class=33
Mass test: TS0(OxxxOxOO)TS7 MS_Class=34
Mass test: TS0(OxxxOxOO)TS7 MS_Class=35
Mass test: TS0(OxxxOxOO)TS7 MS_Class=36
Mass test: TS0(OxxxOxOO)TS7 MS_Class=37
Mass test: TS0(OxxxOxOO)TS7 MS_Class=38
Mass test: TS0(OxxxOxOO)TS7 MS_Class=39
Mass test: TS0(OxxxOxOO)TS7 MS_Class=40
Mass test: TS0(OxxxOxOO)TS7 MS_Class=41
Mass test: TS0(OxxxOxOO)TS7 MS_Class=42
Mass test: TS0(OxxxOxOO)TS7 MS_Class=43
Mass test: TS0(OxxxOxOO)TS7 MS_Class=44
Mass test: TS0(OxxxOxOO)TS7 MS_Class=45
Mass test: TS0(OxxxOOxx)TS7 MS_Class=0
Mass test: TS0(OxxxOOxx)TS7 MS_Class=1
Mass test: TS0(OxxxOOxx)TS7 MS_Class=2
Mass test: TS0(OxxxOOxx)TS7 MS_Class=3
Mass test: TS0(OxxxOOxx)TS7 MS_Class=4
Mass test: TS0(OxxxOOxx)TS7 MS_Class=5
Mass test: TS0(OxxxOOxx)TS7 MS_Class=6
Mass test: TS0(OxxxOOxx)TS7 MS_Class=7
Mass test: TS0(OxxxOOxx)TS7 MS_Class=8
Mass test: TS0(OxxxOOxx)TS7 MS_Class=9
Mass test: TS0(OxxxOOxx)TS7 MS_Class=10
Mass test: TS0(OxxxOOxx)TS7 MS_Class=11
Mass test: TS0(OxxxOOxx)TS7 MS_Class=12
Mass test: TS0(OxxxOOxx)TS7 MS_Class=13
Mass test: TS0(OxxxOOxx)TS7 MS_Class=14
Mass test: TS0(OxxxOOxx)TS7 MS_Class=15
Mass test: TS0(OxxxOOxx)TS7 MS_Class=16
Mass test: TS0(OxxxOOxx)TS7 MS_Class=17
Mass test: TS0(OxxxOOxx)TS7 MS_Class=18
Mass test: TS0(OxxxOOxx)TS7 MS_Class=19
Mass test: TS0(OxxxOOxx)TS7 MS_Class=20
Mass test: TS0(OxxxOOxx)TS7 MS_Class=21
Mass test: TS0(OxxxOOxx)TS7 MS_Class=22
Mass test: TS0(OxxxOOxx)TS7 MS_Class=23
Mass test: TS0(OxxxOOxx)TS7 MS_Class=24
Mass test: TS0(OxxxOOxx)TS7 MS_Class=25
Mass test: TS0(OxxxOOxx)TS7 MS_Class=26
Mass test: TS0(OxxxOOxx)TS7 MS_Class=27
Mass test: TS0(OxxxOOxx)TS7 MS_Class=28
Mass test: TS0(OxxxOOxx)TS7 MS_Class=29
Mass test: TS0(OxxxOOxx)TS7 MS_Class=30
Mass test: TS0(OxxxOOxx)TS7 MS_Class=31
Mass test: TS0(OxxxOOxx)TS7 MS_Class=32
Mass test: TS0(OxxxOOxx)TS7 MS_Class=33
Mass test: TS0(OxxxOOxx)TS7 MS_Class=34
Mass test: TS0(OxxxOOxx)TS7 MS_Class=35
Mass test: TS0(OxxxOOxx)TS7 MS_Class=36
Mass test: TS0(OxxxOOxx)TS7 MS_Class=37
Mass test: TS0(OxxxOOxx)TS7 MS_Class=38
Mass test: TS0(OxxxOOxx)TS7 MS_Class=39
Mass test: TS0(OxxxOOxx)TS7 MS_Class=40
Mass test: TS0(OxxxOOxx)TS7 MS_Class=41
Mass test: TS0(OxxxOOxx)TS7 MS_Class=42
Mass test: TS0(OxxxOOxx)TS7 MS_Class=43
Mass test: TS0(OxxxOOxx)TS7 MS_Class=44
Mass test: TS0(OxxxOOxx)TS7 MS_Class=45
Mass test: TS0(OxxxOOxO)TS7 MS_Class=0
Mass test: TS0(OxxxOOxO)TS7 MS_Class=1
Mass test: TS0(OxxxOOxO)TS7 MS_Class=2
Mass test: TS0(OxxxOOxO)TS7 MS_Class=3
Mass test: TS0(OxxxOOxO)TS7 MS_Class=4
Mass test: TS0(OxxxOOxO)TS7 MS_Class=5
Mass test: TS0(OxxxOOxO)TS7 MS_Class=6
Mass test: TS0(OxxxOOxO)TS7 MS_Class=7
Mass test: TS0(OxxxOOxO)TS7 MS_Class=8
Mass test: TS0(OxxxOOxO)TS7 MS_Class=9
Mass test: TS0(OxxxOOxO)TS7 MS_Class=10
Mass test: TS0(OxxxOOxO)TS7 MS_Class=11
Mass test: TS0(OxxxOOxO)TS7 MS_Class=12
Mass test: TS0(OxxxOOxO)TS7 MS_Class=13
Mass test: TS0(OxxxOOxO)TS7 MS_Class=14
Mass test: TS0(OxxxOOxO)TS7 MS_Class=15
Mass test: TS0(OxxxOOxO)TS7 MS_Class=16
Mass test: TS0(OxxxOOxO)TS7 MS_Class=17
Mass test: TS0(OxxxOOxO)TS7 MS_Class=18
Mass test: TS0(OxxxOOxO)TS7 MS_Class=19
Mass test: TS0(OxxxOOxO)TS7 MS_Class=20
Mass test: TS0(OxxxOOxO)TS7 MS_Class=21
Mass test: TS0(OxxxOOxO)TS7 MS_Class=22
Mass test: TS0(OxxxOOxO)TS7 MS_Class=23
Mass test: TS0(OxxxOOxO)TS7 MS_Class=24
Mass test: TS0(OxxxOOxO)TS7 MS_Class=25
Mass test: TS0(OxxxOOxO)TS7 MS_Class=26
Mass test: TS0(OxxxOOxO)TS7 MS_Class=27
Mass test: TS0(OxxxOOxO)TS7 MS_Class=28
Mass test: TS0(OxxxOOxO)TS7 MS_Class=29
Mass test: TS0(OxxxOOxO)TS7 MS_Class=30
Mass test: TS0(OxxxOOxO)TS7 MS_Class=31
Mass test: TS0(OxxxOOxO)TS7 MS_Class=32
Mass test: TS0(OxxxOOxO)TS7 MS_Class=33
Mass test: TS0(OxxxOOxO)TS7 MS_Class=34
Mass test: TS0(OxxxOOxO)TS7 MS_Class=35
Mass test: TS0(OxxxOOxO)TS7 MS_Class=36
Mass test: TS0(OxxxOOxO)TS7 MS_Class=37
Mass test: TS0(OxxxOOxO)TS7 MS_Class=38
Mass test: TS0(OxxxOOxO)TS7 MS_Class=39
Mass test: TS0(OxxxOOxO)TS7 MS_Class=40
Mass test: TS0(OxxxOOxO)TS7 MS_Class=41
Mass test: TS0(OxxxOOxO)TS7 MS_Class=42
Mass test: TS0(OxxxOOxO)TS7 MS_Class=43
Mass test: TS0(OxxxOOxO)TS7 MS_Class=44
Mass test: TS0(OxxxOOxO)TS7 MS_Class=45
Mass test: TS0(OxxxOOOx)TS7 MS_Class=0
Mass test: TS0(OxxxOOOx)TS7 MS_Class=1
Mass test: TS0(OxxxOOOx)TS7 MS_Class=2
Mass test: TS0(OxxxOOOx)TS7 MS_Class=3
Mass test: TS0(OxxxOOOx)TS7 MS_Class=4
Mass test: TS0(OxxxOOOx)TS7 MS_Class=5
Mass test: TS0(OxxxOOOx)TS7 MS_Class=6
Mass test: TS0(OxxxOOOx)TS7 MS_Class=7
Mass test: TS0(OxxxOOOx)TS7 MS_Class=8
Mass test: TS0(OxxxOOOx)TS7 MS_Class=9
Mass test: TS0(OxxxOOOx)TS7 MS_Class=10
Mass test: TS0(OxxxOOOx)TS7 MS_Class=11
Mass test: TS0(OxxxOOOx)TS7 MS_Class=12
Mass test: TS0(OxxxOOOx)TS7 MS_Class=13
Mass test: TS0(OxxxOOOx)TS7 MS_Class=14
Mass test: TS0(OxxxOOOx)TS7 MS_Class=15
Mass test: TS0(OxxxOOOx)TS7 MS_Class=16
Mass test: TS0(OxxxOOOx)TS7 MS_Class=17
Mass test: TS0(OxxxOOOx)TS7 MS_Class=18
Mass test: TS0(OxxxOOOx)TS7 MS_Class=19
Mass test: TS0(OxxxOOOx)TS7 MS_Class=20
Mass test: TS0(OxxxOOOx)TS7 MS_Class=21
Mass test: TS0(OxxxOOOx)TS7 MS_Class=22
Mass test: TS0(OxxxOOOx)TS7 MS_Class=23
Mass test: TS0(OxxxOOOx)TS7 MS_Class=24
Mass test: TS0(OxxxOOOx)TS7 MS_Class=25
Mass test: TS0(OxxxOOOx)TS7 MS_Class=26
Mass test: TS0(OxxxOOOx)TS7 MS_Class=27
Mass test: TS0(OxxxOOOx)TS7 MS_Class=28
Mass test: TS0(OxxxOOOx)TS7 MS_Class=29
Mass test: TS0(OxxxOOOx)TS7 MS_Class=30
Mass test: TS0(OxxxOOOx)TS7 MS_Class=31
Mass test: TS0(OxxxOOOx)TS7 MS_Class=32
Mass test: TS0(OxxxOOOx)TS7 MS_Class=33
Mass test: TS0(OxxxOOOx)TS7 MS_Class=34
Mass test: TS0(OxxxOOOx)TS7 MS_Class=35
Mass test: TS0(OxxxOOOx)TS7 MS_Class=36
Mass test: TS0(OxxxOOOx)TS7 MS_Class=37
Mass test: TS0(OxxxOOOx)TS7 MS_Class=38
Mass test: TS0(OxxxOOOx)TS7 MS_Class=39
Mass test: TS0(OxxxOOOx)TS7 MS_Class=40
Mass test: TS0(OxxxOOOx)TS7 MS_Class=41
Mass test: TS0(OxxxOOOx)TS7 MS_Class=42
Mass test: TS0(OxxxOOOx)TS7 MS_Class=43
Mass test: TS0(OxxxOOOx)TS7 MS_Class=44
Mass test: TS0(OxxxOOOx)TS7 MS_Class=45
Mass test: TS0(OxxxOOOO)TS7 MS_Class=0
Mass test: TS0(OxxxOOOO)TS7 MS_Class=1
Mass test: TS0(OxxxOOOO)TS7 MS_Class=2
Mass test: TS0(OxxxOOOO)TS7 MS_Class=3
Mass test: TS0(OxxxOOOO)TS7 MS_Class=4
Mass test: TS0(OxxxOOOO)TS7 MS_Class=5
Mass test: TS0(OxxxOOOO)TS7 MS_Class=6
Mass test: TS0(OxxxOOOO)TS7 MS_Class=7
Mass test: TS0(OxxxOOOO)TS7 MS_Class=8
Mass test: TS0(OxxxOOOO)TS7 MS_Class=9
Mass test: TS0(OxxxOOOO)TS7 MS_Class=10
Mass test: TS0(OxxxOOOO)TS7 MS_Class=11
Mass test: TS0(OxxxOOOO)TS7 MS_Class=12
Mass test: TS0(OxxxOOOO)TS7 MS_Class=13
Mass test: TS0(OxxxOOOO)TS7 MS_Class=14
Mass test: TS0(OxxxOOOO)TS7 MS_Class=15
Mass test: TS0(OxxxOOOO)TS7 MS_Class=16
Mass test: TS0(OxxxOOOO)TS7 MS_Class=17
Mass test: TS0(OxxxOOOO)TS7 MS_Class=18
Mass test: TS0(OxxxOOOO)TS7 MS_Class=19
Mass test: TS0(OxxxOOOO)TS7 MS_Class=20
Mass test: TS0(OxxxOOOO)TS7 MS_Class=21
Mass test: TS0(OxxxOOOO)TS7 MS_Class=22
Mass test: TS0(OxxxOOOO)TS7 MS_Class=23
Mass test: TS0(OxxxOOOO)TS7 MS_Class=24
Mass test: TS0(OxxxOOOO)TS7 MS_Class=25
Mass test: TS0(OxxxOOOO)TS7 MS_Class=26
Mass test: TS0(OxxxOOOO)TS7 MS_Class=27
Mass test: TS0(OxxxOOOO)TS7 MS_Class=28
Mass test: TS0(OxxxOOOO)TS7 MS_Class=29
Mass test: TS0(OxxxOOOO)TS7 MS_Class=30
Mass test: TS0(OxxxOOOO)TS7 MS_Class=31
Mass test: TS0(OxxxOOOO)TS7 MS_Class=32
Mass test: TS0(OxxxOOOO)TS7 MS_Class=33
Mass test: TS0(OxxxOOOO)TS7 MS_Class=34
Mass test: TS0(OxxxOOOO)TS7 MS_Class=35
Mass test: TS0(OxxxOOOO)TS7 MS_Class=36
Mass test: TS0(OxxxOOOO)TS7 MS_Class=37
Mass test: TS0(OxxxOOOO)TS7 MS_Class=38
Mass test: TS0(OxxxOOOO)TS7 MS_Class=39
Mass test: TS0(OxxxOOOO)TS7 MS_Class=40
Mass test: TS0(OxxxOOOO)TS7 MS_Class=41
Mass test: TS0(OxxxOOOO)TS7 MS_Class=42
Mass test: TS0(OxxxOOOO)TS7 MS_Class=43
Mass test: TS0(OxxxOOOO)TS7 MS_Class=44
Mass test: TS0(OxxxOOOO)TS7 MS_Class=45
Mass test: TS0(OxxOxxxx)TS7 MS_Class=0
Mass test: TS0(OxxOxxxx)TS7 MS_Class=1
Mass test: TS0(OxxOxxxx)TS7 MS_Class=2
Mass test: TS0(OxxOxxxx)TS7 MS_Class=3
Mass test: TS0(OxxOxxxx)TS7 MS_Class=4
Mass test: TS0(OxxOxxxx)TS7 MS_Class=5
Mass test: TS0(OxxOxxxx)TS7 MS_Class=6
Mass test: TS0(OxxOxxxx)TS7 MS_Class=7
Mass test: TS0(OxxOxxxx)TS7 MS_Class=8
Mass test: TS0(OxxOxxxx)TS7 MS_Class=9
Mass test: TS0(OxxOxxxx)TS7 MS_Class=10
Mass test: TS0(OxxOxxxx)TS7 MS_Class=11
Mass test: TS0(OxxOxxxx)TS7 MS_Class=12
Mass test: TS0(OxxOxxxx)TS7 MS_Class=13
Mass test: TS0(OxxOxxxx)TS7 MS_Class=14
Mass test: TS0(OxxOxxxx)TS7 MS_Class=15
Mass test: TS0(OxxOxxxx)TS7 MS_Class=16
Mass test: TS0(OxxOxxxx)TS7 MS_Class=17
Mass test: TS0(OxxOxxxx)TS7 MS_Class=18
Mass test: TS0(OxxOxxxx)TS7 MS_Class=19
Mass test: TS0(OxxOxxxx)TS7 MS_Class=20
Mass test: TS0(OxxOxxxx)TS7 MS_Class=21
Mass test: TS0(OxxOxxxx)TS7 MS_Class=22
Mass test: TS0(OxxOxxxx)TS7 MS_Class=23
Mass test: TS0(OxxOxxxx)TS7 MS_Class=24
Mass test: TS0(OxxOxxxx)TS7 MS_Class=25
Mass test: TS0(OxxOxxxx)TS7 MS_Class=26
Mass test: TS0(OxxOxxxx)TS7 MS_Class=27
Mass test: TS0(OxxOxxxx)TS7 MS_Class=28
Mass test: TS0(OxxOxxxx)TS7 MS_Class=29
Mass test: TS0(OxxOxxxx)TS7 MS_Class=30
Mass test: TS0(OxxOxxxx)TS7 MS_Class=31
Mass test: TS0(OxxOxxxx)TS7 MS_Class=32
Mass test: TS0(OxxOxxxx)TS7 MS_Class=33
Mass test: TS0(OxxOxxxx)TS7 MS_Class=34
Mass test: TS0(OxxOxxxx)TS7 MS_Class=35
Mass test: TS0(OxxOxxxx)TS7 MS_Class=36
Mass test: TS0(OxxOxxxx)TS7 MS_Class=37
Mass test: TS0(OxxOxxxx)TS7 MS_Class=38
Mass test: TS0(OxxOxxxx)TS7 MS_Class=39
Mass test: TS0(OxxOxxxx)TS7 MS_Class=40
Mass test: TS0(OxxOxxxx)TS7 MS_Class=41
Mass test: TS0(OxxOxxxx)TS7 MS_Class=42
Mass test: TS0(OxxOxxxx)TS7 MS_Class=43
Mass test: TS0(OxxOxxxx)TS7 MS_Class=44
Mass test: TS0(OxxOxxxx)TS7 MS_Class=45
Mass test: TS0(OxxOxxxO)TS7 MS_Class=0
Mass test: TS0(OxxOxxxO)TS7 MS_Class=1
Mass test: TS0(OxxOxxxO)TS7 MS_Class=2
Mass test: TS0(OxxOxxxO)TS7 MS_Class=3
Mass test: TS0(OxxOxxxO)TS7 MS_Class=4
Mass test: TS0(OxxOxxxO)TS7 MS_Class=5
Mass test: TS0(OxxOxxxO)TS7 MS_Class=6
Mass test: TS0(OxxOxxxO)TS7 MS_Class=7
Mass test: TS0(OxxOxxxO)TS7 MS_Class=8
Mass test: TS0(OxxOxxxO)TS7 MS_Class=9
Mass test: TS0(OxxOxxxO)TS7 MS_Class=10
Mass test: TS0(OxxOxxxO)TS7 MS_Class=11
Mass test: TS0(OxxOxxxO)TS7 MS_Class=12
Mass test: TS0(OxxOxxxO)TS7 MS_Class=13
Mass test: TS0(OxxOxxxO)TS7 MS_Class=14
Mass test: TS0(OxxOxxxO)TS7 MS_Class=15
Mass test: TS0(OxxOxxxO)TS7 MS_Class=16
Mass test: TS0(OxxOxxxO)TS7 MS_Class=17
Mass test: TS0(OxxOxxxO)TS7 MS_Class=18
Mass test: TS0(OxxOxxxO)TS7 MS_Class=19
Mass test: TS0(OxxOxxxO)TS7 MS_Class=20
Mass test: TS0(OxxOxxxO)TS7 MS_Class=21
Mass test: TS0(OxxOxxxO)TS7 MS_Class=22
Mass test: TS0(OxxOxxxO)TS7 MS_Class=23
Mass test: TS0(OxxOxxxO)TS7 MS_Class=24
Mass test: TS0(OxxOxxxO)TS7 MS_Class=25
Mass test: TS0(OxxOxxxO)TS7 MS_Class=26
Mass test: TS0(OxxOxxxO)TS7 MS_Class=27
Mass test: TS0(OxxOxxxO)TS7 MS_Class=28
Mass test: TS0(OxxOxxxO)TS7 MS_Class=29
Mass test: TS0(OxxOxxxO)TS7 MS_Class=30
Mass test: TS0(OxxOxxxO)TS7 MS_Class=31
Mass test: TS0(OxxOxxxO)TS7 MS_Class=32
Mass test: TS0(OxxOxxxO)TS7 MS_Class=33
Mass test: TS0(OxxOxxxO)TS7 MS_Class=34
Mass test: TS0(OxxOxxxO)TS7 MS_Class=35
Mass test: TS0(OxxOxxxO)TS7 MS_Class=36
Mass test: TS0(OxxOxxxO)TS7 MS_Class=37
Mass test: TS0(OxxOxxxO)TS7 MS_Class=38
Mass test: TS0(OxxOxxxO)TS7 MS_Class=39
Mass test: TS0(OxxOxxxO)TS7 MS_Class=40
Mass test: TS0(OxxOxxxO)TS7 MS_Class=41
Mass test: TS0(OxxOxxxO)TS7 MS_Class=42
Mass test: TS0(OxxOxxxO)TS7 MS_Class=43
Mass test: TS0(OxxOxxxO)TS7 MS_Class=44
Mass test: TS0(OxxOxxxO)TS7 MS_Class=45
Mass test: TS0(OxxOxxOx)TS7 MS_Class=0
Mass test: TS0(OxxOxxOx)TS7 MS_Class=1
Mass test: TS0(OxxOxxOx)TS7 MS_Class=2
Mass test: TS0(OxxOxxOx)TS7 MS_Class=3
Mass test: TS0(OxxOxxOx)TS7 MS_Class=4
Mass test: TS0(OxxOxxOx)TS7 MS_Class=5
Mass test: TS0(OxxOxxOx)TS7 MS_Class=6
Mass test: TS0(OxxOxxOx)TS7 MS_Class=7
Mass test: TS0(OxxOxxOx)TS7 MS_Class=8
Mass test: TS0(OxxOxxOx)TS7 MS_Class=9
Mass test: TS0(OxxOxxOx)TS7 MS_Class=10
Mass test: TS0(OxxOxxOx)TS7 MS_Class=11
Mass test: TS0(OxxOxxOx)TS7 MS_Class=12
Mass test: TS0(OxxOxxOx)TS7 MS_Class=13
Mass test: TS0(OxxOxxOx)TS7 MS_Class=14
Mass test: TS0(OxxOxxOx)TS7 MS_Class=15
Mass test: TS0(OxxOxxOx)TS7 MS_Class=16
Mass test: TS0(OxxOxxOx)TS7 MS_Class=17
Mass test: TS0(OxxOxxOx)TS7 MS_Class=18
Mass test: TS0(OxxOxxOx)TS7 MS_Class=19
Mass test: TS0(OxxOxxOx)TS7 MS_Class=20
Mass test: TS0(OxxOxxOx)TS7 MS_Class=21
Mass test: TS0(OxxOxxOx)TS7 MS_Class=22
Mass test: TS0(OxxOxxOx)TS7 MS_Class=23
Mass test: TS0(OxxOxxOx)TS7 MS_Class=24
Mass test: TS0(OxxOxxOx)TS7 MS_Class=25
Mass test: TS0(OxxOxxOx)TS7 MS_Class=26
Mass test: TS0(OxxOxxOx)TS7 MS_Class=27
Mass test: TS0(OxxOxxOx)TS7 MS_Class=28
Mass test: TS0(OxxOxxOx)TS7 MS_Class=29
Mass test: TS0(OxxOxxOx)TS7 MS_Class=30
Mass test: TS0(OxxOxxOx)TS7 MS_Class=31
Mass test: TS0(OxxOxxOx)TS7 MS_Class=32
Mass test: TS0(OxxOxxOx)TS7 MS_Class=33
Mass test: TS0(OxxOxxOx)TS7 MS_Class=34
Mass test: TS0(OxxOxxOx)TS7 MS_Class=35
Mass test: TS0(OxxOxxOx)TS7 MS_Class=36
Mass test: TS0(OxxOxxOx)TS7 MS_Class=37
Mass test: TS0(OxxOxxOx)TS7 MS_Class=38
Mass test: TS0(OxxOxxOx)TS7 MS_Class=39
Mass test: TS0(OxxOxxOx)TS7 MS_Class=40
Mass test: TS0(OxxOxxOx)TS7 MS_Class=41
Mass test: TS0(OxxOxxOx)TS7 MS_Class=42
Mass test: TS0(OxxOxxOx)TS7 MS_Class=43
Mass test: TS0(OxxOxxOx)TS7 MS_Class=44
Mass test: TS0(OxxOxxOx)TS7 MS_Class=45
Mass test: TS0(OxxOxxOO)TS7 MS_Class=0
Mass test: TS0(OxxOxxOO)TS7 MS_Class=1
Mass test: TS0(OxxOxxOO)TS7 MS_Class=2
Mass test: TS0(OxxOxxOO)TS7 MS_Class=3
Mass test: TS0(OxxOxxOO)TS7 MS_Class=4
Mass test: TS0(OxxOxxOO)TS7 MS_Class=5
Mass test: TS0(OxxOxxOO)TS7 MS_Class=6
Mass test: TS0(OxxOxxOO)TS7 MS_Class=7
Mass test: TS0(OxxOxxOO)TS7 MS_Class=8
Mass test: TS0(OxxOxxOO)TS7 MS_Class=9
Mass test: TS0(OxxOxxOO)TS7 MS_Class=10
Mass test: TS0(OxxOxxOO)TS7 MS_Class=11
Mass test: TS0(OxxOxxOO)TS7 MS_Class=12
Mass test: TS0(OxxOxxOO)TS7 MS_Class=13
Mass test: TS0(OxxOxxOO)TS7 MS_Class=14
Mass test: TS0(OxxOxxOO)TS7 MS_Class=15
Mass test: TS0(OxxOxxOO)TS7 MS_Class=16
Mass test: TS0(OxxOxxOO)TS7 MS_Class=17
Mass test: TS0(OxxOxxOO)TS7 MS_Class=18
Mass test: TS0(OxxOxxOO)TS7 MS_Class=19
Mass test: TS0(OxxOxxOO)TS7 MS_Class=20
Mass test: TS0(OxxOxxOO)TS7 MS_Class=21
Mass test: TS0(OxxOxxOO)TS7 MS_Class=22
Mass test: TS0(OxxOxxOO)TS7 MS_Class=23
Mass test: TS0(OxxOxxOO)TS7 MS_Class=24
Mass test: TS0(OxxOxxOO)TS7 MS_Class=25
Mass test: TS0(OxxOxxOO)TS7 MS_Class=26
Mass test: TS0(OxxOxxOO)TS7 MS_Class=27
Mass test: TS0(OxxOxxOO)TS7 MS_Class=28
Mass test: TS0(OxxOxxOO)TS7 MS_Class=29
Mass test: TS0(OxxOxxOO)TS7 MS_Class=30
Mass test: TS0(OxxOxxOO)TS7 MS_Class=31
Mass test: TS0(OxxOxxOO)TS7 MS_Class=32
Mass test: TS0(OxxOxxOO)TS7 MS_Class=33
Mass test: TS0(OxxOxxOO)TS7 MS_Class=34
Mass test: TS0(OxxOxxOO)TS7 MS_Class=35
Mass test: TS0(OxxOxxOO)TS7 MS_Class=36
Mass test: TS0(OxxOxxOO)TS7 MS_Class=37
Mass test: TS0(OxxOxxOO)TS7 MS_Class=38
Mass test: TS0(OxxOxxOO)TS7 MS_Class=39
Mass test: TS0(OxxOxxOO)TS7 MS_Class=40
Mass test: TS0(OxxOxxOO)TS7 MS_Class=41
Mass test: TS0(OxxOxxOO)TS7 MS_Class=42
Mass test: TS0(OxxOxxOO)TS7 MS_Class=43
Mass test: TS0(OxxOxxOO)TS7 MS_Class=44
Mass test: TS0(OxxOxxOO)TS7 MS_Class=45
Mass test: TS0(OxxOxOxx)TS7 MS_Class=0
Mass test: TS0(OxxOxOxx)TS7 MS_Class=1
Mass test: TS0(OxxOxOxx)TS7 MS_Class=2
Mass test: TS0(OxxOxOxx)TS7 MS_Class=3
Mass test: TS0(OxxOxOxx)TS7 MS_Class=4
Mass test: TS0(OxxOxOxx)TS7 MS_Class=5
Mass test: TS0(OxxOxOxx)TS7 MS_Class=6
Mass test: TS0(OxxOxOxx)TS7 MS_Class=7
Mass test: TS0(OxxOxOxx)TS7 MS_Class=8
Mass test: TS0(OxxOxOxx)TS7 MS_Class=9
Mass test: TS0(OxxOxOxx)TS7 MS_Class=10
Mass test: TS0(OxxOxOxx)TS7 MS_Class=11
Mass test: TS0(OxxOxOxx)TS7 MS_Class=12
Mass test: TS0(OxxOxOxx)TS7 MS_Class=13
Mass test: TS0(OxxOxOxx)TS7 MS_Class=14
Mass test: TS0(OxxOxOxx)TS7 MS_Class=15
Mass test: TS0(OxxOxOxx)TS7 MS_Class=16
Mass test: TS0(OxxOxOxx)TS7 MS_Class=17
Mass test: TS0(OxxOxOxx)TS7 MS_Class=18
Mass test: TS0(OxxOxOxx)TS7 MS_Class=19
Mass test: TS0(OxxOxOxx)TS7 MS_Class=20
Mass test: TS0(OxxOxOxx)TS7 MS_Class=21
Mass test: TS0(OxxOxOxx)TS7 MS_Class=22
Mass test: TS0(OxxOxOxx)TS7 MS_Class=23
Mass test: TS0(OxxOxOxx)TS7 MS_Class=24
Mass test: TS0(OxxOxOxx)TS7 MS_Class=25
Mass test: TS0(OxxOxOxx)TS7 MS_Class=26
Mass test: TS0(OxxOxOxx)TS7 MS_Class=27
Mass test: TS0(OxxOxOxx)TS7 MS_Class=28
Mass test: TS0(OxxOxOxx)TS7 MS_Class=29
Mass test: TS0(OxxOxOxx)TS7 MS_Class=30
Mass test: TS0(OxxOxOxx)TS7 MS_Class=31
Mass test: TS0(OxxOxOxx)TS7 MS_Class=32
Mass test: TS0(OxxOxOxx)TS7 MS_Class=33
Mass test: TS0(OxxOxOxx)TS7 MS_Class=34
Mass test: TS0(OxxOxOxx)TS7 MS_Class=35
Mass test: TS0(OxxOxOxx)TS7 MS_Class=36
Mass test: TS0(OxxOxOxx)TS7 MS_Class=37
Mass test: TS0(OxxOxOxx)TS7 MS_Class=38
Mass test: TS0(OxxOxOxx)TS7 MS_Class=39
Mass test: TS0(OxxOxOxx)TS7 MS_Class=40
Mass test: TS0(OxxOxOxx)TS7 MS_Class=41
Mass test: TS0(OxxOxOxx)TS7 MS_Class=42
Mass test: TS0(OxxOxOxx)TS7 MS_Class=43
Mass test: TS0(OxxOxOxx)TS7 MS_Class=44
Mass test: TS0(OxxOxOxx)TS7 MS_Class=45
Mass test: TS0(OxxOxOxO)TS7 MS_Class=0
Mass test: TS0(OxxOxOxO)TS7 MS_Class=1
Mass test: TS0(OxxOxOxO)TS7 MS_Class=2
Mass test: TS0(OxxOxOxO)TS7 MS_Class=3
Mass test: TS0(OxxOxOxO)TS7 MS_Class=4
Mass test: TS0(OxxOxOxO)TS7 MS_Class=5
Mass test: TS0(OxxOxOxO)TS7 MS_Class=6
Mass test: TS0(OxxOxOxO)TS7 MS_Class=7
Mass test: TS0(OxxOxOxO)TS7 MS_Class=8
Mass test: TS0(OxxOxOxO)TS7 MS_Class=9
Mass test: TS0(OxxOxOxO)TS7 MS_Class=10
Mass test: TS0(OxxOxOxO)TS7 MS_Class=11
Mass test: TS0(OxxOxOxO)TS7 MS_Class=12
Mass test: TS0(OxxOxOxO)TS7 MS_Class=13
Mass test: TS0(OxxOxOxO)TS7 MS_Class=14
Mass test: TS0(OxxOxOxO)TS7 MS_Class=15
Mass test: TS0(OxxOxOxO)TS7 MS_Class=16
Mass test: TS0(OxxOxOxO)TS7 MS_Class=17
Mass test: TS0(OxxOxOxO)TS7 MS_Class=18
Mass test: TS0(OxxOxOxO)TS7 MS_Class=19
Mass test: TS0(OxxOxOxO)TS7 MS_Class=20
Mass test: TS0(OxxOxOxO)TS7 MS_Class=21
Mass test: TS0(OxxOxOxO)TS7 MS_Class=22
Mass test: TS0(OxxOxOxO)TS7 MS_Class=23
Mass test: TS0(OxxOxOxO)TS7 MS_Class=24
Mass test: TS0(OxxOxOxO)TS7 MS_Class=25
Mass test: TS0(OxxOxOxO)TS7 MS_Class=26
Mass test: TS0(OxxOxOxO)TS7 MS_Class=27
Mass test: TS0(OxxOxOxO)TS7 MS_Class=28
Mass test: TS0(OxxOxOxO)TS7 MS_Class=29
Mass test: TS0(OxxOxOxO)TS7 MS_Class=30
Mass test: TS0(OxxOxOxO)TS7 MS_Class=31
Mass test: TS0(OxxOxOxO)TS7 MS_Class=32
Mass test: TS0(OxxOxOxO)TS7 MS_Class=33
Mass test: TS0(OxxOxOxO)TS7 MS_Class=34
Mass test: TS0(OxxOxOxO)TS7 MS_Class=35
Mass test: TS0(OxxOxOxO)TS7 MS_Class=36
Mass test: TS0(OxxOxOxO)TS7 MS_Class=37
Mass test: TS0(OxxOxOxO)TS7 MS_Class=38
Mass test: TS0(OxxOxOxO)TS7 MS_Class=39
Mass test: TS0(OxxOxOxO)TS7 MS_Class=40
Mass test: TS0(OxxOxOxO)TS7 MS_Class=41
Mass test: TS0(OxxOxOxO)TS7 MS_Class=42
Mass test: TS0(OxxOxOxO)TS7 MS_Class=43
Mass test: TS0(OxxOxOxO)TS7 MS_Class=44
Mass test: TS0(OxxOxOxO)TS7 MS_Class=45
Mass test: TS0(OxxOxOOx)TS7 MS_Class=0
Mass test: TS0(OxxOxOOx)TS7 MS_Class=1
Mass test: TS0(OxxOxOOx)TS7 MS_Class=2
Mass test: TS0(OxxOxOOx)TS7 MS_Class=3
Mass test: TS0(OxxOxOOx)TS7 MS_Class=4
Mass test: TS0(OxxOxOOx)TS7 MS_Class=5
Mass test: TS0(OxxOxOOx)TS7 MS_Class=6
Mass test: TS0(OxxOxOOx)TS7 MS_Class=7
Mass test: TS0(OxxOxOOx)TS7 MS_Class=8
Mass test: TS0(OxxOxOOx)TS7 MS_Class=9
Mass test: TS0(OxxOxOOx)TS7 MS_Class=10
Mass test: TS0(OxxOxOOx)TS7 MS_Class=11
Mass test: TS0(OxxOxOOx)TS7 MS_Class=12
Mass test: TS0(OxxOxOOx)TS7 MS_Class=13
Mass test: TS0(OxxOxOOx)TS7 MS_Class=14
Mass test: TS0(OxxOxOOx)TS7 MS_Class=15
Mass test: TS0(OxxOxOOx)TS7 MS_Class=16
Mass test: TS0(OxxOxOOx)TS7 MS_Class=17
Mass test: TS0(OxxOxOOx)TS7 MS_Class=18
Mass test: TS0(OxxOxOOx)TS7 MS_Class=19
Mass test: TS0(OxxOxOOx)TS7 MS_Class=20
Mass test: TS0(OxxOxOOx)TS7 MS_Class=21
Mass test: TS0(OxxOxOOx)TS7 MS_Class=22
Mass test: TS0(OxxOxOOx)TS7 MS_Class=23
Mass test: TS0(OxxOxOOx)TS7 MS_Class=24
Mass test: TS0(OxxOxOOx)TS7 MS_Class=25
Mass test: TS0(OxxOxOOx)TS7 MS_Class=26
Mass test: TS0(OxxOxOOx)TS7 MS_Class=27
Mass test: TS0(OxxOxOOx)TS7 MS_Class=28
Mass test: TS0(OxxOxOOx)TS7 MS_Class=29
Mass test: TS0(OxxOxOOx)TS7 MS_Class=30
Mass test: TS0(OxxOxOOx)TS7 MS_Class=31
Mass test: TS0(OxxOxOOx)TS7 MS_Class=32
Mass test: TS0(OxxOxOOx)TS7 MS_Class=33
Mass test: TS0(OxxOxOOx)TS7 MS_Class=34
Mass test: TS0(OxxOxOOx)TS7 MS_Class=35
Mass test: TS0(OxxOxOOx)TS7 MS_Class=36
Mass test: TS0(OxxOxOOx)TS7 MS_Class=37
Mass test: TS0(OxxOxOOx)TS7 MS_Class=38
Mass test: TS0(OxxOxOOx)TS7 MS_Class=39
Mass test: TS0(OxxOxOOx)TS7 MS_Class=40
Mass test: TS0(OxxOxOOx)TS7 MS_Class=41
Mass test: TS0(OxxOxOOx)TS7 MS_Class=42
Mass test: TS0(OxxOxOOx)TS7 MS_Class=43
Mass test: TS0(OxxOxOOx)TS7 MS_Class=44
Mass test: TS0(OxxOxOOx)TS7 MS_Class=45
Mass test: TS0(OxxOxOOO)TS7 MS_Class=0
Mass test: TS0(OxxOxOOO)TS7 MS_Class=1
Mass test: TS0(OxxOxOOO)TS7 MS_Class=2
Mass test: TS0(OxxOxOOO)TS7 MS_Class=3
Mass test: TS0(OxxOxOOO)TS7 MS_Class=4
Mass test: TS0(OxxOxOOO)TS7 MS_Class=5
Mass test: TS0(OxxOxOOO)TS7 MS_Class=6
Mass test: TS0(OxxOxOOO)TS7 MS_Class=7
Mass test: TS0(OxxOxOOO)TS7 MS_Class=8
Mass test: TS0(OxxOxOOO)TS7 MS_Class=9
Mass test: TS0(OxxOxOOO)TS7 MS_Class=10
Mass test: TS0(OxxOxOOO)TS7 MS_Class=11
Mass test: TS0(OxxOxOOO)TS7 MS_Class=12
Mass test: TS0(OxxOxOOO)TS7 MS_Class=13
Mass test: TS0(OxxOxOOO)TS7 MS_Class=14
Mass test: TS0(OxxOxOOO)TS7 MS_Class=15
Mass test: TS0(OxxOxOOO)TS7 MS_Class=16
Mass test: TS0(OxxOxOOO)TS7 MS_Class=17
Mass test: TS0(OxxOxOOO)TS7 MS_Class=18
Mass test: TS0(OxxOxOOO)TS7 MS_Class=19
Mass test: TS0(OxxOxOOO)TS7 MS_Class=20
Mass test: TS0(OxxOxOOO)TS7 MS_Class=21
Mass test: TS0(OxxOxOOO)TS7 MS_Class=22
Mass test: TS0(OxxOxOOO)TS7 MS_Class=23
Mass test: TS0(OxxOxOOO)TS7 MS_Class=24
Mass test: TS0(OxxOxOOO)TS7 MS_Class=25
Mass test: TS0(OxxOxOOO)TS7 MS_Class=26
Mass test: TS0(OxxOxOOO)TS7 MS_Class=27
Mass test: TS0(OxxOxOOO)TS7 MS_Class=28
Mass test: TS0(OxxOxOOO)TS7 MS_Class=29
Mass test: TS0(OxxOxOOO)TS7 MS_Class=30
Mass test: TS0(OxxOxOOO)TS7 MS_Class=31
Mass test: TS0(OxxOxOOO)TS7 MS_Class=32
Mass test: TS0(OxxOxOOO)TS7 MS_Class=33
Mass test: TS0(OxxOxOOO)TS7 MS_Class=34
Mass test: TS0(OxxOxOOO)TS7 MS_Class=35
Mass test: TS0(OxxOxOOO)TS7 MS_Class=36
Mass test: TS0(OxxOxOOO)TS7 MS_Class=37
Mass test: TS0(OxxOxOOO)TS7 MS_Class=38
Mass test: TS0(OxxOxOOO)TS7 MS_Class=39
Mass test: TS0(OxxOxOOO)TS7 MS_Class=40
Mass test: TS0(OxxOxOOO)TS7 MS_Class=41
Mass test: TS0(OxxOxOOO)TS7 MS_Class=42
Mass test: TS0(OxxOxOOO)TS7 MS_Class=43
Mass test: TS0(OxxOxOOO)TS7 MS_Class=44
Mass test: TS0(OxxOxOOO)TS7 MS_Class=45
Mass test: TS0(OxxOOxxx)TS7 MS_Class=0
Mass test: TS0(OxxOOxxx)TS7 MS_Class=1
Mass test: TS0(OxxOOxxx)TS7 MS_Class=2
Mass test: TS0(OxxOOxxx)TS7 MS_Class=3
Mass test: TS0(OxxOOxxx)TS7 MS_Class=4
Mass test: TS0(OxxOOxxx)TS7 MS_Class=5
Mass test: TS0(OxxOOxxx)TS7 MS_Class=6
Mass test: TS0(OxxOOxxx)TS7 MS_Class=7
Mass test: TS0(OxxOOxxx)TS7 MS_Class=8
Mass test: TS0(OxxOOxxx)TS7 MS_Class=9
Mass test: TS0(OxxOOxxx)TS7 MS_Class=10
Mass test: TS0(OxxOOxxx)TS7 MS_Class=11
Mass test: TS0(OxxOOxxx)TS7 MS_Class=12
Mass test: TS0(OxxOOxxx)TS7 MS_Class=13
Mass test: TS0(OxxOOxxx)TS7 MS_Class=14
Mass test: TS0(OxxOOxxx)TS7 MS_Class=15
Mass test: TS0(OxxOOxxx)TS7 MS_Class=16
Mass test: TS0(OxxOOxxx)TS7 MS_Class=17
Mass test: TS0(OxxOOxxx)TS7 MS_Class=18
Mass test: TS0(OxxOOxxx)TS7 MS_Class=19
Mass test: TS0(OxxOOxxx)TS7 MS_Class=20
Mass test: TS0(OxxOOxxx)TS7 MS_Class=21
Mass test: TS0(OxxOOxxx)TS7 MS_Class=22
Mass test: TS0(OxxOOxxx)TS7 MS_Class=23
Mass test: TS0(OxxOOxxx)TS7 MS_Class=24
Mass test: TS0(OxxOOxxx)TS7 MS_Class=25
Mass test: TS0(OxxOOxxx)TS7 MS_Class=26
Mass test: TS0(OxxOOxxx)TS7 MS_Class=27
Mass test: TS0(OxxOOxxx)TS7 MS_Class=28
Mass test: TS0(OxxOOxxx)TS7 MS_Class=29
Mass test: TS0(OxxOOxxx)TS7 MS_Class=30
Mass test: TS0(OxxOOxxx)TS7 MS_Class=31
Mass test: TS0(OxxOOxxx)TS7 MS_Class=32
Mass test: TS0(OxxOOxxx)TS7 MS_Class=33
Mass test: TS0(OxxOOxxx)TS7 MS_Class=34
Mass test: TS0(OxxOOxxx)TS7 MS_Class=35
Mass test: TS0(OxxOOxxx)TS7 MS_Class=36
Mass test: TS0(OxxOOxxx)TS7 MS_Class=37
Mass test: TS0(OxxOOxxx)TS7 MS_Class=38
Mass test: TS0(OxxOOxxx)TS7 MS_Class=39
Mass test: TS0(OxxOOxxx)TS7 MS_Class=40
Mass test: TS0(OxxOOxxx)TS7 MS_Class=41
Mass test: TS0(OxxOOxxx)TS7 MS_Class=42
Mass test: TS0(OxxOOxxx)TS7 MS_Class=43
Mass test: TS0(OxxOOxxx)TS7 MS_Class=44
Mass test: TS0(OxxOOxxx)TS7 MS_Class=45
Mass test: TS0(OxxOOxxO)TS7 MS_Class=0
Mass test: TS0(OxxOOxxO)TS7 MS_Class=1
Mass test: TS0(OxxOOxxO)TS7 MS_Class=2
Mass test: TS0(OxxOOxxO)TS7 MS_Class=3
Mass test: TS0(OxxOOxxO)TS7 MS_Class=4
Mass test: TS0(OxxOOxxO)TS7 MS_Class=5
Mass test: TS0(OxxOOxxO)TS7 MS_Class=6
Mass test: TS0(OxxOOxxO)TS7 MS_Class=7
Mass test: TS0(OxxOOxxO)TS7 MS_Class=8
Mass test: TS0(OxxOOxxO)TS7 MS_Class=9
Mass test: TS0(OxxOOxxO)TS7 MS_Class=10
Mass test: TS0(OxxOOxxO)TS7 MS_Class=11
Mass test: TS0(OxxOOxxO)TS7 MS_Class=12
Mass test: TS0(OxxOOxxO)TS7 MS_Class=13
Mass test: TS0(OxxOOxxO)TS7 MS_Class=14
Mass test: TS0(OxxOOxxO)TS7 MS_Class=15
Mass test: TS0(OxxOOxxO)TS7 MS_Class=16
Mass test: TS0(OxxOOxxO)TS7 MS_Class=17
Mass test: TS0(OxxOOxxO)TS7 MS_Class=18
Mass test: TS0(OxxOOxxO)TS7 MS_Class=19
Mass test: TS0(OxxOOxxO)TS7 MS_Class=20
Mass test: TS0(OxxOOxxO)TS7 MS_Class=21
Mass test: TS0(OxxOOxxO)TS7 MS_Class=22
Mass test: TS0(OxxOOxxO)TS7 MS_Class=23
Mass test: TS0(OxxOOxxO)TS7 MS_Class=24
Mass test: TS0(OxxOOxxO)TS7 MS_Class=25
Mass test: TS0(OxxOOxxO)TS7 MS_Class=26
Mass test: TS0(OxxOOxxO)TS7 MS_Class=27
Mass test: TS0(OxxOOxxO)TS7 MS_Class=28
Mass test: TS0(OxxOOxxO)TS7 MS_Class=29
Mass test: TS0(OxxOOxxO)TS7 MS_Class=30
Mass test: TS0(OxxOOxxO)TS7 MS_Class=31
Mass test: TS0(OxxOOxxO)TS7 MS_Class=32
Mass test: TS0(OxxOOxxO)TS7 MS_Class=33
Mass test: TS0(OxxOOxxO)TS7 MS_Class=34
Mass test: TS0(OxxOOxxO)TS7 MS_Class=35
Mass test: TS0(OxxOOxxO)TS7 MS_Class=36
Mass test: TS0(OxxOOxxO)TS7 MS_Class=37
Mass test: TS0(OxxOOxxO)TS7 MS_Class=38
Mass test: TS0(OxxOOxxO)TS7 MS_Class=39
Mass test: TS0(OxxOOxxO)TS7 MS_Class=40
Mass test: TS0(OxxOOxxO)TS7 MS_Class=41
Mass test: TS0(OxxOOxxO)TS7 MS_Class=42
Mass test: TS0(OxxOOxxO)TS7 MS_Class=43
Mass test: TS0(OxxOOxxO)TS7 MS_Class=44
Mass test: TS0(OxxOOxxO)TS7 MS_Class=45
Mass test: TS0(OxxOOxOx)TS7 MS_Class=0
Mass test: TS0(OxxOOxOx)TS7 MS_Class=1
Mass test: TS0(OxxOOxOx)TS7 MS_Class=2
Mass test: TS0(OxxOOxOx)TS7 MS_Class=3
Mass test: TS0(OxxOOxOx)TS7 MS_Class=4
Mass test: TS0(OxxOOxOx)TS7 MS_Class=5
Mass test: TS0(OxxOOxOx)TS7 MS_Class=6
Mass test: TS0(OxxOOxOx)TS7 MS_Class=7
Mass test: TS0(OxxOOxOx)TS7 MS_Class=8
Mass test: TS0(OxxOOxOx)TS7 MS_Class=9
Mass test: TS0(OxxOOxOx)TS7 MS_Class=10
Mass test: TS0(OxxOOxOx)TS7 MS_Class=11
Mass test: TS0(OxxOOxOx)TS7 MS_Class=12
Mass test: TS0(OxxOOxOx)TS7 MS_Class=13
Mass test: TS0(OxxOOxOx)TS7 MS_Class=14
Mass test: TS0(OxxOOxOx)TS7 MS_Class=15
Mass test: TS0(OxxOOxOx)TS7 MS_Class=16
Mass test: TS0(OxxOOxOx)TS7 MS_Class=17
Mass test: TS0(OxxOOxOx)TS7 MS_Class=18
Mass test: TS0(OxxOOxOx)TS7 MS_Class=19
Mass test: TS0(OxxOOxOx)TS7 MS_Class=20
Mass test: TS0(OxxOOxOx)TS7 MS_Class=21
Mass test: TS0(OxxOOxOx)TS7 MS_Class=22
Mass test: TS0(OxxOOxOx)TS7 MS_Class=23
Mass test: TS0(OxxOOxOx)TS7 MS_Class=24
Mass test: TS0(OxxOOxOx)TS7 MS_Class=25
Mass test: TS0(OxxOOxOx)TS7 MS_Class=26
Mass test: TS0(OxxOOxOx)TS7 MS_Class=27
Mass test: TS0(OxxOOxOx)TS7 MS_Class=28
Mass test: TS0(OxxOOxOx)TS7 MS_Class=29
Mass test: TS0(OxxOOxOx)TS7 MS_Class=30
Mass test: TS0(OxxOOxOx)TS7 MS_Class=31
Mass test: TS0(OxxOOxOx)TS7 MS_Class=32
Mass test: TS0(OxxOOxOx)TS7 MS_Class=33
Mass test: TS0(OxxOOxOx)TS7 MS_Class=34
Mass test: TS0(OxxOOxOx)TS7 MS_Class=35
Mass test: TS0(OxxOOxOx)TS7 MS_Class=36
Mass test: TS0(OxxOOxOx)TS7 MS_Class=37
Mass test: TS0(OxxOOxOx)TS7 MS_Class=38
Mass test: TS0(OxxOOxOx)TS7 MS_Class=39
Mass test: TS0(OxxOOxOx)TS7 MS_Class=40
Mass test: TS0(OxxOOxOx)TS7 MS_Class=41
Mass test: TS0(OxxOOxOx)TS7 MS_Class=42
Mass test: TS0(OxxOOxOx)TS7 MS_Class=43
Mass test: TS0(OxxOOxOx)TS7 MS_Class=44
Mass test: TS0(OxxOOxOx)TS7 MS_Class=45
Mass test: TS0(OxxOOxOO)TS7 MS_Class=0
Mass test: TS0(OxxOOxOO)TS7 MS_Class=1
Mass test: TS0(OxxOOxOO)TS7 MS_Class=2
Mass test: TS0(OxxOOxOO)TS7 MS_Class=3
Mass test: TS0(OxxOOxOO)TS7 MS_Class=4
Mass test: TS0(OxxOOxOO)TS7 MS_Class=5
Mass test: TS0(OxxOOxOO)TS7 MS_Class=6
Mass test: TS0(OxxOOxOO)TS7 MS_Class=7
Mass test: TS0(OxxOOxOO)TS7 MS_Class=8
Mass test: TS0(OxxOOxOO)TS7 MS_Class=9
Mass test: TS0(OxxOOxOO)TS7 MS_Class=10
Mass test: TS0(OxxOOxOO)TS7 MS_Class=11
Mass test: TS0(OxxOOxOO)TS7 MS_Class=12
Mass test: TS0(OxxOOxOO)TS7 MS_Class=13
Mass test: TS0(OxxOOxOO)TS7 MS_Class=14
Mass test: TS0(OxxOOxOO)TS7 MS_Class=15
Mass test: TS0(OxxOOxOO)TS7 MS_Class=16
Mass test: TS0(OxxOOxOO)TS7 MS_Class=17
Mass test: TS0(OxxOOxOO)TS7 MS_Class=18
Mass test: TS0(OxxOOxOO)TS7 MS_Class=19
Mass test: TS0(OxxOOxOO)TS7 MS_Class=20
Mass test: TS0(OxxOOxOO)TS7 MS_Class=21
Mass test: TS0(OxxOOxOO)TS7 MS_Class=22
Mass test: TS0(OxxOOxOO)TS7 MS_Class=23
Mass test: TS0(OxxOOxOO)TS7 MS_Class=24
Mass test: TS0(OxxOOxOO)TS7 MS_Class=25
Mass test: TS0(OxxOOxOO)TS7 MS_Class=26
Mass test: TS0(OxxOOxOO)TS7 MS_Class=27
Mass test: TS0(OxxOOxOO)TS7 MS_Class=28
Mass test: TS0(OxxOOxOO)TS7 MS_Class=29
Mass test: TS0(OxxOOxOO)TS7 MS_Class=30
Mass test: TS0(OxxOOxOO)TS7 MS_Class=31
Mass test: TS0(OxxOOxOO)TS7 MS_Class=32
Mass test: TS0(OxxOOxOO)TS7 MS_Class=33
Mass test: TS0(OxxOOxOO)TS7 MS_Class=34
Mass test: TS0(OxxOOxOO)TS7 MS_Class=35
Mass test: TS0(OxxOOxOO)TS7 MS_Class=36
Mass test: TS0(OxxOOxOO)TS7 MS_Class=37
Mass test: TS0(OxxOOxOO)TS7 MS_Class=38
Mass test: TS0(OxxOOxOO)TS7 MS_Class=39
Mass test: TS0(OxxOOxOO)TS7 MS_Class=40
Mass test: TS0(OxxOOxOO)TS7 MS_Class=41
Mass test: TS0(OxxOOxOO)TS7 MS_Class=42
Mass test: TS0(OxxOOxOO)TS7 MS_Class=43
Mass test: TS0(OxxOOxOO)TS7 MS_Class=44
Mass test: TS0(OxxOOxOO)TS7 MS_Class=45
Mass test: TS0(OxxOOOxx)TS7 MS_Class=0
Mass test: TS0(OxxOOOxx)TS7 MS_Class=1
Mass test: TS0(OxxOOOxx)TS7 MS_Class=2
Mass test: TS0(OxxOOOxx)TS7 MS_Class=3
Mass test: TS0(OxxOOOxx)TS7 MS_Class=4
Mass test: TS0(OxxOOOxx)TS7 MS_Class=5
Mass test: TS0(OxxOOOxx)TS7 MS_Class=6
Mass test: TS0(OxxOOOxx)TS7 MS_Class=7
Mass test: TS0(OxxOOOxx)TS7 MS_Class=8
Mass test: TS0(OxxOOOxx)TS7 MS_Class=9
Mass test: TS0(OxxOOOxx)TS7 MS_Class=10
Mass test: TS0(OxxOOOxx)TS7 MS_Class=11
Mass test: TS0(OxxOOOxx)TS7 MS_Class=12
Mass test: TS0(OxxOOOxx)TS7 MS_Class=13
Mass test: TS0(OxxOOOxx)TS7 MS_Class=14
Mass test: TS0(OxxOOOxx)TS7 MS_Class=15
Mass test: TS0(OxxOOOxx)TS7 MS_Class=16
Mass test: TS0(OxxOOOxx)TS7 MS_Class=17
Mass test: TS0(OxxOOOxx)TS7 MS_Class=18
Mass test: TS0(OxxOOOxx)TS7 MS_Class=19
Mass test: TS0(OxxOOOxx)TS7 MS_Class=20
Mass test: TS0(OxxOOOxx)TS7 MS_Class=21
Mass test: TS0(OxxOOOxx)TS7 MS_Class=22
Mass test: TS0(OxxOOOxx)TS7 MS_Class=23
Mass test: TS0(OxxOOOxx)TS7 MS_Class=24
Mass test: TS0(OxxOOOxx)TS7 MS_Class=25
Mass test: TS0(OxxOOOxx)TS7 MS_Class=26
Mass test: TS0(OxxOOOxx)TS7 MS_Class=27
Mass test: TS0(OxxOOOxx)TS7 MS_Class=28
Mass test: TS0(OxxOOOxx)TS7 MS_Class=29
Mass test: TS0(OxxOOOxx)TS7 MS_Class=30
Mass test: TS0(OxxOOOxx)TS7 MS_Class=31
Mass test: TS0(OxxOOOxx)TS7 MS_Class=32
Mass test: TS0(OxxOOOxx)TS7 MS_Class=33
Mass test: TS0(OxxOOOxx)TS7 MS_Class=34
Mass test: TS0(OxxOOOxx)TS7 MS_Class=35
Mass test: TS0(OxxOOOxx)TS7 MS_Class=36
Mass test: TS0(OxxOOOxx)TS7 MS_Class=37
Mass test: TS0(OxxOOOxx)TS7 MS_Class=38
Mass test: TS0(OxxOOOxx)TS7 MS_Class=39
Mass test: TS0(OxxOOOxx)TS7 MS_Class=40
Mass test: TS0(OxxOOOxx)TS7 MS_Class=41
Mass test: TS0(OxxOOOxx)TS7 MS_Class=42
Mass test: TS0(OxxOOOxx)TS7 MS_Class=43
Mass test: TS0(OxxOOOxx)TS7 MS_Class=44
Mass test: TS0(OxxOOOxx)TS7 MS_Class=45
Mass test: TS0(OxxOOOxO)TS7 MS_Class=0
Mass test: TS0(OxxOOOxO)TS7 MS_Class=1
Mass test: TS0(OxxOOOxO)TS7 MS_Class=2
Mass test: TS0(OxxOOOxO)TS7 MS_Class=3
Mass test: TS0(OxxOOOxO)TS7 MS_Class=4
Mass test: TS0(OxxOOOxO)TS7 MS_Class=5
Mass test: TS0(OxxOOOxO)TS7 MS_Class=6
Mass test: TS0(OxxOOOxO)TS7 MS_Class=7
Mass test: TS0(OxxOOOxO)TS7 MS_Class=8
Mass test: TS0(OxxOOOxO)TS7 MS_Class=9
Mass test: TS0(OxxOOOxO)TS7 MS_Class=10
Mass test: TS0(OxxOOOxO)TS7 MS_Class=11
Mass test: TS0(OxxOOOxO)TS7 MS_Class=12
Mass test: TS0(OxxOOOxO)TS7 MS_Class=13
Mass test: TS0(OxxOOOxO)TS7 MS_Class=14
Mass test: TS0(OxxOOOxO)TS7 MS_Class=15
Mass test: TS0(OxxOOOxO)TS7 MS_Class=16
Mass test: TS0(OxxOOOxO)TS7 MS_Class=17
Mass test: TS0(OxxOOOxO)TS7 MS_Class=18
Mass test: TS0(OxxOOOxO)TS7 MS_Class=19
Mass test: TS0(OxxOOOxO)TS7 MS_Class=20
Mass test: TS0(OxxOOOxO)TS7 MS_Class=21
Mass test: TS0(OxxOOOxO)TS7 MS_Class=22
Mass test: TS0(OxxOOOxO)TS7 MS_Class=23
Mass test: TS0(OxxOOOxO)TS7 MS_Class=24
Mass test: TS0(OxxOOOxO)TS7 MS_Class=25
Mass test: TS0(OxxOOOxO)TS7 MS_Class=26
Mass test: TS0(OxxOOOxO)TS7 MS_Class=27
Mass test: TS0(OxxOOOxO)TS7 MS_Class=28
Mass test: TS0(OxxOOOxO)TS7 MS_Class=29
Mass test: TS0(OxxOOOxO)TS7 MS_Class=30
Mass test: TS0(OxxOOOxO)TS7 MS_Class=31
Mass test: TS0(OxxOOOxO)TS7 MS_Class=32
Mass test: TS0(OxxOOOxO)TS7 MS_Class=33
Mass test: TS0(OxxOOOxO)TS7 MS_Class=34
Mass test: TS0(OxxOOOxO)TS7 MS_Class=35
Mass test: TS0(OxxOOOxO)TS7 MS_Class=36
Mass test: TS0(OxxOOOxO)TS7 MS_Class=37
Mass test: TS0(OxxOOOxO)TS7 MS_Class=38
Mass test: TS0(OxxOOOxO)TS7 MS_Class=39
Mass test: TS0(OxxOOOxO)TS7 MS_Class=40
Mass test: TS0(OxxOOOxO)TS7 MS_Class=41
Mass test: TS0(OxxOOOxO)TS7 MS_Class=42
Mass test: TS0(OxxOOOxO)TS7 MS_Class=43
Mass test: TS0(OxxOOOxO)TS7 MS_Class=44
Mass test: TS0(OxxOOOxO)TS7 MS_Class=45
Mass test: TS0(OxxOOOOx)TS7 MS_Class=0
Mass test: TS0(OxxOOOOx)TS7 MS_Class=1
Mass test: TS0(OxxOOOOx)TS7 MS_Class=2
Mass test: TS0(OxxOOOOx)TS7 MS_Class=3
Mass test: TS0(OxxOOOOx)TS7 MS_Class=4
Mass test: TS0(OxxOOOOx)TS7 MS_Class=5
Mass test: TS0(OxxOOOOx)TS7 MS_Class=6
Mass test: TS0(OxxOOOOx)TS7 MS_Class=7
Mass test: TS0(OxxOOOOx)TS7 MS_Class=8
Mass test: TS0(OxxOOOOx)TS7 MS_Class=9
Mass test: TS0(OxxOOOOx)TS7 MS_Class=10
Mass test: TS0(OxxOOOOx)TS7 MS_Class=11
Mass test: TS0(OxxOOOOx)TS7 MS_Class=12
Mass test: TS0(OxxOOOOx)TS7 MS_Class=13
Mass test: TS0(OxxOOOOx)TS7 MS_Class=14
Mass test: TS0(OxxOOOOx)TS7 MS_Class=15
Mass test: TS0(OxxOOOOx)TS7 MS_Class=16
Mass test: TS0(OxxOOOOx)TS7 MS_Class=17
Mass test: TS0(OxxOOOOx)TS7 MS_Class=18
Mass test: TS0(OxxOOOOx)TS7 MS_Class=19
Mass test: TS0(OxxOOOOx)TS7 MS_Class=20
Mass test: TS0(OxxOOOOx)TS7 MS_Class=21
Mass test: TS0(OxxOOOOx)TS7 MS_Class=22
Mass test: TS0(OxxOOOOx)TS7 MS_Class=23
Mass test: TS0(OxxOOOOx)TS7 MS_Class=24
Mass test: TS0(OxxOOOOx)TS7 MS_Class=25
Mass test: TS0(OxxOOOOx)TS7 MS_Class=26
Mass test: TS0(OxxOOOOx)TS7 MS_Class=27
Mass test: TS0(OxxOOOOx)TS7 MS_Class=28
Mass test: TS0(OxxOOOOx)TS7 MS_Class=29
Mass test: TS0(OxxOOOOx)TS7 MS_Class=30
Mass test: TS0(OxxOOOOx)TS7 MS_Class=31
Mass test: TS0(OxxOOOOx)TS7 MS_Class=32
Mass test: TS0(OxxOOOOx)TS7 MS_Class=33
Mass test: TS0(OxxOOOOx)TS7 MS_Class=34
Mass test: TS0(OxxOOOOx)TS7 MS_Class=35
Mass test: TS0(OxxOOOOx)TS7 MS_Class=36
Mass test: TS0(OxxOOOOx)TS7 MS_Class=37
Mass test: TS0(OxxOOOOx)TS7 MS_Class=38
Mass test: TS0(OxxOOOOx)TS7 MS_Class=39
Mass test: TS0(OxxOOOOx)TS7 MS_Class=40
Mass test: TS0(OxxOOOOx)TS7 MS_Class=41
Mass test: TS0(OxxOOOOx)TS7 MS_Class=42
Mass test: TS0(OxxOOOOx)TS7 MS_Class=43
Mass test: TS0(OxxOOOOx)TS7 MS_Class=44
Mass test: TS0(OxxOOOOx)TS7 MS_Class=45
Mass test: TS0(OxxOOOOO)TS7 MS_Class=0
Mass test: TS0(OxxOOOOO)TS7 MS_Class=1
Mass test: TS0(OxxOOOOO)TS7 MS_Class=2
Mass test: TS0(OxxOOOOO)TS7 MS_Class=3
Mass test: TS0(OxxOOOOO)TS7 MS_Class=4
Mass test: TS0(OxxOOOOO)TS7 MS_Class=5
Mass test: TS0(OxxOOOOO)TS7 MS_Class=6
Mass test: TS0(OxxOOOOO)TS7 MS_Class=7
Mass test: TS0(OxxOOOOO)TS7 MS_Class=8
Mass test: TS0(OxxOOOOO)TS7 MS_Class=9
Mass test: TS0(OxxOOOOO)TS7 MS_Class=10
Mass test: TS0(OxxOOOOO)TS7 MS_Class=11
Mass test: TS0(OxxOOOOO)TS7 MS_Class=12
Mass test: TS0(OxxOOOOO)TS7 MS_Class=13
Mass test: TS0(OxxOOOOO)TS7 MS_Class=14
Mass test: TS0(OxxOOOOO)TS7 MS_Class=15
Mass test: TS0(OxxOOOOO)TS7 MS_Class=16
Mass test: TS0(OxxOOOOO)TS7 MS_Class=17
Mass test: TS0(OxxOOOOO)TS7 MS_Class=18
Mass test: TS0(OxxOOOOO)TS7 MS_Class=19
Mass test: TS0(OxxOOOOO)TS7 MS_Class=20
Mass test: TS0(OxxOOOOO)TS7 MS_Class=21
Mass test: TS0(OxxOOOOO)TS7 MS_Class=22
Mass test: TS0(OxxOOOOO)TS7 MS_Class=23
Mass test: TS0(OxxOOOOO)TS7 MS_Class=24
Mass test: TS0(OxxOOOOO)TS7 MS_Class=25
Mass test: TS0(OxxOOOOO)TS7 MS_Class=26
Mass test: TS0(OxxOOOOO)TS7 MS_Class=27
Mass test: TS0(OxxOOOOO)TS7 MS_Class=28
Mass test: TS0(OxxOOOOO)TS7 MS_Class=29
Mass test: TS0(OxxOOOOO)TS7 MS_Class=30
Mass test: TS0(OxxOOOOO)TS7 MS_Class=31
Mass test: TS0(OxxOOOOO)TS7 MS_Class=32
Mass test: TS0(OxxOOOOO)TS7 MS_Class=33
Mass test: TS0(OxxOOOOO)TS7 MS_Class=34
Mass test: TS0(OxxOOOOO)TS7 MS_Class=35
Mass test: TS0(OxxOOOOO)TS7 MS_Class=36
Mass test: TS0(OxxOOOOO)TS7 MS_Class=37
Mass test: TS0(OxxOOOOO)TS7 MS_Class=38
Mass test: TS0(OxxOOOOO)TS7 MS_Class=39
Mass test: TS0(OxxOOOOO)TS7 MS_Class=40
Mass test: TS0(OxxOOOOO)TS7 MS_Class=41
Mass test: TS0(OxxOOOOO)TS7 MS_Class=42
Mass test: TS0(OxxOOOOO)TS7 MS_Class=43
Mass test: TS0(OxxOOOOO)TS7 MS_Class=44
Mass test: TS0(OxxOOOOO)TS7 MS_Class=45
Mass test: TS0(OxOxxxxx)TS7 MS_Class=0
Mass test: TS0(OxOxxxxx)TS7 MS_Class=1
Mass test: TS0(OxOxxxxx)TS7 MS_Class=2
Mass test: TS0(OxOxxxxx)TS7 MS_Class=3
Mass test: TS0(OxOxxxxx)TS7 MS_Class=4
Mass test: TS0(OxOxxxxx)TS7 MS_Class=5
Mass test: TS0(OxOxxxxx)TS7 MS_Class=6
Mass test: TS0(OxOxxxxx)TS7 MS_Class=7
Mass test: TS0(OxOxxxxx)TS7 MS_Class=8
Mass test: TS0(OxOxxxxx)TS7 MS_Class=9
Mass test: TS0(OxOxxxxx)TS7 MS_Class=10
Mass test: TS0(OxOxxxxx)TS7 MS_Class=11
Mass test: TS0(OxOxxxxx)TS7 MS_Class=12
Mass test: TS0(OxOxxxxx)TS7 MS_Class=13
Mass test: TS0(OxOxxxxx)TS7 MS_Class=14
Mass test: TS0(OxOxxxxx)TS7 MS_Class=15
Mass test: TS0(OxOxxxxx)TS7 MS_Class=16
Mass test: TS0(OxOxxxxx)TS7 MS_Class=17
Mass test: TS0(OxOxxxxx)TS7 MS_Class=18
Mass test: TS0(OxOxxxxx)TS7 MS_Class=19
Mass test: TS0(OxOxxxxx)TS7 MS_Class=20
Mass test: TS0(OxOxxxxx)TS7 MS_Class=21
Mass test: TS0(OxOxxxxx)TS7 MS_Class=22
Mass test: TS0(OxOxxxxx)TS7 MS_Class=23
Mass test: TS0(OxOxxxxx)TS7 MS_Class=24
Mass test: TS0(OxOxxxxx)TS7 MS_Class=25
Mass test: TS0(OxOxxxxx)TS7 MS_Class=26
Mass test: TS0(OxOxxxxx)TS7 MS_Class=27
Mass test: TS0(OxOxxxxx)TS7 MS_Class=28
Mass test: TS0(OxOxxxxx)TS7 MS_Class=29
Mass test: TS0(OxOxxxxx)TS7 MS_Class=30
Mass test: TS0(OxOxxxxx)TS7 MS_Class=31
Mass test: TS0(OxOxxxxx)TS7 MS_Class=32
Mass test: TS0(OxOxxxxx)TS7 MS_Class=33
Mass test: TS0(OxOxxxxx)TS7 MS_Class=34
Mass test: TS0(OxOxxxxx)TS7 MS_Class=35
Mass test: TS0(OxOxxxxx)TS7 MS_Class=36
Mass test: TS0(OxOxxxxx)TS7 MS_Class=37
Mass test: TS0(OxOxxxxx)TS7 MS_Class=38
Mass test: TS0(OxOxxxxx)TS7 MS_Class=39
Mass test: TS0(OxOxxxxx)TS7 MS_Class=40
Mass test: TS0(OxOxxxxx)TS7 MS_Class=41
Mass test: TS0(OxOxxxxx)TS7 MS_Class=42
Mass test: TS0(OxOxxxxx)TS7 MS_Class=43
Mass test: TS0(OxOxxxxx)TS7 MS_Class=44
Mass test: TS0(OxOxxxxx)TS7 MS_Class=45
Mass test: TS0(OxOxxxxO)TS7 MS_Class=0
Mass test: TS0(OxOxxxxO)TS7 MS_Class=1
Mass test: TS0(OxOxxxxO)TS7 MS_Class=2
Mass test: TS0(OxOxxxxO)TS7 MS_Class=3
Mass test: TS0(OxOxxxxO)TS7 MS_Class=4
Mass test: TS0(OxOxxxxO)TS7 MS_Class=5
Mass test: TS0(OxOxxxxO)TS7 MS_Class=6
Mass test: TS0(OxOxxxxO)TS7 MS_Class=7
Mass test: TS0(OxOxxxxO)TS7 MS_Class=8
Mass test: TS0(OxOxxxxO)TS7 MS_Class=9
Mass test: TS0(OxOxxxxO)TS7 MS_Class=10
Mass test: TS0(OxOxxxxO)TS7 MS_Class=11
Mass test: TS0(OxOxxxxO)TS7 MS_Class=12
Mass test: TS0(OxOxxxxO)TS7 MS_Class=13
Mass test: TS0(OxOxxxxO)TS7 MS_Class=14
Mass test: TS0(OxOxxxxO)TS7 MS_Class=15
Mass test: TS0(OxOxxxxO)TS7 MS_Class=16
Mass test: TS0(OxOxxxxO)TS7 MS_Class=17
Mass test: TS0(OxOxxxxO)TS7 MS_Class=18
Mass test: TS0(OxOxxxxO)TS7 MS_Class=19
Mass test: TS0(OxOxxxxO)TS7 MS_Class=20
Mass test: TS0(OxOxxxxO)TS7 MS_Class=21
Mass test: TS0(OxOxxxxO)TS7 MS_Class=22
Mass test: TS0(OxOxxxxO)TS7 MS_Class=23
Mass test: TS0(OxOxxxxO)TS7 MS_Class=24
Mass test: TS0(OxOxxxxO)TS7 MS_Class=25
Mass test: TS0(OxOxxxxO)TS7 MS_Class=26
Mass test: TS0(OxOxxxxO)TS7 MS_Class=27
Mass test: TS0(OxOxxxxO)TS7 MS_Class=28
Mass test: TS0(OxOxxxxO)TS7 MS_Class=29
Mass test: TS0(OxOxxxxO)TS7 MS_Class=30
Mass test: TS0(OxOxxxxO)TS7 MS_Class=31
Mass test: TS0(OxOxxxxO)TS7 MS_Class=32
Mass test: TS0(OxOxxxxO)TS7 MS_Class=33
Mass test: TS0(OxOxxxxO)TS7 MS_Class=34
Mass test: TS0(OxOxxxxO)TS7 MS_Class=35
Mass test: TS0(OxOxxxxO)TS7 MS_Class=36
Mass test: TS0(OxOxxxxO)TS7 MS_Class=37
Mass test: TS0(OxOxxxxO)TS7 MS_Class=38
Mass test: TS0(OxOxxxxO)TS7 MS_Class=39
Mass test: TS0(OxOxxxxO)TS7 MS_Class=40
Mass test: TS0(OxOxxxxO)TS7 MS_Class=41
Mass test: TS0(OxOxxxxO)TS7 MS_Class=42
Mass test: TS0(OxOxxxxO)TS7 MS_Class=43
Mass test: TS0(OxOxxxxO)TS7 MS_Class=44
Mass test: TS0(OxOxxxxO)TS7 MS_Class=45
Mass test: TS0(OxOxxxOx)TS7 MS_Class=0
Mass test: TS0(OxOxxxOx)TS7 MS_Class=1
Mass test: TS0(OxOxxxOx)TS7 MS_Class=2
Mass test: TS0(OxOxxxOx)TS7 MS_Class=3
Mass test: TS0(OxOxxxOx)TS7 MS_Class=4
Mass test: TS0(OxOxxxOx)TS7 MS_Class=5
Mass test: TS0(OxOxxxOx)TS7 MS_Class=6
Mass test: TS0(OxOxxxOx)TS7 MS_Class=7
Mass test: TS0(OxOxxxOx)TS7 MS_Class=8
Mass test: TS0(OxOxxxOx)TS7 MS_Class=9
Mass test: TS0(OxOxxxOx)TS7 MS_Class=10
Mass test: TS0(OxOxxxOx)TS7 MS_Class=11
Mass test: TS0(OxOxxxOx)TS7 MS_Class=12
Mass test: TS0(OxOxxxOx)TS7 MS_Class=13
Mass test: TS0(OxOxxxOx)TS7 MS_Class=14
Mass test: TS0(OxOxxxOx)TS7 MS_Class=15
Mass test: TS0(OxOxxxOx)TS7 MS_Class=16
Mass test: TS0(OxOxxxOx)TS7 MS_Class=17
Mass test: TS0(OxOxxxOx)TS7 MS_Class=18
Mass test: TS0(OxOxxxOx)TS7 MS_Class=19
Mass test: TS0(OxOxxxOx)TS7 MS_Class=20
Mass test: TS0(OxOxxxOx)TS7 MS_Class=21
Mass test: TS0(OxOxxxOx)TS7 MS_Class=22
Mass test: TS0(OxOxxxOx)TS7 MS_Class=23
Mass test: TS0(OxOxxxOx)TS7 MS_Class=24
Mass test: TS0(OxOxxxOx)TS7 MS_Class=25
Mass test: TS0(OxOxxxOx)TS7 MS_Class=26
Mass test: TS0(OxOxxxOx)TS7 MS_Class=27
Mass test: TS0(OxOxxxOx)TS7 MS_Class=28
Mass test: TS0(OxOxxxOx)TS7 MS_Class=29
Mass test: TS0(OxOxxxOx)TS7 MS_Class=30
Mass test: TS0(OxOxxxOx)TS7 MS_Class=31
Mass test: TS0(OxOxxxOx)TS7 MS_Class=32
Mass test: TS0(OxOxxxOx)TS7 MS_Class=33
Mass test: TS0(OxOxxxOx)TS7 MS_Class=34
Mass test: TS0(OxOxxxOx)TS7 MS_Class=35
Mass test: TS0(OxOxxxOx)TS7 MS_Class=36
Mass test: TS0(OxOxxxOx)TS7 MS_Class=37
Mass test: TS0(OxOxxxOx)TS7 MS_Class=38
Mass test: TS0(OxOxxxOx)TS7 MS_Class=39
Mass test: TS0(OxOxxxOx)TS7 MS_Class=40
Mass test: TS0(OxOxxxOx)TS7 MS_Class=41
Mass test: TS0(OxOxxxOx)TS7 MS_Class=42
Mass test: TS0(OxOxxxOx)TS7 MS_Class=43
Mass test: TS0(OxOxxxOx)TS7 MS_Class=44
Mass test: TS0(OxOxxxOx)TS7 MS_Class=45
Mass test: TS0(OxOxxxOO)TS7 MS_Class=0
Mass test: TS0(OxOxxxOO)TS7 MS_Class=1
Mass test: TS0(OxOxxxOO)TS7 MS_Class=2
Mass test: TS0(OxOxxxOO)TS7 MS_Class=3
Mass test: TS0(OxOxxxOO)TS7 MS_Class=4
Mass test: TS0(OxOxxxOO)TS7 MS_Class=5
Mass test: TS0(OxOxxxOO)TS7 MS_Class=6
Mass test: TS0(OxOxxxOO)TS7 MS_Class=7
Mass test: TS0(OxOxxxOO)TS7 MS_Class=8
Mass test: TS0(OxOxxxOO)TS7 MS_Class=9
Mass test: TS0(OxOxxxOO)TS7 MS_Class=10
Mass test: TS0(OxOxxxOO)TS7 MS_Class=11
Mass test: TS0(OxOxxxOO)TS7 MS_Class=12
Mass test: TS0(OxOxxxOO)TS7 MS_Class=13
Mass test: TS0(OxOxxxOO)TS7 MS_Class=14
Mass test: TS0(OxOxxxOO)TS7 MS_Class=15
Mass test: TS0(OxOxxxOO)TS7 MS_Class=16
Mass test: TS0(OxOxxxOO)TS7 MS_Class=17
Mass test: TS0(OxOxxxOO)TS7 MS_Class=18
Mass test: TS0(OxOxxxOO)TS7 MS_Class=19
Mass test: TS0(OxOxxxOO)TS7 MS_Class=20
Mass test: TS0(OxOxxxOO)TS7 MS_Class=21
Mass test: TS0(OxOxxxOO)TS7 MS_Class=22
Mass test: TS0(OxOxxxOO)TS7 MS_Class=23
Mass test: TS0(OxOxxxOO)TS7 MS_Class=24
Mass test: TS0(OxOxxxOO)TS7 MS_Class=25
Mass test: TS0(OxOxxxOO)TS7 MS_Class=26
Mass test: TS0(OxOxxxOO)TS7 MS_Class=27
Mass test: TS0(OxOxxxOO)TS7 MS_Class=28
Mass test: TS0(OxOxxxOO)TS7 MS_Class=29
Mass test: TS0(OxOxxxOO)TS7 MS_Class=30
Mass test: TS0(OxOxxxOO)TS7 MS_Class=31
Mass test: TS0(OxOxxxOO)TS7 MS_Class=32
Mass test: TS0(OxOxxxOO)TS7 MS_Class=33
Mass test: TS0(OxOxxxOO)TS7 MS_Class=34
Mass test: TS0(OxOxxxOO)TS7 MS_Class=35
Mass test: TS0(OxOxxxOO)TS7 MS_Class=36
Mass test: TS0(OxOxxxOO)TS7 MS_Class=37
Mass test: TS0(OxOxxxOO)TS7 MS_Class=38
Mass test: TS0(OxOxxxOO)TS7 MS_Class=39
Mass test: TS0(OxOxxxOO)TS7 MS_Class=40
Mass test: TS0(OxOxxxOO)TS7 MS_Class=41
Mass test: TS0(OxOxxxOO)TS7 MS_Class=42
Mass test: TS0(OxOxxxOO)TS7 MS_Class=43
Mass test: TS0(OxOxxxOO)TS7 MS_Class=44
Mass test: TS0(OxOxxxOO)TS7 MS_Class=45
Mass test: TS0(OxOxxOxx)TS7 MS_Class=0
Mass test: TS0(OxOxxOxx)TS7 MS_Class=1
Mass test: TS0(OxOxxOxx)TS7 MS_Class=2
Mass test: TS0(OxOxxOxx)TS7 MS_Class=3
Mass test: TS0(OxOxxOxx)TS7 MS_Class=4
Mass test: TS0(OxOxxOxx)TS7 MS_Class=5
Mass test: TS0(OxOxxOxx)TS7 MS_Class=6
Mass test: TS0(OxOxxOxx)TS7 MS_Class=7
Mass test: TS0(OxOxxOxx)TS7 MS_Class=8
Mass test: TS0(OxOxxOxx)TS7 MS_Class=9
Mass test: TS0(OxOxxOxx)TS7 MS_Class=10
Mass test: TS0(OxOxxOxx)TS7 MS_Class=11
Mass test: TS0(OxOxxOxx)TS7 MS_Class=12
Mass test: TS0(OxOxxOxx)TS7 MS_Class=13
Mass test: TS0(OxOxxOxx)TS7 MS_Class=14
Mass test: TS0(OxOxxOxx)TS7 MS_Class=15
Mass test: TS0(OxOxxOxx)TS7 MS_Class=16
Mass test: TS0(OxOxxOxx)TS7 MS_Class=17
Mass test: TS0(OxOxxOxx)TS7 MS_Class=18
Mass test: TS0(OxOxxOxx)TS7 MS_Class=19
Mass test: TS0(OxOxxOxx)TS7 MS_Class=20
Mass test: TS0(OxOxxOxx)TS7 MS_Class=21
Mass test: TS0(OxOxxOxx)TS7 MS_Class=22
Mass test: TS0(OxOxxOxx)TS7 MS_Class=23
Mass test: TS0(OxOxxOxx)TS7 MS_Class=24
Mass test: TS0(OxOxxOxx)TS7 MS_Class=25
Mass test: TS0(OxOxxOxx)TS7 MS_Class=26
Mass test: TS0(OxOxxOxx)TS7 MS_Class=27
Mass test: TS0(OxOxxOxx)TS7 MS_Class=28
Mass test: TS0(OxOxxOxx)TS7 MS_Class=29
Mass test: TS0(OxOxxOxx)TS7 MS_Class=30
Mass test: TS0(OxOxxOxx)TS7 MS_Class=31
Mass test: TS0(OxOxxOxx)TS7 MS_Class=32
Mass test: TS0(OxOxxOxx)TS7 MS_Class=33
Mass test: TS0(OxOxxOxx)TS7 MS_Class=34
Mass test: TS0(OxOxxOxx)TS7 MS_Class=35
Mass test: TS0(OxOxxOxx)TS7 MS_Class=36
Mass test: TS0(OxOxxOxx)TS7 MS_Class=37
Mass test: TS0(OxOxxOxx)TS7 MS_Class=38
Mass test: TS0(OxOxxOxx)TS7 MS_Class=39
Mass test: TS0(OxOxxOxx)TS7 MS_Class=40
Mass test: TS0(OxOxxOxx)TS7 MS_Class=41
Mass test: TS0(OxOxxOxx)TS7 MS_Class=42
Mass test: TS0(OxOxxOxx)TS7 MS_Class=43
Mass test: TS0(OxOxxOxx)TS7 MS_Class=44
Mass test: TS0(OxOxxOxx)TS7 MS_Class=45
Mass test: TS0(OxOxxOxO)TS7 MS_Class=0
Mass test: TS0(OxOxxOxO)TS7 MS_Class=1
Mass test: TS0(OxOxxOxO)TS7 MS_Class=2
Mass test: TS0(OxOxxOxO)TS7 MS_Class=3
Mass test: TS0(OxOxxOxO)TS7 MS_Class=4
Mass test: TS0(OxOxxOxO)TS7 MS_Class=5
Mass test: TS0(OxOxxOxO)TS7 MS_Class=6
Mass test: TS0(OxOxxOxO)TS7 MS_Class=7
Mass test: TS0(OxOxxOxO)TS7 MS_Class=8
Mass test: TS0(OxOxxOxO)TS7 MS_Class=9
Mass test: TS0(OxOxxOxO)TS7 MS_Class=10
Mass test: TS0(OxOxxOxO)TS7 MS_Class=11
Mass test: TS0(OxOxxOxO)TS7 MS_Class=12
Mass test: TS0(OxOxxOxO)TS7 MS_Class=13
Mass test: TS0(OxOxxOxO)TS7 MS_Class=14
Mass test: TS0(OxOxxOxO)TS7 MS_Class=15
Mass test: TS0(OxOxxOxO)TS7 MS_Class=16
Mass test: TS0(OxOxxOxO)TS7 MS_Class=17
Mass test: TS0(OxOxxOxO)TS7 MS_Class=18
Mass test: TS0(OxOxxOxO)TS7 MS_Class=19
Mass test: TS0(OxOxxOxO)TS7 MS_Class=20
Mass test: TS0(OxOxxOxO)TS7 MS_Class=21
Mass test: TS0(OxOxxOxO)TS7 MS_Class=22
Mass test: TS0(OxOxxOxO)TS7 MS_Class=23
Mass test: TS0(OxOxxOxO)TS7 MS_Class=24
Mass test: TS0(OxOxxOxO)TS7 MS_Class=25
Mass test: TS0(OxOxxOxO)TS7 MS_Class=26
Mass test: TS0(OxOxxOxO)TS7 MS_Class=27
Mass test: TS0(OxOxxOxO)TS7 MS_Class=28
Mass test: TS0(OxOxxOxO)TS7 MS_Class=29
Mass test: TS0(OxOxxOxO)TS7 MS_Class=30
Mass test: TS0(OxOxxOxO)TS7 MS_Class=31
Mass test: TS0(OxOxxOxO)TS7 MS_Class=32
Mass test: TS0(OxOxxOxO)TS7 MS_Class=33
Mass test: TS0(OxOxxOxO)TS7 MS_Class=34
Mass test: TS0(OxOxxOxO)TS7 MS_Class=35
Mass test: TS0(OxOxxOxO)TS7 MS_Class=36
Mass test: TS0(OxOxxOxO)TS7 MS_Class=37
Mass test: TS0(OxOxxOxO)TS7 MS_Class=38
Mass test: TS0(OxOxxOxO)TS7 MS_Class=39
Mass test: TS0(OxOxxOxO)TS7 MS_Class=40
Mass test: TS0(OxOxxOxO)TS7 MS_Class=41
Mass test: TS0(OxOxxOxO)TS7 MS_Class=42
Mass test: TS0(OxOxxOxO)TS7 MS_Class=43
Mass test: TS0(OxOxxOxO)TS7 MS_Class=44
Mass test: TS0(OxOxxOxO)TS7 MS_Class=45
Mass test: TS0(OxOxxOOx)TS7 MS_Class=0
Mass test: TS0(OxOxxOOx)TS7 MS_Class=1
Mass test: TS0(OxOxxOOx)TS7 MS_Class=2
Mass test: TS0(OxOxxOOx)TS7 MS_Class=3
Mass test: TS0(OxOxxOOx)TS7 MS_Class=4
Mass test: TS0(OxOxxOOx)TS7 MS_Class=5
Mass test: TS0(OxOxxOOx)TS7 MS_Class=6
Mass test: TS0(OxOxxOOx)TS7 MS_Class=7
Mass test: TS0(OxOxxOOx)TS7 MS_Class=8
Mass test: TS0(OxOxxOOx)TS7 MS_Class=9
Mass test: TS0(OxOxxOOx)TS7 MS_Class=10
Mass test: TS0(OxOxxOOx)TS7 MS_Class=11
Mass test: TS0(OxOxxOOx)TS7 MS_Class=12
Mass test: TS0(OxOxxOOx)TS7 MS_Class=13
Mass test: TS0(OxOxxOOx)TS7 MS_Class=14
Mass test: TS0(OxOxxOOx)TS7 MS_Class=15
Mass test: TS0(OxOxxOOx)TS7 MS_Class=16
Mass test: TS0(OxOxxOOx)TS7 MS_Class=17
Mass test: TS0(OxOxxOOx)TS7 MS_Class=18
Mass test: TS0(OxOxxOOx)TS7 MS_Class=19
Mass test: TS0(OxOxxOOx)TS7 MS_Class=20
Mass test: TS0(OxOxxOOx)TS7 MS_Class=21
Mass test: TS0(OxOxxOOx)TS7 MS_Class=22
Mass test: TS0(OxOxxOOx)TS7 MS_Class=23
Mass test: TS0(OxOxxOOx)TS7 MS_Class=24
Mass test: TS0(OxOxxOOx)TS7 MS_Class=25
Mass test: TS0(OxOxxOOx)TS7 MS_Class=26
Mass test: TS0(OxOxxOOx)TS7 MS_Class=27
Mass test: TS0(OxOxxOOx)TS7 MS_Class=28
Mass test: TS0(OxOxxOOx)TS7 MS_Class=29
Mass test: TS0(OxOxxOOx)TS7 MS_Class=30
Mass test: TS0(OxOxxOOx)TS7 MS_Class=31
Mass test: TS0(OxOxxOOx)TS7 MS_Class=32
Mass test: TS0(OxOxxOOx)TS7 MS_Class=33
Mass test: TS0(OxOxxOOx)TS7 MS_Class=34
Mass test: TS0(OxOxxOOx)TS7 MS_Class=35
Mass test: TS0(OxOxxOOx)TS7 MS_Class=36
Mass test: TS0(OxOxxOOx)TS7 MS_Class=37
Mass test: TS0(OxOxxOOx)TS7 MS_Class=38
Mass test: TS0(OxOxxOOx)TS7 MS_Class=39
Mass test: TS0(OxOxxOOx)TS7 MS_Class=40
Mass test: TS0(OxOxxOOx)TS7 MS_Class=41
Mass test: TS0(OxOxxOOx)TS7 MS_Class=42
Mass test: TS0(OxOxxOOx)TS7 MS_Class=43
Mass test: TS0(OxOxxOOx)TS7 MS_Class=44
Mass test: TS0(OxOxxOOx)TS7 MS_Class=45
Mass test: TS0(OxOxxOOO)TS7 MS_Class=0
Mass test: TS0(OxOxxOOO)TS7 MS_Class=1
Mass test: TS0(OxOxxOOO)TS7 MS_Class=2
Mass test: TS0(OxOxxOOO)TS7 MS_Class=3
Mass test: TS0(OxOxxOOO)TS7 MS_Class=4
Mass test: TS0(OxOxxOOO)TS7 MS_Class=5
Mass test: TS0(OxOxxOOO)TS7 MS_Class=6
Mass test: TS0(OxOxxOOO)TS7 MS_Class=7
Mass test: TS0(OxOxxOOO)TS7 MS_Class=8
Mass test: TS0(OxOxxOOO)TS7 MS_Class=9
Mass test: TS0(OxOxxOOO)TS7 MS_Class=10
Mass test: TS0(OxOxxOOO)TS7 MS_Class=11
Mass test: TS0(OxOxxOOO)TS7 MS_Class=12
Mass test: TS0(OxOxxOOO)TS7 MS_Class=13
Mass test: TS0(OxOxxOOO)TS7 MS_Class=14
Mass test: TS0(OxOxxOOO)TS7 MS_Class=15
Mass test: TS0(OxOxxOOO)TS7 MS_Class=16
Mass test: TS0(OxOxxOOO)TS7 MS_Class=17
Mass test: TS0(OxOxxOOO)TS7 MS_Class=18
Mass test: TS0(OxOxxOOO)TS7 MS_Class=19
Mass test: TS0(OxOxxOOO)TS7 MS_Class=20
Mass test: TS0(OxOxxOOO)TS7 MS_Class=21
Mass test: TS0(OxOxxOOO)TS7 MS_Class=22
Mass test: TS0(OxOxxOOO)TS7 MS_Class=23
Mass test: TS0(OxOxxOOO)TS7 MS_Class=24
Mass test: TS0(OxOxxOOO)TS7 MS_Class=25
Mass test: TS0(OxOxxOOO)TS7 MS_Class=26
Mass test: TS0(OxOxxOOO)TS7 MS_Class=27
Mass test: TS0(OxOxxOOO)TS7 MS_Class=28
Mass test: TS0(OxOxxOOO)TS7 MS_Class=29
Mass test: TS0(OxOxxOOO)TS7 MS_Class=30
Mass test: TS0(OxOxxOOO)TS7 MS_Class=31
Mass test: TS0(OxOxxOOO)TS7 MS_Class=32
Mass test: TS0(OxOxxOOO)TS7 MS_Class=33
Mass test: TS0(OxOxxOOO)TS7 MS_Class=34
Mass test: TS0(OxOxxOOO)TS7 MS_Class=35
Mass test: TS0(OxOxxOOO)TS7 MS_Class=36
Mass test: TS0(OxOxxOOO)TS7 MS_Class=37
Mass test: TS0(OxOxxOOO)TS7 MS_Class=38
Mass test: TS0(OxOxxOOO)TS7 MS_Class=39
Mass test: TS0(OxOxxOOO)TS7 MS_Class=40
Mass test: TS0(OxOxxOOO)TS7 MS_Class=41
Mass test: TS0(OxOxxOOO)TS7 MS_Class=42
Mass test: TS0(OxOxxOOO)TS7 MS_Class=43
Mass test: TS0(OxOxxOOO)TS7 MS_Class=44
Mass test: TS0(OxOxxOOO)TS7 MS_Class=45
Mass test: TS0(OxOxOxxx)TS7 MS_Class=0
Mass test: TS0(OxOxOxxx)TS7 MS_Class=1
Mass test: TS0(OxOxOxxx)TS7 MS_Class=2
Mass test: TS0(OxOxOxxx)TS7 MS_Class=3
Mass test: TS0(OxOxOxxx)TS7 MS_Class=4
Mass test: TS0(OxOxOxxx)TS7 MS_Class=5
Mass test: TS0(OxOxOxxx)TS7 MS_Class=6
Mass test: TS0(OxOxOxxx)TS7 MS_Class=7
Mass test: TS0(OxOxOxxx)TS7 MS_Class=8
Mass test: TS0(OxOxOxxx)TS7 MS_Class=9
Mass test: TS0(OxOxOxxx)TS7 MS_Class=10
Mass test: TS0(OxOxOxxx)TS7 MS_Class=11
Mass test: TS0(OxOxOxxx)TS7 MS_Class=12
Mass test: TS0(OxOxOxxx)TS7 MS_Class=13
Mass test: TS0(OxOxOxxx)TS7 MS_Class=14
Mass test: TS0(OxOxOxxx)TS7 MS_Class=15
Mass test: TS0(OxOxOxxx)TS7 MS_Class=16
Mass test: TS0(OxOxOxxx)TS7 MS_Class=17
Mass test: TS0(OxOxOxxx)TS7 MS_Class=18
Mass test: TS0(OxOxOxxx)TS7 MS_Class=19
Mass test: TS0(OxOxOxxx)TS7 MS_Class=20
Mass test: TS0(OxOxOxxx)TS7 MS_Class=21
Mass test: TS0(OxOxOxxx)TS7 MS_Class=22
Mass test: TS0(OxOxOxxx)TS7 MS_Class=23
Mass test: TS0(OxOxOxxx)TS7 MS_Class=24
Mass test: TS0(OxOxOxxx)TS7 MS_Class=25
Mass test: TS0(OxOxOxxx)TS7 MS_Class=26
Mass test: TS0(OxOxOxxx)TS7 MS_Class=27
Mass test: TS0(OxOxOxxx)TS7 MS_Class=28
Mass test: TS0(OxOxOxxx)TS7 MS_Class=29
Mass test: TS0(OxOxOxxx)TS7 MS_Class=30
Mass test: TS0(OxOxOxxx)TS7 MS_Class=31
Mass test: TS0(OxOxOxxx)TS7 MS_Class=32
Mass test: TS0(OxOxOxxx)TS7 MS_Class=33
Mass test: TS0(OxOxOxxx)TS7 MS_Class=34
Mass test: TS0(OxOxOxxx)TS7 MS_Class=35
Mass test: TS0(OxOxOxxx)TS7 MS_Class=36
Mass test: TS0(OxOxOxxx)TS7 MS_Class=37
Mass test: TS0(OxOxOxxx)TS7 MS_Class=38
Mass test: TS0(OxOxOxxx)TS7 MS_Class=39
Mass test: TS0(OxOxOxxx)TS7 MS_Class=40
Mass test: TS0(OxOxOxxx)TS7 MS_Class=41
Mass test: TS0(OxOxOxxx)TS7 MS_Class=42
Mass test: TS0(OxOxOxxx)TS7 MS_Class=43
Mass test: TS0(OxOxOxxx)TS7 MS_Class=44
Mass test: TS0(OxOxOxxx)TS7 MS_Class=45
Mass test: TS0(OxOxOxxO)TS7 MS_Class=0
Mass test: TS0(OxOxOxxO)TS7 MS_Class=1
Mass test: TS0(OxOxOxxO)TS7 MS_Class=2
Mass test: TS0(OxOxOxxO)TS7 MS_Class=3
Mass test: TS0(OxOxOxxO)TS7 MS_Class=4
Mass test: TS0(OxOxOxxO)TS7 MS_Class=5
Mass test: TS0(OxOxOxxO)TS7 MS_Class=6
Mass test: TS0(OxOxOxxO)TS7 MS_Class=7
Mass test: TS0(OxOxOxxO)TS7 MS_Class=8
Mass test: TS0(OxOxOxxO)TS7 MS_Class=9
Mass test: TS0(OxOxOxxO)TS7 MS_Class=10
Mass test: TS0(OxOxOxxO)TS7 MS_Class=11
Mass test: TS0(OxOxOxxO)TS7 MS_Class=12
Mass test: TS0(OxOxOxxO)TS7 MS_Class=13
Mass test: TS0(OxOxOxxO)TS7 MS_Class=14
Mass test: TS0(OxOxOxxO)TS7 MS_Class=15
Mass test: TS0(OxOxOxxO)TS7 MS_Class=16
Mass test: TS0(OxOxOxxO)TS7 MS_Class=17
Mass test: TS0(OxOxOxxO)TS7 MS_Class=18
Mass test: TS0(OxOxOxxO)TS7 MS_Class=19
Mass test: TS0(OxOxOxxO)TS7 MS_Class=20
Mass test: TS0(OxOxOxxO)TS7 MS_Class=21
Mass test: TS0(OxOxOxxO)TS7 MS_Class=22
Mass test: TS0(OxOxOxxO)TS7 MS_Class=23
Mass test: TS0(OxOxOxxO)TS7 MS_Class=24
Mass test: TS0(OxOxOxxO)TS7 MS_Class=25
Mass test: TS0(OxOxOxxO)TS7 MS_Class=26
Mass test: TS0(OxOxOxxO)TS7 MS_Class=27
Mass test: TS0(OxOxOxxO)TS7 MS_Class=28
Mass test: TS0(OxOxOxxO)TS7 MS_Class=29
Mass test: TS0(OxOxOxxO)TS7 MS_Class=30
Mass test: TS0(OxOxOxxO)TS7 MS_Class=31
Mass test: TS0(OxOxOxxO)TS7 MS_Class=32
Mass test: TS0(OxOxOxxO)TS7 MS_Class=33
Mass test: TS0(OxOxOxxO)TS7 MS_Class=34
Mass test: TS0(OxOxOxxO)TS7 MS_Class=35
Mass test: TS0(OxOxOxxO)TS7 MS_Class=36
Mass test: TS0(OxOxOxxO)TS7 MS_Class=37
Mass test: TS0(OxOxOxxO)TS7 MS_Class=38
Mass test: TS0(OxOxOxxO)TS7 MS_Class=39
Mass test: TS0(OxOxOxxO)TS7 MS_Class=40
Mass test: TS0(OxOxOxxO)TS7 MS_Class=41
Mass test: TS0(OxOxOxxO)TS7 MS_Class=42
Mass test: TS0(OxOxOxxO)TS7 MS_Class=43
Mass test: TS0(OxOxOxxO)TS7 MS_Class=44
Mass test: TS0(OxOxOxxO)TS7 MS_Class=45
Mass test: TS0(OxOxOxOx)TS7 MS_Class=0
Mass test: TS0(OxOxOxOx)TS7 MS_Class=1
Mass test: TS0(OxOxOxOx)TS7 MS_Class=2
Mass test: TS0(OxOxOxOx)TS7 MS_Class=3
Mass test: TS0(OxOxOxOx)TS7 MS_Class=4
Mass test: TS0(OxOxOxOx)TS7 MS_Class=5
Mass test: TS0(OxOxOxOx)TS7 MS_Class=6
Mass test: TS0(OxOxOxOx)TS7 MS_Class=7
Mass test: TS0(OxOxOxOx)TS7 MS_Class=8
Mass test: TS0(OxOxOxOx)TS7 MS_Class=9
Mass test: TS0(OxOxOxOx)TS7 MS_Class=10
Mass test: TS0(OxOxOxOx)TS7 MS_Class=11
Mass test: TS0(OxOxOxOx)TS7 MS_Class=12
Mass test: TS0(OxOxOxOx)TS7 MS_Class=13
Mass test: TS0(OxOxOxOx)TS7 MS_Class=14
Mass test: TS0(OxOxOxOx)TS7 MS_Class=15
Mass test: TS0(OxOxOxOx)TS7 MS_Class=16
Mass test: TS0(OxOxOxOx)TS7 MS_Class=17
Mass test: TS0(OxOxOxOx)TS7 MS_Class=18
Mass test: TS0(OxOxOxOx)TS7 MS_Class=19
Mass test: TS0(OxOxOxOx)TS7 MS_Class=20
Mass test: TS0(OxOxOxOx)TS7 MS_Class=21
Mass test: TS0(OxOxOxOx)TS7 MS_Class=22
Mass test: TS0(OxOxOxOx)TS7 MS_Class=23
Mass test: TS0(OxOxOxOx)TS7 MS_Class=24
Mass test: TS0(OxOxOxOx)TS7 MS_Class=25
Mass test: TS0(OxOxOxOx)TS7 MS_Class=26
Mass test: TS0(OxOxOxOx)TS7 MS_Class=27
Mass test: TS0(OxOxOxOx)TS7 MS_Class=28
Mass test: TS0(OxOxOxOx)TS7 MS_Class=29
Mass test: TS0(OxOxOxOx)TS7 MS_Class=30
Mass test: TS0(OxOxOxOx)TS7 MS_Class=31
Mass test: TS0(OxOxOxOx)TS7 MS_Class=32
Mass test: TS0(OxOxOxOx)TS7 MS_Class=33
Mass test: TS0(OxOxOxOx)TS7 MS_Class=34
Mass test: TS0(OxOxOxOx)TS7 MS_Class=35
Mass test: TS0(OxOxOxOx)TS7 MS_Class=36
Mass test: TS0(OxOxOxOx)TS7 MS_Class=37
Mass test: TS0(OxOxOxOx)TS7 MS_Class=38
Mass test: TS0(OxOxOxOx)TS7 MS_Class=39
Mass test: TS0(OxOxOxOx)TS7 MS_Class=40
Mass test: TS0(OxOxOxOx)TS7 MS_Class=41
Mass test: TS0(OxOxOxOx)TS7 MS_Class=42
Mass test: TS0(OxOxOxOx)TS7 MS_Class=43
Mass test: TS0(OxOxOxOx)TS7 MS_Class=44
Mass test: TS0(OxOxOxOx)TS7 MS_Class=45
Mass test: TS0(OxOxOxOO)TS7 MS_Class=0
Mass test: TS0(OxOxOxOO)TS7 MS_Class=1
Mass test: TS0(OxOxOxOO)TS7 MS_Class=2
Mass test: TS0(OxOxOxOO)TS7 MS_Class=3
Mass test: TS0(OxOxOxOO)TS7 MS_Class=4
Mass test: TS0(OxOxOxOO)TS7 MS_Class=5
Mass test: TS0(OxOxOxOO)TS7 MS_Class=6
Mass test: TS0(OxOxOxOO)TS7 MS_Class=7
Mass test: TS0(OxOxOxOO)TS7 MS_Class=8
Mass test: TS0(OxOxOxOO)TS7 MS_Class=9
Mass test: TS0(OxOxOxOO)TS7 MS_Class=10
Mass test: TS0(OxOxOxOO)TS7 MS_Class=11
Mass test: TS0(OxOxOxOO)TS7 MS_Class=12
Mass test: TS0(OxOxOxOO)TS7 MS_Class=13
Mass test: TS0(OxOxOxOO)TS7 MS_Class=14
Mass test: TS0(OxOxOxOO)TS7 MS_Class=15
Mass test: TS0(OxOxOxOO)TS7 MS_Class=16
Mass test: TS0(OxOxOxOO)TS7 MS_Class=17
Mass test: TS0(OxOxOxOO)TS7 MS_Class=18
Mass test: TS0(OxOxOxOO)TS7 MS_Class=19
Mass test: TS0(OxOxOxOO)TS7 MS_Class=20
Mass test: TS0(OxOxOxOO)TS7 MS_Class=21
Mass test: TS0(OxOxOxOO)TS7 MS_Class=22
Mass test: TS0(OxOxOxOO)TS7 MS_Class=23
Mass test: TS0(OxOxOxOO)TS7 MS_Class=24
Mass test: TS0(OxOxOxOO)TS7 MS_Class=25
Mass test: TS0(OxOxOxOO)TS7 MS_Class=26
Mass test: TS0(OxOxOxOO)TS7 MS_Class=27
Mass test: TS0(OxOxOxOO)TS7 MS_Class=28
Mass test: TS0(OxOxOxOO)TS7 MS_Class=29
Mass test: TS0(OxOxOxOO)TS7 MS_Class=30
Mass test: TS0(OxOxOxOO)TS7 MS_Class=31
Mass test: TS0(OxOxOxOO)TS7 MS_Class=32
Mass test: TS0(OxOxOxOO)TS7 MS_Class=33
Mass test: TS0(OxOxOxOO)TS7 MS_Class=34
Mass test: TS0(OxOxOxOO)TS7 MS_Class=35
Mass test: TS0(OxOxOxOO)TS7 MS_Class=36
Mass test: TS0(OxOxOxOO)TS7 MS_Class=37
Mass test: TS0(OxOxOxOO)TS7 MS_Class=38
Mass test: TS0(OxOxOxOO)TS7 MS_Class=39
Mass test: TS0(OxOxOxOO)TS7 MS_Class=40
Mass test: TS0(OxOxOxOO)TS7 MS_Class=41
Mass test: TS0(OxOxOxOO)TS7 MS_Class=42
Mass test: TS0(OxOxOxOO)TS7 MS_Class=43
Mass test: TS0(OxOxOxOO)TS7 MS_Class=44
Mass test: TS0(OxOxOxOO)TS7 MS_Class=45
Mass test: TS0(OxOxOOxx)TS7 MS_Class=0
Mass test: TS0(OxOxOOxx)TS7 MS_Class=1
Mass test: TS0(OxOxOOxx)TS7 MS_Class=2
Mass test: TS0(OxOxOOxx)TS7 MS_Class=3
Mass test: TS0(OxOxOOxx)TS7 MS_Class=4
Mass test: TS0(OxOxOOxx)TS7 MS_Class=5
Mass test: TS0(OxOxOOxx)TS7 MS_Class=6
Mass test: TS0(OxOxOOxx)TS7 MS_Class=7
Mass test: TS0(OxOxOOxx)TS7 MS_Class=8
Mass test: TS0(OxOxOOxx)TS7 MS_Class=9
Mass test: TS0(OxOxOOxx)TS7 MS_Class=10
Mass test: TS0(OxOxOOxx)TS7 MS_Class=11
Mass test: TS0(OxOxOOxx)TS7 MS_Class=12
Mass test: TS0(OxOxOOxx)TS7 MS_Class=13
Mass test: TS0(OxOxOOxx)TS7 MS_Class=14
Mass test: TS0(OxOxOOxx)TS7 MS_Class=15
Mass test: TS0(OxOxOOxx)TS7 MS_Class=16
Mass test: TS0(OxOxOOxx)TS7 MS_Class=17
Mass test: TS0(OxOxOOxx)TS7 MS_Class=18
Mass test: TS0(OxOxOOxx)TS7 MS_Class=19
Mass test: TS0(OxOxOOxx)TS7 MS_Class=20
Mass test: TS0(OxOxOOxx)TS7 MS_Class=21
Mass test: TS0(OxOxOOxx)TS7 MS_Class=22
Mass test: TS0(OxOxOOxx)TS7 MS_Class=23
Mass test: TS0(OxOxOOxx)TS7 MS_Class=24
Mass test: TS0(OxOxOOxx)TS7 MS_Class=25
Mass test: TS0(OxOxOOxx)TS7 MS_Class=26
Mass test: TS0(OxOxOOxx)TS7 MS_Class=27
Mass test: TS0(OxOxOOxx)TS7 MS_Class=28
Mass test: TS0(OxOxOOxx)TS7 MS_Class=29
Mass test: TS0(OxOxOOxx)TS7 MS_Class=30
Mass test: TS0(OxOxOOxx)TS7 MS_Class=31
Mass test: TS0(OxOxOOxx)TS7 MS_Class=32
Mass test: TS0(OxOxOOxx)TS7 MS_Class=33
Mass test: TS0(OxOxOOxx)TS7 MS_Class=34
Mass test: TS0(OxOxOOxx)TS7 MS_Class=35
Mass test: TS0(OxOxOOxx)TS7 MS_Class=36
Mass test: TS0(OxOxOOxx)TS7 MS_Class=37
Mass test: TS0(OxOxOOxx)TS7 MS_Class=38
Mass test: TS0(OxOxOOxx)TS7 MS_Class=39
Mass test: TS0(OxOxOOxx)TS7 MS_Class=40
Mass test: TS0(OxOxOOxx)TS7 MS_Class=41
Mass test: TS0(OxOxOOxx)TS7 MS_Class=42
Mass test: TS0(OxOxOOxx)TS7 MS_Class=43
Mass test: TS0(OxOxOOxx)TS7 MS_Class=44
Mass test: TS0(OxOxOOxx)TS7 MS_Class=45
Mass test: TS0(OxOxOOxO)TS7 MS_Class=0
Mass test: TS0(OxOxOOxO)TS7 MS_Class=1
Mass test: TS0(OxOxOOxO)TS7 MS_Class=2
Mass test: TS0(OxOxOOxO)TS7 MS_Class=3
Mass test: TS0(OxOxOOxO)TS7 MS_Class=4
Mass test: TS0(OxOxOOxO)TS7 MS_Class=5
Mass test: TS0(OxOxOOxO)TS7 MS_Class=6
Mass test: TS0(OxOxOOxO)TS7 MS_Class=7
Mass test: TS0(OxOxOOxO)TS7 MS_Class=8
Mass test: TS0(OxOxOOxO)TS7 MS_Class=9
Mass test: TS0(OxOxOOxO)TS7 MS_Class=10
Mass test: TS0(OxOxOOxO)TS7 MS_Class=11
Mass test: TS0(OxOxOOxO)TS7 MS_Class=12
Mass test: TS0(OxOxOOxO)TS7 MS_Class=13
Mass test: TS0(OxOxOOxO)TS7 MS_Class=14
Mass test: TS0(OxOxOOxO)TS7 MS_Class=15
Mass test: TS0(OxOxOOxO)TS7 MS_Class=16
Mass test: TS0(OxOxOOxO)TS7 MS_Class=17
Mass test: TS0(OxOxOOxO)TS7 MS_Class=18
Mass test: TS0(OxOxOOxO)TS7 MS_Class=19
Mass test: TS0(OxOxOOxO)TS7 MS_Class=20
Mass test: TS0(OxOxOOxO)TS7 MS_Class=21
Mass test: TS0(OxOxOOxO)TS7 MS_Class=22
Mass test: TS0(OxOxOOxO)TS7 MS_Class=23
Mass test: TS0(OxOxOOxO)TS7 MS_Class=24
Mass test: TS0(OxOxOOxO)TS7 MS_Class=25
Mass test: TS0(OxOxOOxO)TS7 MS_Class=26
Mass test: TS0(OxOxOOxO)TS7 MS_Class=27
Mass test: TS0(OxOxOOxO)TS7 MS_Class=28
Mass test: TS0(OxOxOOxO)TS7 MS_Class=29
Mass test: TS0(OxOxOOxO)TS7 MS_Class=30
Mass test: TS0(OxOxOOxO)TS7 MS_Class=31
Mass test: TS0(OxOxOOxO)TS7 MS_Class=32
Mass test: TS0(OxOxOOxO)TS7 MS_Class=33
Mass test: TS0(OxOxOOxO)TS7 MS_Class=34
Mass test: TS0(OxOxOOxO)TS7 MS_Class=35
Mass test: TS0(OxOxOOxO)TS7 MS_Class=36
Mass test: TS0(OxOxOOxO)TS7 MS_Class=37
Mass test: TS0(OxOxOOxO)TS7 MS_Class=38
Mass test: TS0(OxOxOOxO)TS7 MS_Class=39
Mass test: TS0(OxOxOOxO)TS7 MS_Class=40
Mass test: TS0(OxOxOOxO)TS7 MS_Class=41
Mass test: TS0(OxOxOOxO)TS7 MS_Class=42
Mass test: TS0(OxOxOOxO)TS7 MS_Class=43
Mass test: TS0(OxOxOOxO)TS7 MS_Class=44
Mass test: TS0(OxOxOOxO)TS7 MS_Class=45
Mass test: TS0(OxOxOOOx)TS7 MS_Class=0
Mass test: TS0(OxOxOOOx)TS7 MS_Class=1
Mass test: TS0(OxOxOOOx)TS7 MS_Class=2
Mass test: TS0(OxOxOOOx)TS7 MS_Class=3
Mass test: TS0(OxOxOOOx)TS7 MS_Class=4
Mass test: TS0(OxOxOOOx)TS7 MS_Class=5
Mass test: TS0(OxOxOOOx)TS7 MS_Class=6
Mass test: TS0(OxOxOOOx)TS7 MS_Class=7
Mass test: TS0(OxOxOOOx)TS7 MS_Class=8
Mass test: TS0(OxOxOOOx)TS7 MS_Class=9
Mass test: TS0(OxOxOOOx)TS7 MS_Class=10
Mass test: TS0(OxOxOOOx)TS7 MS_Class=11
Mass test: TS0(OxOxOOOx)TS7 MS_Class=12
Mass test: TS0(OxOxOOOx)TS7 MS_Class=13
Mass test: TS0(OxOxOOOx)TS7 MS_Class=14
Mass test: TS0(OxOxOOOx)TS7 MS_Class=15
Mass test: TS0(OxOxOOOx)TS7 MS_Class=16
Mass test: TS0(OxOxOOOx)TS7 MS_Class=17
Mass test: TS0(OxOxOOOx)TS7 MS_Class=18
Mass test: TS0(OxOxOOOx)TS7 MS_Class=19
Mass test: TS0(OxOxOOOx)TS7 MS_Class=20
Mass test: TS0(OxOxOOOx)TS7 MS_Class=21
Mass test: TS0(OxOxOOOx)TS7 MS_Class=22
Mass test: TS0(OxOxOOOx)TS7 MS_Class=23
Mass test: TS0(OxOxOOOx)TS7 MS_Class=24
Mass test: TS0(OxOxOOOx)TS7 MS_Class=25
Mass test: TS0(OxOxOOOx)TS7 MS_Class=26
Mass test: TS0(OxOxOOOx)TS7 MS_Class=27
Mass test: TS0(OxOxOOOx)TS7 MS_Class=28
Mass test: TS0(OxOxOOOx)TS7 MS_Class=29
Mass test: TS0(OxOxOOOx)TS7 MS_Class=30
Mass test: TS0(OxOxOOOx)TS7 MS_Class=31
Mass test: TS0(OxOxOOOx)TS7 MS_Class=32
Mass test: TS0(OxOxOOOx)TS7 MS_Class=33
Mass test: TS0(OxOxOOOx)TS7 MS_Class=34
Mass test: TS0(OxOxOOOx)TS7 MS_Class=35
Mass test: TS0(OxOxOOOx)TS7 MS_Class=36
Mass test: TS0(OxOxOOOx)TS7 MS_Class=37
Mass test: TS0(OxOxOOOx)TS7 MS_Class=38
Mass test: TS0(OxOxOOOx)TS7 MS_Class=39
Mass test: TS0(OxOxOOOx)TS7 MS_Class=40
Mass test: TS0(OxOxOOOx)TS7 MS_Class=41
Mass test: TS0(OxOxOOOx)TS7 MS_Class=42
Mass test: TS0(OxOxOOOx)TS7 MS_Class=43
Mass test: TS0(OxOxOOOx)TS7 MS_Class=44
Mass test: TS0(OxOxOOOx)TS7 MS_Class=45
Mass test: TS0(OxOxOOOO)TS7 MS_Class=0
Mass test: TS0(OxOxOOOO)TS7 MS_Class=1
Mass test: TS0(OxOxOOOO)TS7 MS_Class=2
Mass test: TS0(OxOxOOOO)TS7 MS_Class=3
Mass test: TS0(OxOxOOOO)TS7 MS_Class=4
Mass test: TS0(OxOxOOOO)TS7 MS_Class=5
Mass test: TS0(OxOxOOOO)TS7 MS_Class=6
Mass test: TS0(OxOxOOOO)TS7 MS_Class=7
Mass test: TS0(OxOxOOOO)TS7 MS_Class=8
Mass test: TS0(OxOxOOOO)TS7 MS_Class=9
Mass test: TS0(OxOxOOOO)TS7 MS_Class=10
Mass test: TS0(OxOxOOOO)TS7 MS_Class=11
Mass test: TS0(OxOxOOOO)TS7 MS_Class=12
Mass test: TS0(OxOxOOOO)TS7 MS_Class=13
Mass test: TS0(OxOxOOOO)TS7 MS_Class=14
Mass test: TS0(OxOxOOOO)TS7 MS_Class=15
Mass test: TS0(OxOxOOOO)TS7 MS_Class=16
Mass test: TS0(OxOxOOOO)TS7 MS_Class=17
Mass test: TS0(OxOxOOOO)TS7 MS_Class=18
Mass test: TS0(OxOxOOOO)TS7 MS_Class=19
Mass test: TS0(OxOxOOOO)TS7 MS_Class=20
Mass test: TS0(OxOxOOOO)TS7 MS_Class=21
Mass test: TS0(OxOxOOOO)TS7 MS_Class=22
Mass test: TS0(OxOxOOOO)TS7 MS_Class=23
Mass test: TS0(OxOxOOOO)TS7 MS_Class=24
Mass test: TS0(OxOxOOOO)TS7 MS_Class=25
Mass test: TS0(OxOxOOOO)TS7 MS_Class=26
Mass test: TS0(OxOxOOOO)TS7 MS_Class=27
Mass test: TS0(OxOxOOOO)TS7 MS_Class=28
Mass test: TS0(OxOxOOOO)TS7 MS_Class=29
Mass test: TS0(OxOxOOOO)TS7 MS_Class=30
Mass test: TS0(OxOxOOOO)TS7 MS_Class=31
Mass test: TS0(OxOxOOOO)TS7 MS_Class=32
Mass test: TS0(OxOxOOOO)TS7 MS_Class=33
Mass test: TS0(OxOxOOOO)TS7 MS_Class=34
Mass test: TS0(OxOxOOOO)TS7 MS_Class=35
Mass test: TS0(OxOxOOOO)TS7 MS_Class=36
Mass test: TS0(OxOxOOOO)TS7 MS_Class=37
Mass test: TS0(OxOxOOOO)TS7 MS_Class=38
Mass test: TS0(OxOxOOOO)TS7 MS_Class=39
Mass test: TS0(OxOxOOOO)TS7 MS_Class=40
Mass test: TS0(OxOxOOOO)TS7 MS_Class=41
Mass test: TS0(OxOxOOOO)TS7 MS_Class=42
Mass test: TS0(OxOxOOOO)TS7 MS_Class=43
Mass test: TS0(OxOxOOOO)TS7 MS_Class=44
Mass test: TS0(OxOxOOOO)TS7 MS_Class=45
Mass test: TS0(OxOOxxxx)TS7 MS_Class=0
Mass test: TS0(OxOOxxxx)TS7 MS_Class=1
Mass test: TS0(OxOOxxxx)TS7 MS_Class=2
Mass test: TS0(OxOOxxxx)TS7 MS_Class=3
Mass test: TS0(OxOOxxxx)TS7 MS_Class=4
Mass test: TS0(OxOOxxxx)TS7 MS_Class=5
Mass test: TS0(OxOOxxxx)TS7 MS_Class=6
Mass test: TS0(OxOOxxxx)TS7 MS_Class=7
Mass test: TS0(OxOOxxxx)TS7 MS_Class=8
Mass test: TS0(OxOOxxxx)TS7 MS_Class=9
Mass test: TS0(OxOOxxxx)TS7 MS_Class=10
Mass test: TS0(OxOOxxxx)TS7 MS_Class=11
Mass test: TS0(OxOOxxxx)TS7 MS_Class=12
Mass test: TS0(OxOOxxxx)TS7 MS_Class=13
Mass test: TS0(OxOOxxxx)TS7 MS_Class=14
Mass test: TS0(OxOOxxxx)TS7 MS_Class=15
Mass test: TS0(OxOOxxxx)TS7 MS_Class=16
Mass test: TS0(OxOOxxxx)TS7 MS_Class=17
Mass test: TS0(OxOOxxxx)TS7 MS_Class=18
Mass test: TS0(OxOOxxxx)TS7 MS_Class=19
Mass test: TS0(OxOOxxxx)TS7 MS_Class=20
Mass test: TS0(OxOOxxxx)TS7 MS_Class=21
Mass test: TS0(OxOOxxxx)TS7 MS_Class=22
Mass test: TS0(OxOOxxxx)TS7 MS_Class=23
Mass test: TS0(OxOOxxxx)TS7 MS_Class=24
Mass test: TS0(OxOOxxxx)TS7 MS_Class=25
Mass test: TS0(OxOOxxxx)TS7 MS_Class=26
Mass test: TS0(OxOOxxxx)TS7 MS_Class=27
Mass test: TS0(OxOOxxxx)TS7 MS_Class=28
Mass test: TS0(OxOOxxxx)TS7 MS_Class=29
Mass test: TS0(OxOOxxxx)TS7 MS_Class=30
Mass test: TS0(OxOOxxxx)TS7 MS_Class=31
Mass test: TS0(OxOOxxxx)TS7 MS_Class=32
Mass test: TS0(OxOOxxxx)TS7 MS_Class=33
Mass test: TS0(OxOOxxxx)TS7 MS_Class=34
Mass test: TS0(OxOOxxxx)TS7 MS_Class=35
Mass test: TS0(OxOOxxxx)TS7 MS_Class=36
Mass test: TS0(OxOOxxxx)TS7 MS_Class=37
Mass test: TS0(OxOOxxxx)TS7 MS_Class=38
Mass test: TS0(OxOOxxxx)TS7 MS_Class=39
Mass test: TS0(OxOOxxxx)TS7 MS_Class=40
Mass test: TS0(OxOOxxxx)TS7 MS_Class=41
Mass test: TS0(OxOOxxxx)TS7 MS_Class=42
Mass test: TS0(OxOOxxxx)TS7 MS_Class=43
Mass test: TS0(OxOOxxxx)TS7 MS_Class=44
Mass test: TS0(OxOOxxxx)TS7 MS_Class=45
Mass test: TS0(OxOOxxxO)TS7 MS_Class=0
Mass test: TS0(OxOOxxxO)TS7 MS_Class=1
Mass test: TS0(OxOOxxxO)TS7 MS_Class=2
Mass test: TS0(OxOOxxxO)TS7 MS_Class=3
Mass test: TS0(OxOOxxxO)TS7 MS_Class=4
Mass test: TS0(OxOOxxxO)TS7 MS_Class=5
Mass test: TS0(OxOOxxxO)TS7 MS_Class=6
Mass test: TS0(OxOOxxxO)TS7 MS_Class=7
Mass test: TS0(OxOOxxxO)TS7 MS_Class=8
Mass test: TS0(OxOOxxxO)TS7 MS_Class=9
Mass test: TS0(OxOOxxxO)TS7 MS_Class=10
Mass test: TS0(OxOOxxxO)TS7 MS_Class=11
Mass test: TS0(OxOOxxxO)TS7 MS_Class=12
Mass test: TS0(OxOOxxxO)TS7 MS_Class=13
Mass test: TS0(OxOOxxxO)TS7 MS_Class=14
Mass test: TS0(OxOOxxxO)TS7 MS_Class=15
Mass test: TS0(OxOOxxxO)TS7 MS_Class=16
Mass test: TS0(OxOOxxxO)TS7 MS_Class=17
Mass test: TS0(OxOOxxxO)TS7 MS_Class=18
Mass test: TS0(OxOOxxxO)TS7 MS_Class=19
Mass test: TS0(OxOOxxxO)TS7 MS_Class=20
Mass test: TS0(OxOOxxxO)TS7 MS_Class=21
Mass test: TS0(OxOOxxxO)TS7 MS_Class=22
Mass test: TS0(OxOOxxxO)TS7 MS_Class=23
Mass test: TS0(OxOOxxxO)TS7 MS_Class=24
Mass test: TS0(OxOOxxxO)TS7 MS_Class=25
Mass test: TS0(OxOOxxxO)TS7 MS_Class=26
Mass test: TS0(OxOOxxxO)TS7 MS_Class=27
Mass test: TS0(OxOOxxxO)TS7 MS_Class=28
Mass test: TS0(OxOOxxxO)TS7 MS_Class=29
Mass test: TS0(OxOOxxxO)TS7 MS_Class=30
Mass test: TS0(OxOOxxxO)TS7 MS_Class=31
Mass test: TS0(OxOOxxxO)TS7 MS_Class=32
Mass test: TS0(OxOOxxxO)TS7 MS_Class=33
Mass test: TS0(OxOOxxxO)TS7 MS_Class=34
Mass test: TS0(OxOOxxxO)TS7 MS_Class=35
Mass test: TS0(OxOOxxxO)TS7 MS_Class=36
Mass test: TS0(OxOOxxxO)TS7 MS_Class=37
Mass test: TS0(OxOOxxxO)TS7 MS_Class=38
Mass test: TS0(OxOOxxxO)TS7 MS_Class=39
Mass test: TS0(OxOOxxxO)TS7 MS_Class=40
Mass test: TS0(OxOOxxxO)TS7 MS_Class=41
Mass test: TS0(OxOOxxxO)TS7 MS_Class=42
Mass test: TS0(OxOOxxxO)TS7 MS_Class=43
Mass test: TS0(OxOOxxxO)TS7 MS_Class=44
Mass test: TS0(OxOOxxxO)TS7 MS_Class=45
Mass test: TS0(OxOOxxOx)TS7 MS_Class=0
Mass test: TS0(OxOOxxOx)TS7 MS_Class=1
Mass test: TS0(OxOOxxOx)TS7 MS_Class=2
Mass test: TS0(OxOOxxOx)TS7 MS_Class=3
Mass test: TS0(OxOOxxOx)TS7 MS_Class=4
Mass test: TS0(OxOOxxOx)TS7 MS_Class=5
Mass test: TS0(OxOOxxOx)TS7 MS_Class=6
Mass test: TS0(OxOOxxOx)TS7 MS_Class=7
Mass test: TS0(OxOOxxOx)TS7 MS_Class=8
Mass test: TS0(OxOOxxOx)TS7 MS_Class=9
Mass test: TS0(OxOOxxOx)TS7 MS_Class=10
Mass test: TS0(OxOOxxOx)TS7 MS_Class=11
Mass test: TS0(OxOOxxOx)TS7 MS_Class=12
Mass test: TS0(OxOOxxOx)TS7 MS_Class=13
Mass test: TS0(OxOOxxOx)TS7 MS_Class=14
Mass test: TS0(OxOOxxOx)TS7 MS_Class=15
Mass test: TS0(OxOOxxOx)TS7 MS_Class=16
Mass test: TS0(OxOOxxOx)TS7 MS_Class=17
Mass test: TS0(OxOOxxOx)TS7 MS_Class=18
Mass test: TS0(OxOOxxOx)TS7 MS_Class=19
Mass test: TS0(OxOOxxOx)TS7 MS_Class=20
Mass test: TS0(OxOOxxOx)TS7 MS_Class=21
Mass test: TS0(OxOOxxOx)TS7 MS_Class=22
Mass test: TS0(OxOOxxOx)TS7 MS_Class=23
Mass test: TS0(OxOOxxOx)TS7 MS_Class=24
Mass test: TS0(OxOOxxOx)TS7 MS_Class=25
Mass test: TS0(OxOOxxOx)TS7 MS_Class=26
Mass test: TS0(OxOOxxOx)TS7 MS_Class=27
Mass test: TS0(OxOOxxOx)TS7 MS_Class=28
Mass test: TS0(OxOOxxOx)TS7 MS_Class=29
Mass test: TS0(OxOOxxOx)TS7 MS_Class=30
Mass test: TS0(OxOOxxOx)TS7 MS_Class=31
Mass test: TS0(OxOOxxOx)TS7 MS_Class=32
Mass test: TS0(OxOOxxOx)TS7 MS_Class=33
Mass test: TS0(OxOOxxOx)TS7 MS_Class=34
Mass test: TS0(OxOOxxOx)TS7 MS_Class=35
Mass test: TS0(OxOOxxOx)TS7 MS_Class=36
Mass test: TS0(OxOOxxOx)TS7 MS_Class=37
Mass test: TS0(OxOOxxOx)TS7 MS_Class=38
Mass test: TS0(OxOOxxOx)TS7 MS_Class=39
Mass test: TS0(OxOOxxOx)TS7 MS_Class=40
Mass test: TS0(OxOOxxOx)TS7 MS_Class=41
Mass test: TS0(OxOOxxOx)TS7 MS_Class=42
Mass test: TS0(OxOOxxOx)TS7 MS_Class=43
Mass test: TS0(OxOOxxOx)TS7 MS_Class=44
Mass test: TS0(OxOOxxOx)TS7 MS_Class=45
Mass test: TS0(OxOOxxOO)TS7 MS_Class=0
Mass test: TS0(OxOOxxOO)TS7 MS_Class=1
Mass test: TS0(OxOOxxOO)TS7 MS_Class=2
Mass test: TS0(OxOOxxOO)TS7 MS_Class=3
Mass test: TS0(OxOOxxOO)TS7 MS_Class=4
Mass test: TS0(OxOOxxOO)TS7 MS_Class=5
Mass test: TS0(OxOOxxOO)TS7 MS_Class=6
Mass test: TS0(OxOOxxOO)TS7 MS_Class=7
Mass test: TS0(OxOOxxOO)TS7 MS_Class=8
Mass test: TS0(OxOOxxOO)TS7 MS_Class=9
Mass test: TS0(OxOOxxOO)TS7 MS_Class=10
Mass test: TS0(OxOOxxOO)TS7 MS_Class=11
Mass test: TS0(OxOOxxOO)TS7 MS_Class=12
Mass test: TS0(OxOOxxOO)TS7 MS_Class=13
Mass test: TS0(OxOOxxOO)TS7 MS_Class=14
Mass test: TS0(OxOOxxOO)TS7 MS_Class=15
Mass test: TS0(OxOOxxOO)TS7 MS_Class=16
Mass test: TS0(OxOOxxOO)TS7 MS_Class=17
Mass test: TS0(OxOOxxOO)TS7 MS_Class=18
Mass test: TS0(OxOOxxOO)TS7 MS_Class=19
Mass test: TS0(OxOOxxOO)TS7 MS_Class=20
Mass test: TS0(OxOOxxOO)TS7 MS_Class=21
Mass test: TS0(OxOOxxOO)TS7 MS_Class=22
Mass test: TS0(OxOOxxOO)TS7 MS_Class=23
Mass test: TS0(OxOOxxOO)TS7 MS_Class=24
Mass test: TS0(OxOOxxOO)TS7 MS_Class=25
Mass test: TS0(OxOOxxOO)TS7 MS_Class=26
Mass test: TS0(OxOOxxOO)TS7 MS_Class=27
Mass test: TS0(OxOOxxOO)TS7 MS_Class=28
Mass test: TS0(OxOOxxOO)TS7 MS_Class=29
Mass test: TS0(OxOOxxOO)TS7 MS_Class=30
Mass test: TS0(OxOOxxOO)TS7 MS_Class=31
Mass test: TS0(OxOOxxOO)TS7 MS_Class=32
Mass test: TS0(OxOOxxOO)TS7 MS_Class=33
Mass test: TS0(OxOOxxOO)TS7 MS_Class=34
Mass test: TS0(OxOOxxOO)TS7 MS_Class=35
Mass test: TS0(OxOOxxOO)TS7 MS_Class=36
Mass test: TS0(OxOOxxOO)TS7 MS_Class=37
Mass test: TS0(OxOOxxOO)TS7 MS_Class=38
Mass test: TS0(OxOOxxOO)TS7 MS_Class=39
Mass test: TS0(OxOOxxOO)TS7 MS_Class=40
Mass test: TS0(OxOOxxOO)TS7 MS_Class=41
Mass test: TS0(OxOOxxOO)TS7 MS_Class=42
Mass test: TS0(OxOOxxOO)TS7 MS_Class=43
Mass test: TS0(OxOOxxOO)TS7 MS_Class=44
Mass test: TS0(OxOOxxOO)TS7 MS_Class=45
Mass test: TS0(OxOOxOxx)TS7 MS_Class=0
Mass test: TS0(OxOOxOxx)TS7 MS_Class=1
Mass test: TS0(OxOOxOxx)TS7 MS_Class=2
Mass test: TS0(OxOOxOxx)TS7 MS_Class=3
Mass test: TS0(OxOOxOxx)TS7 MS_Class=4
Mass test: TS0(OxOOxOxx)TS7 MS_Class=5
Mass test: TS0(OxOOxOxx)TS7 MS_Class=6
Mass test: TS0(OxOOxOxx)TS7 MS_Class=7
Mass test: TS0(OxOOxOxx)TS7 MS_Class=8
Mass test: TS0(OxOOxOxx)TS7 MS_Class=9
Mass test: TS0(OxOOxOxx)TS7 MS_Class=10
Mass test: TS0(OxOOxOxx)TS7 MS_Class=11
Mass test: TS0(OxOOxOxx)TS7 MS_Class=12
Mass test: TS0(OxOOxOxx)TS7 MS_Class=13
Mass test: TS0(OxOOxOxx)TS7 MS_Class=14
Mass test: TS0(OxOOxOxx)TS7 MS_Class=15
Mass test: TS0(OxOOxOxx)TS7 MS_Class=16
Mass test: TS0(OxOOxOxx)TS7 MS_Class=17
Mass test: TS0(OxOOxOxx)TS7 MS_Class=18
Mass test: TS0(OxOOxOxx)TS7 MS_Class=19
Mass test: TS0(OxOOxOxx)TS7 MS_Class=20
Mass test: TS0(OxOOxOxx)TS7 MS_Class=21
Mass test: TS0(OxOOxOxx)TS7 MS_Class=22
Mass test: TS0(OxOOxOxx)TS7 MS_Class=23
Mass test: TS0(OxOOxOxx)TS7 MS_Class=24
Mass test: TS0(OxOOxOxx)TS7 MS_Class=25
Mass test: TS0(OxOOxOxx)TS7 MS_Class=26
Mass test: TS0(OxOOxOxx)TS7 MS_Class=27
Mass test: TS0(OxOOxOxx)TS7 MS_Class=28
Mass test: TS0(OxOOxOxx)TS7 MS_Class=29
Mass test: TS0(OxOOxOxx)TS7 MS_Class=30
Mass test: TS0(OxOOxOxx)TS7 MS_Class=31
Mass test: TS0(OxOOxOxx)TS7 MS_Class=32
Mass test: TS0(OxOOxOxx)TS7 MS_Class=33
Mass test: TS0(OxOOxOxx)TS7 MS_Class=34
Mass test: TS0(OxOOxOxx)TS7 MS_Class=35
Mass test: TS0(OxOOxOxx)TS7 MS_Class=36
Mass test: TS0(OxOOxOxx)TS7 MS_Class=37
Mass test: TS0(OxOOxOxx)TS7 MS_Class=38
Mass test: TS0(OxOOxOxx)TS7 MS_Class=39
Mass test: TS0(OxOOxOxx)TS7 MS_Class=40
Mass test: TS0(OxOOxOxx)TS7 MS_Class=41
Mass test: TS0(OxOOxOxx)TS7 MS_Class=42
Mass test: TS0(OxOOxOxx)TS7 MS_Class=43
Mass test: TS0(OxOOxOxx)TS7 MS_Class=44
Mass test: TS0(OxOOxOxx)TS7 MS_Class=45
Mass test: TS0(OxOOxOxO)TS7 MS_Class=0
Mass test: TS0(OxOOxOxO)TS7 MS_Class=1
Mass test: TS0(OxOOxOxO)TS7 MS_Class=2
Mass test: TS0(OxOOxOxO)TS7 MS_Class=3
Mass test: TS0(OxOOxOxO)TS7 MS_Class=4
Mass test: TS0(OxOOxOxO)TS7 MS_Class=5
Mass test: TS0(OxOOxOxO)TS7 MS_Class=6
Mass test: TS0(OxOOxOxO)TS7 MS_Class=7
Mass test: TS0(OxOOxOxO)TS7 MS_Class=8
Mass test: TS0(OxOOxOxO)TS7 MS_Class=9
Mass test: TS0(OxOOxOxO)TS7 MS_Class=10
Mass test: TS0(OxOOxOxO)TS7 MS_Class=11
Mass test: TS0(OxOOxOxO)TS7 MS_Class=12
Mass test: TS0(OxOOxOxO)TS7 MS_Class=13
Mass test: TS0(OxOOxOxO)TS7 MS_Class=14
Mass test: TS0(OxOOxOxO)TS7 MS_Class=15
Mass test: TS0(OxOOxOxO)TS7 MS_Class=16
Mass test: TS0(OxOOxOxO)TS7 MS_Class=17
Mass test: TS0(OxOOxOxO)TS7 MS_Class=18
Mass test: TS0(OxOOxOxO)TS7 MS_Class=19
Mass test: TS0(OxOOxOxO)TS7 MS_Class=20
Mass test: TS0(OxOOxOxO)TS7 MS_Class=21
Mass test: TS0(OxOOxOxO)TS7 MS_Class=22
Mass test: TS0(OxOOxOxO)TS7 MS_Class=23
Mass test: TS0(OxOOxOxO)TS7 MS_Class=24
Mass test: TS0(OxOOxOxO)TS7 MS_Class=25
Mass test: TS0(OxOOxOxO)TS7 MS_Class=26
Mass test: TS0(OxOOxOxO)TS7 MS_Class=27
Mass test: TS0(OxOOxOxO)TS7 MS_Class=28
Mass test: TS0(OxOOxOxO)TS7 MS_Class=29
Mass test: TS0(OxOOxOxO)TS7 MS_Class=30
Mass test: TS0(OxOOxOxO)TS7 MS_Class=31
Mass test: TS0(OxOOxOxO)TS7 MS_Class=32
Mass test: TS0(OxOOxOxO)TS7 MS_Class=33
Mass test: TS0(OxOOxOxO)TS7 MS_Class=34
Mass test: TS0(OxOOxOxO)TS7 MS_Class=35
Mass test: TS0(OxOOxOxO)TS7 MS_Class=36
Mass test: TS0(OxOOxOxO)TS7 MS_Class=37
Mass test: TS0(OxOOxOxO)TS7 MS_Class=38
Mass test: TS0(OxOOxOxO)TS7 MS_Class=39
Mass test: TS0(OxOOxOxO)TS7 MS_Class=40
Mass test: TS0(OxOOxOxO)TS7 MS_Class=41
Mass test: TS0(OxOOxOxO)TS7 MS_Class=42
Mass test: TS0(OxOOxOxO)TS7 MS_Class=43
Mass test: TS0(OxOOxOxO)TS7 MS_Class=44
Mass test: TS0(OxOOxOxO)TS7 MS_Class=45
Mass test: TS0(OxOOxOOx)TS7 MS_Class=0
Mass test: TS0(OxOOxOOx)TS7 MS_Class=1
Mass test: TS0(OxOOxOOx)TS7 MS_Class=2
Mass test: TS0(OxOOxOOx)TS7 MS_Class=3
Mass test: TS0(OxOOxOOx)TS7 MS_Class=4
Mass test: TS0(OxOOxOOx)TS7 MS_Class=5
Mass test: TS0(OxOOxOOx)TS7 MS_Class=6
Mass test: TS0(OxOOxOOx)TS7 MS_Class=7
Mass test: TS0(OxOOxOOx)TS7 MS_Class=8
Mass test: TS0(OxOOxOOx)TS7 MS_Class=9
Mass test: TS0(OxOOxOOx)TS7 MS_Class=10
Mass test: TS0(OxOOxOOx)TS7 MS_Class=11
Mass test: TS0(OxOOxOOx)TS7 MS_Class=12
Mass test: TS0(OxOOxOOx)TS7 MS_Class=13
Mass test: TS0(OxOOxOOx)TS7 MS_Class=14
Mass test: TS0(OxOOxOOx)TS7 MS_Class=15
Mass test: TS0(OxOOxOOx)TS7 MS_Class=16
Mass test: TS0(OxOOxOOx)TS7 MS_Class=17
Mass test: TS0(OxOOxOOx)TS7 MS_Class=18
Mass test: TS0(OxOOxOOx)TS7 MS_Class=19
Mass test: TS0(OxOOxOOx)TS7 MS_Class=20
Mass test: TS0(OxOOxOOx)TS7 MS_Class=21
Mass test: TS0(OxOOxOOx)TS7 MS_Class=22
Mass test: TS0(OxOOxOOx)TS7 MS_Class=23
Mass test: TS0(OxOOxOOx)TS7 MS_Class=24
Mass test: TS0(OxOOxOOx)TS7 MS_Class=25
Mass test: TS0(OxOOxOOx)TS7 MS_Class=26
Mass test: TS0(OxOOxOOx)TS7 MS_Class=27
Mass test: TS0(OxOOxOOx)TS7 MS_Class=28
Mass test: TS0(OxOOxOOx)TS7 MS_Class=29
Mass test: TS0(OxOOxOOx)TS7 MS_Class=30
Mass test: TS0(OxOOxOOx)TS7 MS_Class=31
Mass test: TS0(OxOOxOOx)TS7 MS_Class=32
Mass test: TS0(OxOOxOOx)TS7 MS_Class=33
Mass test: TS0(OxOOxOOx)TS7 MS_Class=34
Mass test: TS0(OxOOxOOx)TS7 MS_Class=35
Mass test: TS0(OxOOxOOx)TS7 MS_Class=36
Mass test: TS0(OxOOxOOx)TS7 MS_Class=37
Mass test: TS0(OxOOxOOx)TS7 MS_Class=38
Mass test: TS0(OxOOxOOx)TS7 MS_Class=39
Mass test: TS0(OxOOxOOx)TS7 MS_Class=40
Mass test: TS0(OxOOxOOx)TS7 MS_Class=41
Mass test: TS0(OxOOxOOx)TS7 MS_Class=42
Mass test: TS0(OxOOxOOx)TS7 MS_Class=43
Mass test: TS0(OxOOxOOx)TS7 MS_Class=44
Mass test: TS0(OxOOxOOx)TS7 MS_Class=45
Mass test: TS0(OxOOxOOO)TS7 MS_Class=0
Mass test: TS0(OxOOxOOO)TS7 MS_Class=1
Mass test: TS0(OxOOxOOO)TS7 MS_Class=2
Mass test: TS0(OxOOxOOO)TS7 MS_Class=3
Mass test: TS0(OxOOxOOO)TS7 MS_Class=4
Mass test: TS0(OxOOxOOO)TS7 MS_Class=5
Mass test: TS0(OxOOxOOO)TS7 MS_Class=6
Mass test: TS0(OxOOxOOO)TS7 MS_Class=7
Mass test: TS0(OxOOxOOO)TS7 MS_Class=8
Mass test: TS0(OxOOxOOO)TS7 MS_Class=9
Mass test: TS0(OxOOxOOO)TS7 MS_Class=10
Mass test: TS0(OxOOxOOO)TS7 MS_Class=11
Mass test: TS0(OxOOxOOO)TS7 MS_Class=12
Mass test: TS0(OxOOxOOO)TS7 MS_Class=13
Mass test: TS0(OxOOxOOO)TS7 MS_Class=14
Mass test: TS0(OxOOxOOO)TS7 MS_Class=15
Mass test: TS0(OxOOxOOO)TS7 MS_Class=16
Mass test: TS0(OxOOxOOO)TS7 MS_Class=17
Mass test: TS0(OxOOxOOO)TS7 MS_Class=18
Mass test: TS0(OxOOxOOO)TS7 MS_Class=19
Mass test: TS0(OxOOxOOO)TS7 MS_Class=20
Mass test: TS0(OxOOxOOO)TS7 MS_Class=21
Mass test: TS0(OxOOxOOO)TS7 MS_Class=22
Mass test: TS0(OxOOxOOO)TS7 MS_Class=23
Mass test: TS0(OxOOxOOO)TS7 MS_Class=24
Mass test: TS0(OxOOxOOO)TS7 MS_Class=25
Mass test: TS0(OxOOxOOO)TS7 MS_Class=26
Mass test: TS0(OxOOxOOO)TS7 MS_Class=27
Mass test: TS0(OxOOxOOO)TS7 MS_Class=28
Mass test: TS0(OxOOxOOO)TS7 MS_Class=29
Mass test: TS0(OxOOxOOO)TS7 MS_Class=30
Mass test: TS0(OxOOxOOO)TS7 MS_Class=31
Mass test: TS0(OxOOxOOO)TS7 MS_Class=32
Mass test: TS0(OxOOxOOO)TS7 MS_Class=33
Mass test: TS0(OxOOxOOO)TS7 MS_Class=34
Mass test: TS0(OxOOxOOO)TS7 MS_Class=35
Mass test: TS0(OxOOxOOO)TS7 MS_Class=36
Mass test: TS0(OxOOxOOO)TS7 MS_Class=37
Mass test: TS0(OxOOxOOO)TS7 MS_Class=38
Mass test: TS0(OxOOxOOO)TS7 MS_Class=39
Mass test: TS0(OxOOxOOO)TS7 MS_Class=40
Mass test: TS0(OxOOxOOO)TS7 MS_Class=41
Mass test: TS0(OxOOxOOO)TS7 MS_Class=42
Mass test: TS0(OxOOxOOO)TS7 MS_Class=43
Mass test: TS0(OxOOxOOO)TS7 MS_Class=44
Mass test: TS0(OxOOxOOO)TS7 MS_Class=45
Mass test: TS0(OxOOOxxx)TS7 MS_Class=0
Mass test: TS0(OxOOOxxx)TS7 MS_Class=1
Mass test: TS0(OxOOOxxx)TS7 MS_Class=2
Mass test: TS0(OxOOOxxx)TS7 MS_Class=3
Mass test: TS0(OxOOOxxx)TS7 MS_Class=4
Mass test: TS0(OxOOOxxx)TS7 MS_Class=5
Mass test: TS0(OxOOOxxx)TS7 MS_Class=6
Mass test: TS0(OxOOOxxx)TS7 MS_Class=7
Mass test: TS0(OxOOOxxx)TS7 MS_Class=8
Mass test: TS0(OxOOOxxx)TS7 MS_Class=9
Mass test: TS0(OxOOOxxx)TS7 MS_Class=10
Mass test: TS0(OxOOOxxx)TS7 MS_Class=11
Mass test: TS0(OxOOOxxx)TS7 MS_Class=12
Mass test: TS0(OxOOOxxx)TS7 MS_Class=13
Mass test: TS0(OxOOOxxx)TS7 MS_Class=14
Mass test: TS0(OxOOOxxx)TS7 MS_Class=15
Mass test: TS0(OxOOOxxx)TS7 MS_Class=16
Mass test: TS0(OxOOOxxx)TS7 MS_Class=17
Mass test: TS0(OxOOOxxx)TS7 MS_Class=18
Mass test: TS0(OxOOOxxx)TS7 MS_Class=19
Mass test: TS0(OxOOOxxx)TS7 MS_Class=20
Mass test: TS0(OxOOOxxx)TS7 MS_Class=21
Mass test: TS0(OxOOOxxx)TS7 MS_Class=22
Mass test: TS0(OxOOOxxx)TS7 MS_Class=23
Mass test: TS0(OxOOOxxx)TS7 MS_Class=24
Mass test: TS0(OxOOOxxx)TS7 MS_Class=25
Mass test: TS0(OxOOOxxx)TS7 MS_Class=26
Mass test: TS0(OxOOOxxx)TS7 MS_Class=27
Mass test: TS0(OxOOOxxx)TS7 MS_Class=28
Mass test: TS0(OxOOOxxx)TS7 MS_Class=29
Mass test: TS0(OxOOOxxx)TS7 MS_Class=30
Mass test: TS0(OxOOOxxx)TS7 MS_Class=31
Mass test: TS0(OxOOOxxx)TS7 MS_Class=32
Mass test: TS0(OxOOOxxx)TS7 MS_Class=33
Mass test: TS0(OxOOOxxx)TS7 MS_Class=34
Mass test: TS0(OxOOOxxx)TS7 MS_Class=35
Mass test: TS0(OxOOOxxx)TS7 MS_Class=36
Mass test: TS0(OxOOOxxx)TS7 MS_Class=37
Mass test: TS0(OxOOOxxx)TS7 MS_Class=38
Mass test: TS0(OxOOOxxx)TS7 MS_Class=39
Mass test: TS0(OxOOOxxx)TS7 MS_Class=40
Mass test: TS0(OxOOOxxx)TS7 MS_Class=41
Mass test: TS0(OxOOOxxx)TS7 MS_Class=42
Mass test: TS0(OxOOOxxx)TS7 MS_Class=43
Mass test: TS0(OxOOOxxx)TS7 MS_Class=44
Mass test: TS0(OxOOOxxx)TS7 MS_Class=45
Mass test: TS0(OxOOOxxO)TS7 MS_Class=0
Mass test: TS0(OxOOOxxO)TS7 MS_Class=1
Mass test: TS0(OxOOOxxO)TS7 MS_Class=2
Mass test: TS0(OxOOOxxO)TS7 MS_Class=3
Mass test: TS0(OxOOOxxO)TS7 MS_Class=4
Mass test: TS0(OxOOOxxO)TS7 MS_Class=5
Mass test: TS0(OxOOOxxO)TS7 MS_Class=6
Mass test: TS0(OxOOOxxO)TS7 MS_Class=7
Mass test: TS0(OxOOOxxO)TS7 MS_Class=8
Mass test: TS0(OxOOOxxO)TS7 MS_Class=9
Mass test: TS0(OxOOOxxO)TS7 MS_Class=10
Mass test: TS0(OxOOOxxO)TS7 MS_Class=11
Mass test: TS0(OxOOOxxO)TS7 MS_Class=12
Mass test: TS0(OxOOOxxO)TS7 MS_Class=13
Mass test: TS0(OxOOOxxO)TS7 MS_Class=14
Mass test: TS0(OxOOOxxO)TS7 MS_Class=15
Mass test: TS0(OxOOOxxO)TS7 MS_Class=16
Mass test: TS0(OxOOOxxO)TS7 MS_Class=17
Mass test: TS0(OxOOOxxO)TS7 MS_Class=18
Mass test: TS0(OxOOOxxO)TS7 MS_Class=19
Mass test: TS0(OxOOOxxO)TS7 MS_Class=20
Mass test: TS0(OxOOOxxO)TS7 MS_Class=21
Mass test: TS0(OxOOOxxO)TS7 MS_Class=22
Mass test: TS0(OxOOOxxO)TS7 MS_Class=23
Mass test: TS0(OxOOOxxO)TS7 MS_Class=24
Mass test: TS0(OxOOOxxO)TS7 MS_Class=25
Mass test: TS0(OxOOOxxO)TS7 MS_Class=26
Mass test: TS0(OxOOOxxO)TS7 MS_Class=27
Mass test: TS0(OxOOOxxO)TS7 MS_Class=28
Mass test: TS0(OxOOOxxO)TS7 MS_Class=29
Mass test: TS0(OxOOOxxO)TS7 MS_Class=30
Mass test: TS0(OxOOOxxO)TS7 MS_Class=31
Mass test: TS0(OxOOOxxO)TS7 MS_Class=32
Mass test: TS0(OxOOOxxO)TS7 MS_Class=33
Mass test: TS0(OxOOOxxO)TS7 MS_Class=34
Mass test: TS0(OxOOOxxO)TS7 MS_Class=35
Mass test: TS0(OxOOOxxO)TS7 MS_Class=36
Mass test: TS0(OxOOOxxO)TS7 MS_Class=37
Mass test: TS0(OxOOOxxO)TS7 MS_Class=38
Mass test: TS0(OxOOOxxO)TS7 MS_Class=39
Mass test: TS0(OxOOOxxO)TS7 MS_Class=40
Mass test: TS0(OxOOOxxO)TS7 MS_Class=41
Mass test: TS0(OxOOOxxO)TS7 MS_Class=42
Mass test: TS0(OxOOOxxO)TS7 MS_Class=43
Mass test: TS0(OxOOOxxO)TS7 MS_Class=44
Mass test: TS0(OxOOOxxO)TS7 MS_Class=45
Mass test: TS0(OxOOOxOx)TS7 MS_Class=0
Mass test: TS0(OxOOOxOx)TS7 MS_Class=1
Mass test: TS0(OxOOOxOx)TS7 MS_Class=2
Mass test: TS0(OxOOOxOx)TS7 MS_Class=3
Mass test: TS0(OxOOOxOx)TS7 MS_Class=4
Mass test: TS0(OxOOOxOx)TS7 MS_Class=5
Mass test: TS0(OxOOOxOx)TS7 MS_Class=6
Mass test: TS0(OxOOOxOx)TS7 MS_Class=7
Mass test: TS0(OxOOOxOx)TS7 MS_Class=8
Mass test: TS0(OxOOOxOx)TS7 MS_Class=9
Mass test: TS0(OxOOOxOx)TS7 MS_Class=10
Mass test: TS0(OxOOOxOx)TS7 MS_Class=11
Mass test: TS0(OxOOOxOx)TS7 MS_Class=12
Mass test: TS0(OxOOOxOx)TS7 MS_Class=13
Mass test: TS0(OxOOOxOx)TS7 MS_Class=14
Mass test: TS0(OxOOOxOx)TS7 MS_Class=15
Mass test: TS0(OxOOOxOx)TS7 MS_Class=16
Mass test: TS0(OxOOOxOx)TS7 MS_Class=17
Mass test: TS0(OxOOOxOx)TS7 MS_Class=18
Mass test: TS0(OxOOOxOx)TS7 MS_Class=19
Mass test: TS0(OxOOOxOx)TS7 MS_Class=20
Mass test: TS0(OxOOOxOx)TS7 MS_Class=21
Mass test: TS0(OxOOOxOx)TS7 MS_Class=22
Mass test: TS0(OxOOOxOx)TS7 MS_Class=23
Mass test: TS0(OxOOOxOx)TS7 MS_Class=24
Mass test: TS0(OxOOOxOx)TS7 MS_Class=25
Mass test: TS0(OxOOOxOx)TS7 MS_Class=26
Mass test: TS0(OxOOOxOx)TS7 MS_Class=27
Mass test: TS0(OxOOOxOx)TS7 MS_Class=28
Mass test: TS0(OxOOOxOx)TS7 MS_Class=29
Mass test: TS0(OxOOOxOx)TS7 MS_Class=30
Mass test: TS0(OxOOOxOx)TS7 MS_Class=31
Mass test: TS0(OxOOOxOx)TS7 MS_Class=32
Mass test: TS0(OxOOOxOx)TS7 MS_Class=33
Mass test: TS0(OxOOOxOx)TS7 MS_Class=34
Mass test: TS0(OxOOOxOx)TS7 MS_Class=35
Mass test: TS0(OxOOOxOx)TS7 MS_Class=36
Mass test: TS0(OxOOOxOx)TS7 MS_Class=37
Mass test: TS0(OxOOOxOx)TS7 MS_Class=38
Mass test: TS0(OxOOOxOx)TS7 MS_Class=39
Mass test: TS0(OxOOOxOx)TS7 MS_Class=40
Mass test: TS0(OxOOOxOx)TS7 MS_Class=41
Mass test: TS0(OxOOOxOx)TS7 MS_Class=42
Mass test: TS0(OxOOOxOx)TS7 MS_Class=43
Mass test: TS0(OxOOOxOx)TS7 MS_Class=44
Mass test: TS0(OxOOOxOx)TS7 MS_Class=45
Mass test: TS0(OxOOOxOO)TS7 MS_Class=0
Mass test: TS0(OxOOOxOO)TS7 MS_Class=1
Mass test: TS0(OxOOOxOO)TS7 MS_Class=2
Mass test: TS0(OxOOOxOO)TS7 MS_Class=3
Mass test: TS0(OxOOOxOO)TS7 MS_Class=4
Mass test: TS0(OxOOOxOO)TS7 MS_Class=5
Mass test: TS0(OxOOOxOO)TS7 MS_Class=6
Mass test: TS0(OxOOOxOO)TS7 MS_Class=7
Mass test: TS0(OxOOOxOO)TS7 MS_Class=8
Mass test: TS0(OxOOOxOO)TS7 MS_Class=9
Mass test: TS0(OxOOOxOO)TS7 MS_Class=10
Mass test: TS0(OxOOOxOO)TS7 MS_Class=11
Mass test: TS0(OxOOOxOO)TS7 MS_Class=12
Mass test: TS0(OxOOOxOO)TS7 MS_Class=13
Mass test: TS0(OxOOOxOO)TS7 MS_Class=14
Mass test: TS0(OxOOOxOO)TS7 MS_Class=15
Mass test: TS0(OxOOOxOO)TS7 MS_Class=16
Mass test: TS0(OxOOOxOO)TS7 MS_Class=17
Mass test: TS0(OxOOOxOO)TS7 MS_Class=18
Mass test: TS0(OxOOOxOO)TS7 MS_Class=19
Mass test: TS0(OxOOOxOO)TS7 MS_Class=20
Mass test: TS0(OxOOOxOO)TS7 MS_Class=21
Mass test: TS0(OxOOOxOO)TS7 MS_Class=22
Mass test: TS0(OxOOOxOO)TS7 MS_Class=23
Mass test: TS0(OxOOOxOO)TS7 MS_Class=24
Mass test: TS0(OxOOOxOO)TS7 MS_Class=25
Mass test: TS0(OxOOOxOO)TS7 MS_Class=26
Mass test: TS0(OxOOOxOO)TS7 MS_Class=27
Mass test: TS0(OxOOOxOO)TS7 MS_Class=28
Mass test: TS0(OxOOOxOO)TS7 MS_Class=29
Mass test: TS0(OxOOOxOO)TS7 MS_Class=30
Mass test: TS0(OxOOOxOO)TS7 MS_Class=31
Mass test: TS0(OxOOOxOO)TS7 MS_Class=32
Mass test: TS0(OxOOOxOO)TS7 MS_Class=33
Mass test: TS0(OxOOOxOO)TS7 MS_Class=34
Mass test: TS0(OxOOOxOO)TS7 MS_Class=35
Mass test: TS0(OxOOOxOO)TS7 MS_Class=36
Mass test: TS0(OxOOOxOO)TS7 MS_Class=37
Mass test: TS0(OxOOOxOO)TS7 MS_Class=38
Mass test: TS0(OxOOOxOO)TS7 MS_Class=39
Mass test: TS0(OxOOOxOO)TS7 MS_Class=40
Mass test: TS0(OxOOOxOO)TS7 MS_Class=41
Mass test: TS0(OxOOOxOO)TS7 MS_Class=42
Mass test: TS0(OxOOOxOO)TS7 MS_Class=43
Mass test: TS0(OxOOOxOO)TS7 MS_Class=44
Mass test: TS0(OxOOOxOO)TS7 MS_Class=45
Mass test: TS0(OxOOOOxx)TS7 MS_Class=0
Mass test: TS0(OxOOOOxx)TS7 MS_Class=1
Mass test: TS0(OxOOOOxx)TS7 MS_Class=2
Mass test: TS0(OxOOOOxx)TS7 MS_Class=3
Mass test: TS0(OxOOOOxx)TS7 MS_Class=4
Mass test: TS0(OxOOOOxx)TS7 MS_Class=5
Mass test: TS0(OxOOOOxx)TS7 MS_Class=6
Mass test: TS0(OxOOOOxx)TS7 MS_Class=7
Mass test: TS0(OxOOOOxx)TS7 MS_Class=8
Mass test: TS0(OxOOOOxx)TS7 MS_Class=9
Mass test: TS0(OxOOOOxx)TS7 MS_Class=10
Mass test: TS0(OxOOOOxx)TS7 MS_Class=11
Mass test: TS0(OxOOOOxx)TS7 MS_Class=12
Mass test: TS0(OxOOOOxx)TS7 MS_Class=13
Mass test: TS0(OxOOOOxx)TS7 MS_Class=14
Mass test: TS0(OxOOOOxx)TS7 MS_Class=15
Mass test: TS0(OxOOOOxx)TS7 MS_Class=16
Mass test: TS0(OxOOOOxx)TS7 MS_Class=17
Mass test: TS0(OxOOOOxx)TS7 MS_Class=18
Mass test: TS0(OxOOOOxx)TS7 MS_Class=19
Mass test: TS0(OxOOOOxx)TS7 MS_Class=20
Mass test: TS0(OxOOOOxx)TS7 MS_Class=21
Mass test: TS0(OxOOOOxx)TS7 MS_Class=22
Mass test: TS0(OxOOOOxx)TS7 MS_Class=23
Mass test: TS0(OxOOOOxx)TS7 MS_Class=24
Mass test: TS0(OxOOOOxx)TS7 MS_Class=25
Mass test: TS0(OxOOOOxx)TS7 MS_Class=26
Mass test: TS0(OxOOOOxx)TS7 MS_Class=27
Mass test: TS0(OxOOOOxx)TS7 MS_Class=28
Mass test: TS0(OxOOOOxx)TS7 MS_Class=29
Mass test: TS0(OxOOOOxx)TS7 MS_Class=30
Mass test: TS0(OxOOOOxx)TS7 MS_Class=31
Mass test: TS0(OxOOOOxx)TS7 MS_Class=32
Mass test: TS0(OxOOOOxx)TS7 MS_Class=33
Mass test: TS0(OxOOOOxx)TS7 MS_Class=34
Mass test: TS0(OxOOOOxx)TS7 MS_Class=35
Mass test: TS0(OxOOOOxx)TS7 MS_Class=36
Mass test: TS0(OxOOOOxx)TS7 MS_Class=37
Mass test: TS0(OxOOOOxx)TS7 MS_Class=38
Mass test: TS0(OxOOOOxx)TS7 MS_Class=39
Mass test: TS0(OxOOOOxx)TS7 MS_Class=40
Mass test: TS0(OxOOOOxx)TS7 MS_Class=41
Mass test: TS0(OxOOOOxx)TS7 MS_Class=42
Mass test: TS0(OxOOOOxx)TS7 MS_Class=43
Mass test: TS0(OxOOOOxx)TS7 MS_Class=44
Mass test: TS0(OxOOOOxx)TS7 MS_Class=45
Mass test: TS0(OxOOOOxO)TS7 MS_Class=0
Mass test: TS0(OxOOOOxO)TS7 MS_Class=1
Mass test: TS0(OxOOOOxO)TS7 MS_Class=2
Mass test: TS0(OxOOOOxO)TS7 MS_Class=3
Mass test: TS0(OxOOOOxO)TS7 MS_Class=4
Mass test: TS0(OxOOOOxO)TS7 MS_Class=5
Mass test: TS0(OxOOOOxO)TS7 MS_Class=6
Mass test: TS0(OxOOOOxO)TS7 MS_Class=7
Mass test: TS0(OxOOOOxO)TS7 MS_Class=8
Mass test: TS0(OxOOOOxO)TS7 MS_Class=9
Mass test: TS0(OxOOOOxO)TS7 MS_Class=10
Mass test: TS0(OxOOOOxO)TS7 MS_Class=11
Mass test: TS0(OxOOOOxO)TS7 MS_Class=12
Mass test: TS0(OxOOOOxO)TS7 MS_Class=13
Mass test: TS0(OxOOOOxO)TS7 MS_Class=14
Mass test: TS0(OxOOOOxO)TS7 MS_Class=15
Mass test: TS0(OxOOOOxO)TS7 MS_Class=16
Mass test: TS0(OxOOOOxO)TS7 MS_Class=17
Mass test: TS0(OxOOOOxO)TS7 MS_Class=18
Mass test: TS0(OxOOOOxO)TS7 MS_Class=19
Mass test: TS0(OxOOOOxO)TS7 MS_Class=20
Mass test: TS0(OxOOOOxO)TS7 MS_Class=21
Mass test: TS0(OxOOOOxO)TS7 MS_Class=22
Mass test: TS0(OxOOOOxO)TS7 MS_Class=23
Mass test: TS0(OxOOOOxO)TS7 MS_Class=24
Mass test: TS0(OxOOOOxO)TS7 MS_Class=25
Mass test: TS0(OxOOOOxO)TS7 MS_Class=26
Mass test: TS0(OxOOOOxO)TS7 MS_Class=27
Mass test: TS0(OxOOOOxO)TS7 MS_Class=28
Mass test: TS0(OxOOOOxO)TS7 MS_Class=29
Mass test: TS0(OxOOOOxO)TS7 MS_Class=30
Mass test: TS0(OxOOOOxO)TS7 MS_Class=31
Mass test: TS0(OxOOOOxO)TS7 MS_Class=32
Mass test: TS0(OxOOOOxO)TS7 MS_Class=33
Mass test: TS0(OxOOOOxO)TS7 MS_Class=34
Mass test: TS0(OxOOOOxO)TS7 MS_Class=35
Mass test: TS0(OxOOOOxO)TS7 MS_Class=36
Mass test: TS0(OxOOOOxO)TS7 MS_Class=37
Mass test: TS0(OxOOOOxO)TS7 MS_Class=38
Mass test: TS0(OxOOOOxO)TS7 MS_Class=39
Mass test: TS0(OxOOOOxO)TS7 MS_Class=40
Mass test: TS0(OxOOOOxO)TS7 MS_Class=41
Mass test: TS0(OxOOOOxO)TS7 MS_Class=42
Mass test: TS0(OxOOOOxO)TS7 MS_Class=43
Mass test: TS0(OxOOOOxO)TS7 MS_Class=44
Mass test: TS0(OxOOOOxO)TS7 MS_Class=45
Mass test: TS0(OxOOOOOx)TS7 MS_Class=0
Mass test: TS0(OxOOOOOx)TS7 MS_Class=1
Mass test: TS0(OxOOOOOx)TS7 MS_Class=2
Mass test: TS0(OxOOOOOx)TS7 MS_Class=3
Mass test: TS0(OxOOOOOx)TS7 MS_Class=4
Mass test: TS0(OxOOOOOx)TS7 MS_Class=5
Mass test: TS0(OxOOOOOx)TS7 MS_Class=6
Mass test: TS0(OxOOOOOx)TS7 MS_Class=7
Mass test: TS0(OxOOOOOx)TS7 MS_Class=8
Mass test: TS0(OxOOOOOx)TS7 MS_Class=9
Mass test: TS0(OxOOOOOx)TS7 MS_Class=10
Mass test: TS0(OxOOOOOx)TS7 MS_Class=11
Mass test: TS0(OxOOOOOx)TS7 MS_Class=12
Mass test: TS0(OxOOOOOx)TS7 MS_Class=13
Mass test: TS0(OxOOOOOx)TS7 MS_Class=14
Mass test: TS0(OxOOOOOx)TS7 MS_Class=15
Mass test: TS0(OxOOOOOx)TS7 MS_Class=16
Mass test: TS0(OxOOOOOx)TS7 MS_Class=17
Mass test: TS0(OxOOOOOx)TS7 MS_Class=18
Mass test: TS0(OxOOOOOx)TS7 MS_Class=19
Mass test: TS0(OxOOOOOx)TS7 MS_Class=20
Mass test: TS0(OxOOOOOx)TS7 MS_Class=21
Mass test: TS0(OxOOOOOx)TS7 MS_Class=22
Mass test: TS0(OxOOOOOx)TS7 MS_Class=23
Mass test: TS0(OxOOOOOx)TS7 MS_Class=24
Mass test: TS0(OxOOOOOx)TS7 MS_Class=25
Mass test: TS0(OxOOOOOx)TS7 MS_Class=26
Mass test: TS0(OxOOOOOx)TS7 MS_Class=27
Mass test: TS0(OxOOOOOx)TS7 MS_Class=28
Mass test: TS0(OxOOOOOx)TS7 MS_Class=29
Mass test: TS0(OxOOOOOx)TS7 MS_Class=30
Mass test: TS0(OxOOOOOx)TS7 MS_Class=31
Mass test: TS0(OxOOOOOx)TS7 MS_Class=32
Mass test: TS0(OxOOOOOx)TS7 MS_Class=33
Mass test: TS0(OxOOOOOx)TS7 MS_Class=34
Mass test: TS0(OxOOOOOx)TS7 MS_Class=35
Mass test: TS0(OxOOOOOx)TS7 MS_Class=36
Mass test: TS0(OxOOOOOx)TS7 MS_Class=37
Mass test: TS0(OxOOOOOx)TS7 MS_Class=38
Mass test: TS0(OxOOOOOx)TS7 MS_Class=39
Mass test: TS0(OxOOOOOx)TS7 MS_Class=40
Mass test: TS0(OxOOOOOx)TS7 MS_Class=41
Mass test: TS0(OxOOOOOx)TS7 MS_Class=42
Mass test: TS0(OxOOOOOx)TS7 MS_Class=43
Mass test: TS0(OxOOOOOx)TS7 MS_Class=44
Mass test: TS0(OxOOOOOx)TS7 MS_Class=45
Mass test: TS0(OxOOOOOO)TS7 MS_Class=0
Mass test: TS0(OxOOOOOO)TS7 MS_Class=1
Mass test: TS0(OxOOOOOO)TS7 MS_Class=2
Mass test: TS0(OxOOOOOO)TS7 MS_Class=3
Mass test: TS0(OxOOOOOO)TS7 MS_Class=4
Mass test: TS0(OxOOOOOO)TS7 MS_Class=5
Mass test: TS0(OxOOOOOO)TS7 MS_Class=6
Mass test: TS0(OxOOOOOO)TS7 MS_Class=7
Mass test: TS0(OxOOOOOO)TS7 MS_Class=8
Mass test: TS0(OxOOOOOO)TS7 MS_Class=9
Mass test: TS0(OxOOOOOO)TS7 MS_Class=10
Mass test: TS0(OxOOOOOO)TS7 MS_Class=11
Mass test: TS0(OxOOOOOO)TS7 MS_Class=12
Mass test: TS0(OxOOOOOO)TS7 MS_Class=13
Mass test: TS0(OxOOOOOO)TS7 MS_Class=14
Mass test: TS0(OxOOOOOO)TS7 MS_Class=15
Mass test: TS0(OxOOOOOO)TS7 MS_Class=16
Mass test: TS0(OxOOOOOO)TS7 MS_Class=17
Mass test: TS0(OxOOOOOO)TS7 MS_Class=18
Mass test: TS0(OxOOOOOO)TS7 MS_Class=19
Mass test: TS0(OxOOOOOO)TS7 MS_Class=20
Mass test: TS0(OxOOOOOO)TS7 MS_Class=21
Mass test: TS0(OxOOOOOO)TS7 MS_Class=22
Mass test: TS0(OxOOOOOO)TS7 MS_Class=23
Mass test: TS0(OxOOOOOO)TS7 MS_Class=24
Mass test: TS0(OxOOOOOO)TS7 MS_Class=25
Mass test: TS0(OxOOOOOO)TS7 MS_Class=26
Mass test: TS0(OxOOOOOO)TS7 MS_Class=27
Mass test: TS0(OxOOOOOO)TS7 MS_Class=28
Mass test: TS0(OxOOOOOO)TS7 MS_Class=29
Mass test: TS0(OxOOOOOO)TS7 MS_Class=30
Mass test: TS0(OxOOOOOO)TS7 MS_Class=31
Mass test: TS0(OxOOOOOO)TS7 MS_Class=32
Mass test: TS0(OxOOOOOO)TS7 MS_Class=33
Mass test: TS0(OxOOOOOO)TS7 MS_Class=34
Mass test: TS0(OxOOOOOO)TS7 MS_Class=35
Mass test: TS0(OxOOOOOO)TS7 MS_Class=36
Mass test: TS0(OxOOOOOO)TS7 MS_Class=37
Mass test: TS0(OxOOOOOO)TS7 MS_Class=38
Mass test: TS0(OxOOOOOO)TS7 MS_Class=39
Mass test: TS0(OxOOOOOO)TS7 MS_Class=40
Mass test: TS0(OxOOOOOO)TS7 MS_Class=41
Mass test: TS0(OxOOOOOO)TS7 MS_Class=42
Mass test: TS0(OxOOOOOO)TS7 MS_Class=43
Mass test: TS0(OxOOOOOO)TS7 MS_Class=44
Mass test: TS0(OxOOOOOO)TS7 MS_Class=45
Mass test: TS0(OOxxxxxx)TS7 MS_Class=0
Mass test: TS0(OOxxxxxx)TS7 MS_Class=1
Mass test: TS0(OOxxxxxx)TS7 MS_Class=2
Mass test: TS0(OOxxxxxx)TS7 MS_Class=3
Mass test: TS0(OOxxxxxx)TS7 MS_Class=4
Mass test: TS0(OOxxxxxx)TS7 MS_Class=5
Mass test: TS0(OOxxxxxx)TS7 MS_Class=6
Mass test: TS0(OOxxxxxx)TS7 MS_Class=7
Mass test: TS0(OOxxxxxx)TS7 MS_Class=8
Mass test: TS0(OOxxxxxx)TS7 MS_Class=9
Mass test: TS0(OOxxxxxx)TS7 MS_Class=10
Mass test: TS0(OOxxxxxx)TS7 MS_Class=11
Mass test: TS0(OOxxxxxx)TS7 MS_Class=12
Mass test: TS0(OOxxxxxx)TS7 MS_Class=13
Mass test: TS0(OOxxxxxx)TS7 MS_Class=14
Mass test: TS0(OOxxxxxx)TS7 MS_Class=15
Mass test: TS0(OOxxxxxx)TS7 MS_Class=16
Mass test: TS0(OOxxxxxx)TS7 MS_Class=17
Mass test: TS0(OOxxxxxx)TS7 MS_Class=18
Mass test: TS0(OOxxxxxx)TS7 MS_Class=19
Mass test: TS0(OOxxxxxx)TS7 MS_Class=20
Mass test: TS0(OOxxxxxx)TS7 MS_Class=21
Mass test: TS0(OOxxxxxx)TS7 MS_Class=22
Mass test: TS0(OOxxxxxx)TS7 MS_Class=23
Mass test: TS0(OOxxxxxx)TS7 MS_Class=24
Mass test: TS0(OOxxxxxx)TS7 MS_Class=25
Mass test: TS0(OOxxxxxx)TS7 MS_Class=26
Mass test: TS0(OOxxxxxx)TS7 MS_Class=27
Mass test: TS0(OOxxxxxx)TS7 MS_Class=28
Mass test: TS0(OOxxxxxx)TS7 MS_Class=29
Mass test: TS0(OOxxxxxx)TS7 MS_Class=30
Mass test: TS0(OOxxxxxx)TS7 MS_Class=31
Mass test: TS0(OOxxxxxx)TS7 MS_Class=32
Mass test: TS0(OOxxxxxx)TS7 MS_Class=33
Mass test: TS0(OOxxxxxx)TS7 MS_Class=34
Mass test: TS0(OOxxxxxx)TS7 MS_Class=35
Mass test: TS0(OOxxxxxx)TS7 MS_Class=36
Mass test: TS0(OOxxxxxx)TS7 MS_Class=37
Mass test: TS0(OOxxxxxx)TS7 MS_Class=38
Mass test: TS0(OOxxxxxx)TS7 MS_Class=39
Mass test: TS0(OOxxxxxx)TS7 MS_Class=40
Mass test: TS0(OOxxxxxx)TS7 MS_Class=41
Mass test: TS0(OOxxxxxx)TS7 MS_Class=42
Mass test: TS0(OOxxxxxx)TS7 MS_Class=43
Mass test: TS0(OOxxxxxx)TS7 MS_Class=44
Mass test: TS0(OOxxxxxx)TS7 MS_Class=45
Mass test: TS0(OOxxxxxO)TS7 MS_Class=0
Mass test: TS0(OOxxxxxO)TS7 MS_Class=1
Mass test: TS0(OOxxxxxO)TS7 MS_Class=2
Mass test: TS0(OOxxxxxO)TS7 MS_Class=3
Mass test: TS0(OOxxxxxO)TS7 MS_Class=4
Mass test: TS0(OOxxxxxO)TS7 MS_Class=5
Mass test: TS0(OOxxxxxO)TS7 MS_Class=6
Mass test: TS0(OOxxxxxO)TS7 MS_Class=7
Mass test: TS0(OOxxxxxO)TS7 MS_Class=8
Mass test: TS0(OOxxxxxO)TS7 MS_Class=9
Mass test: TS0(OOxxxxxO)TS7 MS_Class=10
Mass test: TS0(OOxxxxxO)TS7 MS_Class=11
Mass test: TS0(OOxxxxxO)TS7 MS_Class=12
Mass test: TS0(OOxxxxxO)TS7 MS_Class=13
Mass test: TS0(OOxxxxxO)TS7 MS_Class=14
Mass test: TS0(OOxxxxxO)TS7 MS_Class=15
Mass test: TS0(OOxxxxxO)TS7 MS_Class=16
Mass test: TS0(OOxxxxxO)TS7 MS_Class=17
Mass test: TS0(OOxxxxxO)TS7 MS_Class=18
Mass test: TS0(OOxxxxxO)TS7 MS_Class=19
Mass test: TS0(OOxxxxxO)TS7 MS_Class=20
Mass test: TS0(OOxxxxxO)TS7 MS_Class=21
Mass test: TS0(OOxxxxxO)TS7 MS_Class=22
Mass test: TS0(OOxxxxxO)TS7 MS_Class=23
Mass test: TS0(OOxxxxxO)TS7 MS_Class=24
Mass test: TS0(OOxxxxxO)TS7 MS_Class=25
Mass test: TS0(OOxxxxxO)TS7 MS_Class=26
Mass test: TS0(OOxxxxxO)TS7 MS_Class=27
Mass test: TS0(OOxxxxxO)TS7 MS_Class=28
Mass test: TS0(OOxxxxxO)TS7 MS_Class=29
Mass test: TS0(OOxxxxxO)TS7 MS_Class=30
Mass test: TS0(OOxxxxxO)TS7 MS_Class=31
Mass test: TS0(OOxxxxxO)TS7 MS_Class=32
Mass test: TS0(OOxxxxxO)TS7 MS_Class=33
Mass test: TS0(OOxxxxxO)TS7 MS_Class=34
Mass test: TS0(OOxxxxxO)TS7 MS_Class=35
Mass test: TS0(OOxxxxxO)TS7 MS_Class=36
Mass test: TS0(OOxxxxxO)TS7 MS_Class=37
Mass test: TS0(OOxxxxxO)TS7 MS_Class=38
Mass test: TS0(OOxxxxxO)TS7 MS_Class=39
Mass test: TS0(OOxxxxxO)TS7 MS_Class=40
Mass test: TS0(OOxxxxxO)TS7 MS_Class=41
Mass test: TS0(OOxxxxxO)TS7 MS_Class=42
Mass test: TS0(OOxxxxxO)TS7 MS_Class=43
Mass test: TS0(OOxxxxxO)TS7 MS_Class=44
Mass test: TS0(OOxxxxxO)TS7 MS_Class=45
Mass test: TS0(OOxxxxOx)TS7 MS_Class=0
Mass test: TS0(OOxxxxOx)TS7 MS_Class=1
Mass test: TS0(OOxxxxOx)TS7 MS_Class=2
Mass test: TS0(OOxxxxOx)TS7 MS_Class=3
Mass test: TS0(OOxxxxOx)TS7 MS_Class=4
Mass test: TS0(OOxxxxOx)TS7 MS_Class=5
Mass test: TS0(OOxxxxOx)TS7 MS_Class=6
Mass test: TS0(OOxxxxOx)TS7 MS_Class=7
Mass test: TS0(OOxxxxOx)TS7 MS_Class=8
Mass test: TS0(OOxxxxOx)TS7 MS_Class=9
Mass test: TS0(OOxxxxOx)TS7 MS_Class=10
Mass test: TS0(OOxxxxOx)TS7 MS_Class=11
Mass test: TS0(OOxxxxOx)TS7 MS_Class=12
Mass test: TS0(OOxxxxOx)TS7 MS_Class=13
Mass test: TS0(OOxxxxOx)TS7 MS_Class=14
Mass test: TS0(OOxxxxOx)TS7 MS_Class=15
Mass test: TS0(OOxxxxOx)TS7 MS_Class=16
Mass test: TS0(OOxxxxOx)TS7 MS_Class=17
Mass test: TS0(OOxxxxOx)TS7 MS_Class=18
Mass test: TS0(OOxxxxOx)TS7 MS_Class=19
Mass test: TS0(OOxxxxOx)TS7 MS_Class=20
Mass test: TS0(OOxxxxOx)TS7 MS_Class=21
Mass test: TS0(OOxxxxOx)TS7 MS_Class=22
Mass test: TS0(OOxxxxOx)TS7 MS_Class=23
Mass test: TS0(OOxxxxOx)TS7 MS_Class=24
Mass test: TS0(OOxxxxOx)TS7 MS_Class=25
Mass test: TS0(OOxxxxOx)TS7 MS_Class=26
Mass test: TS0(OOxxxxOx)TS7 MS_Class=27
Mass test: TS0(OOxxxxOx)TS7 MS_Class=28
Mass test: TS0(OOxxxxOx)TS7 MS_Class=29
Mass test: TS0(OOxxxxOx)TS7 MS_Class=30
Mass test: TS0(OOxxxxOx)TS7 MS_Class=31
Mass test: TS0(OOxxxxOx)TS7 MS_Class=32
Mass test: TS0(OOxxxxOx)TS7 MS_Class=33
Mass test: TS0(OOxxxxOx)TS7 MS_Class=34
Mass test: TS0(OOxxxxOx)TS7 MS_Class=35
Mass test: TS0(OOxxxxOx)TS7 MS_Class=36
Mass test: TS0(OOxxxxOx)TS7 MS_Class=37
Mass test: TS0(OOxxxxOx)TS7 MS_Class=38
Mass test: TS0(OOxxxxOx)TS7 MS_Class=39
Mass test: TS0(OOxxxxOx)TS7 MS_Class=40
Mass test: TS0(OOxxxxOx)TS7 MS_Class=41
Mass test: TS0(OOxxxxOx)TS7 MS_Class=42
Mass test: TS0(OOxxxxOx)TS7 MS_Class=43
Mass test: TS0(OOxxxxOx)TS7 MS_Class=44
Mass test: TS0(OOxxxxOx)TS7 MS_Class=45
Mass test: TS0(OOxxxxOO)TS7 MS_Class=0
Mass test: TS0(OOxxxxOO)TS7 MS_Class=1
Mass test: TS0(OOxxxxOO)TS7 MS_Class=2
Mass test: TS0(OOxxxxOO)TS7 MS_Class=3
Mass test: TS0(OOxxxxOO)TS7 MS_Class=4
Mass test: TS0(OOxxxxOO)TS7 MS_Class=5
Mass test: TS0(OOxxxxOO)TS7 MS_Class=6
Mass test: TS0(OOxxxxOO)TS7 MS_Class=7
Mass test: TS0(OOxxxxOO)TS7 MS_Class=8
Mass test: TS0(OOxxxxOO)TS7 MS_Class=9
Mass test: TS0(OOxxxxOO)TS7 MS_Class=10
Mass test: TS0(OOxxxxOO)TS7 MS_Class=11
Mass test: TS0(OOxxxxOO)TS7 MS_Class=12
Mass test: TS0(OOxxxxOO)TS7 MS_Class=13
Mass test: TS0(OOxxxxOO)TS7 MS_Class=14
Mass test: TS0(OOxxxxOO)TS7 MS_Class=15
Mass test: TS0(OOxxxxOO)TS7 MS_Class=16
Mass test: TS0(OOxxxxOO)TS7 MS_Class=17
Mass test: TS0(OOxxxxOO)TS7 MS_Class=18
Mass test: TS0(OOxxxxOO)TS7 MS_Class=19
Mass test: TS0(OOxxxxOO)TS7 MS_Class=20
Mass test: TS0(OOxxxxOO)TS7 MS_Class=21
Mass test: TS0(OOxxxxOO)TS7 MS_Class=22
Mass test: TS0(OOxxxxOO)TS7 MS_Class=23
Mass test: TS0(OOxxxxOO)TS7 MS_Class=24
Mass test: TS0(OOxxxxOO)TS7 MS_Class=25
Mass test: TS0(OOxxxxOO)TS7 MS_Class=26
Mass test: TS0(OOxxxxOO)TS7 MS_Class=27
Mass test: TS0(OOxxxxOO)TS7 MS_Class=28
Mass test: TS0(OOxxxxOO)TS7 MS_Class=29
Mass test: TS0(OOxxxxOO)TS7 MS_Class=30
Mass test: TS0(OOxxxxOO)TS7 MS_Class=31
Mass test: TS0(OOxxxxOO)TS7 MS_Class=32
Mass test: TS0(OOxxxxOO)TS7 MS_Class=33
Mass test: TS0(OOxxxxOO)TS7 MS_Class=34
Mass test: TS0(OOxxxxOO)TS7 MS_Class=35
Mass test: TS0(OOxxxxOO)TS7 MS_Class=36
Mass test: TS0(OOxxxxOO)TS7 MS_Class=37
Mass test: TS0(OOxxxxOO)TS7 MS_Class=38
Mass test: TS0(OOxxxxOO)TS7 MS_Class=39
Mass test: TS0(OOxxxxOO)TS7 MS_Class=40
Mass test: TS0(OOxxxxOO)TS7 MS_Class=41
Mass test: TS0(OOxxxxOO)TS7 MS_Class=42
Mass test: TS0(OOxxxxOO)TS7 MS_Class=43
Mass test: TS0(OOxxxxOO)TS7 MS_Class=44
Mass test: TS0(OOxxxxOO)TS7 MS_Class=45
Mass test: TS0(OOxxxOxx)TS7 MS_Class=0
Mass test: TS0(OOxxxOxx)TS7 MS_Class=1
Mass test: TS0(OOxxxOxx)TS7 MS_Class=2
Mass test: TS0(OOxxxOxx)TS7 MS_Class=3
Mass test: TS0(OOxxxOxx)TS7 MS_Class=4
Mass test: TS0(OOxxxOxx)TS7 MS_Class=5
Mass test: TS0(OOxxxOxx)TS7 MS_Class=6
Mass test: TS0(OOxxxOxx)TS7 MS_Class=7
Mass test: TS0(OOxxxOxx)TS7 MS_Class=8
Mass test: TS0(OOxxxOxx)TS7 MS_Class=9
Mass test: TS0(OOxxxOxx)TS7 MS_Class=10
Mass test: TS0(OOxxxOxx)TS7 MS_Class=11
Mass test: TS0(OOxxxOxx)TS7 MS_Class=12
Mass test: TS0(OOxxxOxx)TS7 MS_Class=13
Mass test: TS0(OOxxxOxx)TS7 MS_Class=14
Mass test: TS0(OOxxxOxx)TS7 MS_Class=15
Mass test: TS0(OOxxxOxx)TS7 MS_Class=16
Mass test: TS0(OOxxxOxx)TS7 MS_Class=17
Mass test: TS0(OOxxxOxx)TS7 MS_Class=18
Mass test: TS0(OOxxxOxx)TS7 MS_Class=19
Mass test: TS0(OOxxxOxx)TS7 MS_Class=20
Mass test: TS0(OOxxxOxx)TS7 MS_Class=21
Mass test: TS0(OOxxxOxx)TS7 MS_Class=22
Mass test: TS0(OOxxxOxx)TS7 MS_Class=23
Mass test: TS0(OOxxxOxx)TS7 MS_Class=24
Mass test: TS0(OOxxxOxx)TS7 MS_Class=25
Mass test: TS0(OOxxxOxx)TS7 MS_Class=26
Mass test: TS0(OOxxxOxx)TS7 MS_Class=27
Mass test: TS0(OOxxxOxx)TS7 MS_Class=28
Mass test: TS0(OOxxxOxx)TS7 MS_Class=29
Mass test: TS0(OOxxxOxx)TS7 MS_Class=30
Mass test: TS0(OOxxxOxx)TS7 MS_Class=31
Mass test: TS0(OOxxxOxx)TS7 MS_Class=32
Mass test: TS0(OOxxxOxx)TS7 MS_Class=33
Mass test: TS0(OOxxxOxx)TS7 MS_Class=34
Mass test: TS0(OOxxxOxx)TS7 MS_Class=35
Mass test: TS0(OOxxxOxx)TS7 MS_Class=36
Mass test: TS0(OOxxxOxx)TS7 MS_Class=37
Mass test: TS0(OOxxxOxx)TS7 MS_Class=38
Mass test: TS0(OOxxxOxx)TS7 MS_Class=39
Mass test: TS0(OOxxxOxx)TS7 MS_Class=40
Mass test: TS0(OOxxxOxx)TS7 MS_Class=41
Mass test: TS0(OOxxxOxx)TS7 MS_Class=42
Mass test: TS0(OOxxxOxx)TS7 MS_Class=43
Mass test: TS0(OOxxxOxx)TS7 MS_Class=44
Mass test: TS0(OOxxxOxx)TS7 MS_Class=45
Mass test: TS0(OOxxxOxO)TS7 MS_Class=0
Mass test: TS0(OOxxxOxO)TS7 MS_Class=1
Mass test: TS0(OOxxxOxO)TS7 MS_Class=2
Mass test: TS0(OOxxxOxO)TS7 MS_Class=3
Mass test: TS0(OOxxxOxO)TS7 MS_Class=4
Mass test: TS0(OOxxxOxO)TS7 MS_Class=5
Mass test: TS0(OOxxxOxO)TS7 MS_Class=6
Mass test: TS0(OOxxxOxO)TS7 MS_Class=7
Mass test: TS0(OOxxxOxO)TS7 MS_Class=8
Mass test: TS0(OOxxxOxO)TS7 MS_Class=9
Mass test: TS0(OOxxxOxO)TS7 MS_Class=10
Mass test: TS0(OOxxxOxO)TS7 MS_Class=11
Mass test: TS0(OOxxxOxO)TS7 MS_Class=12
Mass test: TS0(OOxxxOxO)TS7 MS_Class=13
Mass test: TS0(OOxxxOxO)TS7 MS_Class=14
Mass test: TS0(OOxxxOxO)TS7 MS_Class=15
Mass test: TS0(OOxxxOxO)TS7 MS_Class=16
Mass test: TS0(OOxxxOxO)TS7 MS_Class=17
Mass test: TS0(OOxxxOxO)TS7 MS_Class=18
Mass test: TS0(OOxxxOxO)TS7 MS_Class=19
Mass test: TS0(OOxxxOxO)TS7 MS_Class=20
Mass test: TS0(OOxxxOxO)TS7 MS_Class=21
Mass test: TS0(OOxxxOxO)TS7 MS_Class=22
Mass test: TS0(OOxxxOxO)TS7 MS_Class=23
Mass test: TS0(OOxxxOxO)TS7 MS_Class=24
Mass test: TS0(OOxxxOxO)TS7 MS_Class=25
Mass test: TS0(OOxxxOxO)TS7 MS_Class=26
Mass test: TS0(OOxxxOxO)TS7 MS_Class=27
Mass test: TS0(OOxxxOxO)TS7 MS_Class=28
Mass test: TS0(OOxxxOxO)TS7 MS_Class=29
Mass test: TS0(OOxxxOxO)TS7 MS_Class=30
Mass test: TS0(OOxxxOxO)TS7 MS_Class=31
Mass test: TS0(OOxxxOxO)TS7 MS_Class=32
Mass test: TS0(OOxxxOxO)TS7 MS_Class=33
Mass test: TS0(OOxxxOxO)TS7 MS_Class=34
Mass test: TS0(OOxxxOxO)TS7 MS_Class=35
Mass test: TS0(OOxxxOxO)TS7 MS_Class=36
Mass test: TS0(OOxxxOxO)TS7 MS_Class=37
Mass test: TS0(OOxxxOxO)TS7 MS_Class=38
Mass test: TS0(OOxxxOxO)TS7 MS_Class=39
Mass test: TS0(OOxxxOxO)TS7 MS_Class=40
Mass test: TS0(OOxxxOxO)TS7 MS_Class=41
Mass test: TS0(OOxxxOxO)TS7 MS_Class=42
Mass test: TS0(OOxxxOxO)TS7 MS_Class=43
Mass test: TS0(OOxxxOxO)TS7 MS_Class=44
Mass test: TS0(OOxxxOxO)TS7 MS_Class=45
Mass test: TS0(OOxxxOOx)TS7 MS_Class=0
Mass test: TS0(OOxxxOOx)TS7 MS_Class=1
Mass test: TS0(OOxxxOOx)TS7 MS_Class=2
Mass test: TS0(OOxxxOOx)TS7 MS_Class=3
Mass test: TS0(OOxxxOOx)TS7 MS_Class=4
Mass test: TS0(OOxxxOOx)TS7 MS_Class=5
Mass test: TS0(OOxxxOOx)TS7 MS_Class=6
Mass test: TS0(OOxxxOOx)TS7 MS_Class=7
Mass test: TS0(OOxxxOOx)TS7 MS_Class=8
Mass test: TS0(OOxxxOOx)TS7 MS_Class=9
Mass test: TS0(OOxxxOOx)TS7 MS_Class=10
Mass test: TS0(OOxxxOOx)TS7 MS_Class=11
Mass test: TS0(OOxxxOOx)TS7 MS_Class=12
Mass test: TS0(OOxxxOOx)TS7 MS_Class=13
Mass test: TS0(OOxxxOOx)TS7 MS_Class=14
Mass test: TS0(OOxxxOOx)TS7 MS_Class=15
Mass test: TS0(OOxxxOOx)TS7 MS_Class=16
Mass test: TS0(OOxxxOOx)TS7 MS_Class=17
Mass test: TS0(OOxxxOOx)TS7 MS_Class=18
Mass test: TS0(OOxxxOOx)TS7 MS_Class=19
Mass test: TS0(OOxxxOOx)TS7 MS_Class=20
Mass test: TS0(OOxxxOOx)TS7 MS_Class=21
Mass test: TS0(OOxxxOOx)TS7 MS_Class=22
Mass test: TS0(OOxxxOOx)TS7 MS_Class=23
Mass test: TS0(OOxxxOOx)TS7 MS_Class=24
Mass test: TS0(OOxxxOOx)TS7 MS_Class=25
Mass test: TS0(OOxxxOOx)TS7 MS_Class=26
Mass test: TS0(OOxxxOOx)TS7 MS_Class=27
Mass test: TS0(OOxxxOOx)TS7 MS_Class=28
Mass test: TS0(OOxxxOOx)TS7 MS_Class=29
Mass test: TS0(OOxxxOOx)TS7 MS_Class=30
Mass test: TS0(OOxxxOOx)TS7 MS_Class=31
Mass test: TS0(OOxxxOOx)TS7 MS_Class=32
Mass test: TS0(OOxxxOOx)TS7 MS_Class=33
Mass test: TS0(OOxxxOOx)TS7 MS_Class=34
Mass test: TS0(OOxxxOOx)TS7 MS_Class=35
Mass test: TS0(OOxxxOOx)TS7 MS_Class=36
Mass test: TS0(OOxxxOOx)TS7 MS_Class=37
Mass test: TS0(OOxxxOOx)TS7 MS_Class=38
Mass test: TS0(OOxxxOOx)TS7 MS_Class=39
Mass test: TS0(OOxxxOOx)TS7 MS_Class=40
Mass test: TS0(OOxxxOOx)TS7 MS_Class=41
Mass test: TS0(OOxxxOOx)TS7 MS_Class=42
Mass test: TS0(OOxxxOOx)TS7 MS_Class=43
Mass test: TS0(OOxxxOOx)TS7 MS_Class=44
Mass test: TS0(OOxxxOOx)TS7 MS_Class=45
Mass test: TS0(OOxxxOOO)TS7 MS_Class=0
Mass test: TS0(OOxxxOOO)TS7 MS_Class=1
Mass test: TS0(OOxxxOOO)TS7 MS_Class=2
Mass test: TS0(OOxxxOOO)TS7 MS_Class=3
Mass test: TS0(OOxxxOOO)TS7 MS_Class=4
Mass test: TS0(OOxxxOOO)TS7 MS_Class=5
Mass test: TS0(OOxxxOOO)TS7 MS_Class=6
Mass test: TS0(OOxxxOOO)TS7 MS_Class=7
Mass test: TS0(OOxxxOOO)TS7 MS_Class=8
Mass test: TS0(OOxxxOOO)TS7 MS_Class=9
Mass test: TS0(OOxxxOOO)TS7 MS_Class=10
Mass test: TS0(OOxxxOOO)TS7 MS_Class=11
Mass test: TS0(OOxxxOOO)TS7 MS_Class=12
Mass test: TS0(OOxxxOOO)TS7 MS_Class=13
Mass test: TS0(OOxxxOOO)TS7 MS_Class=14
Mass test: TS0(OOxxxOOO)TS7 MS_Class=15
Mass test: TS0(OOxxxOOO)TS7 MS_Class=16
Mass test: TS0(OOxxxOOO)TS7 MS_Class=17
Mass test: TS0(OOxxxOOO)TS7 MS_Class=18
Mass test: TS0(OOxxxOOO)TS7 MS_Class=19
Mass test: TS0(OOxxxOOO)TS7 MS_Class=20
Mass test: TS0(OOxxxOOO)TS7 MS_Class=21
Mass test: TS0(OOxxxOOO)TS7 MS_Class=22
Mass test: TS0(OOxxxOOO)TS7 MS_Class=23
Mass test: TS0(OOxxxOOO)TS7 MS_Class=24
Mass test: TS0(OOxxxOOO)TS7 MS_Class=25
Mass test: TS0(OOxxxOOO)TS7 MS_Class=26
Mass test: TS0(OOxxxOOO)TS7 MS_Class=27
Mass test: TS0(OOxxxOOO)TS7 MS_Class=28
Mass test: TS0(OOxxxOOO)TS7 MS_Class=29
Mass test: TS0(OOxxxOOO)TS7 MS_Class=30
Mass test: TS0(OOxxxOOO)TS7 MS_Class=31
Mass test: TS0(OOxxxOOO)TS7 MS_Class=32
Mass test: TS0(OOxxxOOO)TS7 MS_Class=33
Mass test: TS0(OOxxxOOO)TS7 MS_Class=34
Mass test: TS0(OOxxxOOO)TS7 MS_Class=35
Mass test: TS0(OOxxxOOO)TS7 MS_Class=36
Mass test: TS0(OOxxxOOO)TS7 MS_Class=37
Mass test: TS0(OOxxxOOO)TS7 MS_Class=38
Mass test: TS0(OOxxxOOO)TS7 MS_Class=39
Mass test: TS0(OOxxxOOO)TS7 MS_Class=40
Mass test: TS0(OOxxxOOO)TS7 MS_Class=41
Mass test: TS0(OOxxxOOO)TS7 MS_Class=42
Mass test: TS0(OOxxxOOO)TS7 MS_Class=43
Mass test: TS0(OOxxxOOO)TS7 MS_Class=44
Mass test: TS0(OOxxxOOO)TS7 MS_Class=45
Mass test: TS0(OOxxOxxx)TS7 MS_Class=0
Mass test: TS0(OOxxOxxx)TS7 MS_Class=1
Mass test: TS0(OOxxOxxx)TS7 MS_Class=2
Mass test: TS0(OOxxOxxx)TS7 MS_Class=3
Mass test: TS0(OOxxOxxx)TS7 MS_Class=4
Mass test: TS0(OOxxOxxx)TS7 MS_Class=5
Mass test: TS0(OOxxOxxx)TS7 MS_Class=6
Mass test: TS0(OOxxOxxx)TS7 MS_Class=7
Mass test: TS0(OOxxOxxx)TS7 MS_Class=8
Mass test: TS0(OOxxOxxx)TS7 MS_Class=9
Mass test: TS0(OOxxOxxx)TS7 MS_Class=10
Mass test: TS0(OOxxOxxx)TS7 MS_Class=11
Mass test: TS0(OOxxOxxx)TS7 MS_Class=12
Mass test: TS0(OOxxOxxx)TS7 MS_Class=13
Mass test: TS0(OOxxOxxx)TS7 MS_Class=14
Mass test: TS0(OOxxOxxx)TS7 MS_Class=15
Mass test: TS0(OOxxOxxx)TS7 MS_Class=16
Mass test: TS0(OOxxOxxx)TS7 MS_Class=17
Mass test: TS0(OOxxOxxx)TS7 MS_Class=18
Mass test: TS0(OOxxOxxx)TS7 MS_Class=19
Mass test: TS0(OOxxOxxx)TS7 MS_Class=20
Mass test: TS0(OOxxOxxx)TS7 MS_Class=21
Mass test: TS0(OOxxOxxx)TS7 MS_Class=22
Mass test: TS0(OOxxOxxx)TS7 MS_Class=23
Mass test: TS0(OOxxOxxx)TS7 MS_Class=24
Mass test: TS0(OOxxOxxx)TS7 MS_Class=25
Mass test: TS0(OOxxOxxx)TS7 MS_Class=26
Mass test: TS0(OOxxOxxx)TS7 MS_Class=27
Mass test: TS0(OOxxOxxx)TS7 MS_Class=28
Mass test: TS0(OOxxOxxx)TS7 MS_Class=29
Mass test: TS0(OOxxOxxx)TS7 MS_Class=30
Mass test: TS0(OOxxOxxx)TS7 MS_Class=31
Mass test: TS0(OOxxOxxx)TS7 MS_Class=32
Mass test: TS0(OOxxOxxx)TS7 MS_Class=33
Mass test: TS0(OOxxOxxx)TS7 MS_Class=34
Mass test: TS0(OOxxOxxx)TS7 MS_Class=35
Mass test: TS0(OOxxOxxx)TS7 MS_Class=36
Mass test: TS0(OOxxOxxx)TS7 MS_Class=37
Mass test: TS0(OOxxOxxx)TS7 MS_Class=38
Mass test: TS0(OOxxOxxx)TS7 MS_Class=39
Mass test: TS0(OOxxOxxx)TS7 MS_Class=40
Mass test: TS0(OOxxOxxx)TS7 MS_Class=41
Mass test: TS0(OOxxOxxx)TS7 MS_Class=42
Mass test: TS0(OOxxOxxx)TS7 MS_Class=43
Mass test: TS0(OOxxOxxx)TS7 MS_Class=44
Mass test: TS0(OOxxOxxx)TS7 MS_Class=45
Mass test: TS0(OOxxOxxO)TS7 MS_Class=0
Mass test: TS0(OOxxOxxO)TS7 MS_Class=1
Mass test: TS0(OOxxOxxO)TS7 MS_Class=2
Mass test: TS0(OOxxOxxO)TS7 MS_Class=3
Mass test: TS0(OOxxOxxO)TS7 MS_Class=4
Mass test: TS0(OOxxOxxO)TS7 MS_Class=5
Mass test: TS0(OOxxOxxO)TS7 MS_Class=6
Mass test: TS0(OOxxOxxO)TS7 MS_Class=7
Mass test: TS0(OOxxOxxO)TS7 MS_Class=8
Mass test: TS0(OOxxOxxO)TS7 MS_Class=9
Mass test: TS0(OOxxOxxO)TS7 MS_Class=10
Mass test: TS0(OOxxOxxO)TS7 MS_Class=11
Mass test: TS0(OOxxOxxO)TS7 MS_Class=12
Mass test: TS0(OOxxOxxO)TS7 MS_Class=13
Mass test: TS0(OOxxOxxO)TS7 MS_Class=14
Mass test: TS0(OOxxOxxO)TS7 MS_Class=15
Mass test: TS0(OOxxOxxO)TS7 MS_Class=16
Mass test: TS0(OOxxOxxO)TS7 MS_Class=17
Mass test: TS0(OOxxOxxO)TS7 MS_Class=18
Mass test: TS0(OOxxOxxO)TS7 MS_Class=19
Mass test: TS0(OOxxOxxO)TS7 MS_Class=20
Mass test: TS0(OOxxOxxO)TS7 MS_Class=21
Mass test: TS0(OOxxOxxO)TS7 MS_Class=22
Mass test: TS0(OOxxOxxO)TS7 MS_Class=23
Mass test: TS0(OOxxOxxO)TS7 MS_Class=24
Mass test: TS0(OOxxOxxO)TS7 MS_Class=25
Mass test: TS0(OOxxOxxO)TS7 MS_Class=26
Mass test: TS0(OOxxOxxO)TS7 MS_Class=27
Mass test: TS0(OOxxOxxO)TS7 MS_Class=28
Mass test: TS0(OOxxOxxO)TS7 MS_Class=29
Mass test: TS0(OOxxOxxO)TS7 MS_Class=30
Mass test: TS0(OOxxOxxO)TS7 MS_Class=31
Mass test: TS0(OOxxOxxO)TS7 MS_Class=32
Mass test: TS0(OOxxOxxO)TS7 MS_Class=33
Mass test: TS0(OOxxOxxO)TS7 MS_Class=34
Mass test: TS0(OOxxOxxO)TS7 MS_Class=35
Mass test: TS0(OOxxOxxO)TS7 MS_Class=36
Mass test: TS0(OOxxOxxO)TS7 MS_Class=37
Mass test: TS0(OOxxOxxO)TS7 MS_Class=38
Mass test: TS0(OOxxOxxO)TS7 MS_Class=39
Mass test: TS0(OOxxOxxO)TS7 MS_Class=40
Mass test: TS0(OOxxOxxO)TS7 MS_Class=41
Mass test: TS0(OOxxOxxO)TS7 MS_Class=42
Mass test: TS0(OOxxOxxO)TS7 MS_Class=43
Mass test: TS0(OOxxOxxO)TS7 MS_Class=44
Mass test: TS0(OOxxOxxO)TS7 MS_Class=45
Mass test: TS0(OOxxOxOx)TS7 MS_Class=0
Mass test: TS0(OOxxOxOx)TS7 MS_Class=1
Mass test: TS0(OOxxOxOx)TS7 MS_Class=2
Mass test: TS0(OOxxOxOx)TS7 MS_Class=3
Mass test: TS0(OOxxOxOx)TS7 MS_Class=4
Mass test: TS0(OOxxOxOx)TS7 MS_Class=5
Mass test: TS0(OOxxOxOx)TS7 MS_Class=6
Mass test: TS0(OOxxOxOx)TS7 MS_Class=7
Mass test: TS0(OOxxOxOx)TS7 MS_Class=8
Mass test: TS0(OOxxOxOx)TS7 MS_Class=9
Mass test: TS0(OOxxOxOx)TS7 MS_Class=10
Mass test: TS0(OOxxOxOx)TS7 MS_Class=11
Mass test: TS0(OOxxOxOx)TS7 MS_Class=12
Mass test: TS0(OOxxOxOx)TS7 MS_Class=13
Mass test: TS0(OOxxOxOx)TS7 MS_Class=14
Mass test: TS0(OOxxOxOx)TS7 MS_Class=15
Mass test: TS0(OOxxOxOx)TS7 MS_Class=16
Mass test: TS0(OOxxOxOx)TS7 MS_Class=17
Mass test: TS0(OOxxOxOx)TS7 MS_Class=18
Mass test: TS0(OOxxOxOx)TS7 MS_Class=19
Mass test: TS0(OOxxOxOx)TS7 MS_Class=20
Mass test: TS0(OOxxOxOx)TS7 MS_Class=21
Mass test: TS0(OOxxOxOx)TS7 MS_Class=22
Mass test: TS0(OOxxOxOx)TS7 MS_Class=23
Mass test: TS0(OOxxOxOx)TS7 MS_Class=24
Mass test: TS0(OOxxOxOx)TS7 MS_Class=25
Mass test: TS0(OOxxOxOx)TS7 MS_Class=26
Mass test: TS0(OOxxOxOx)TS7 MS_Class=27
Mass test: TS0(OOxxOxOx)TS7 MS_Class=28
Mass test: TS0(OOxxOxOx)TS7 MS_Class=29
Mass test: TS0(OOxxOxOx)TS7 MS_Class=30
Mass test: TS0(OOxxOxOx)TS7 MS_Class=31
Mass test: TS0(OOxxOxOx)TS7 MS_Class=32
Mass test: TS0(OOxxOxOx)TS7 MS_Class=33
Mass test: TS0(OOxxOxOx)TS7 MS_Class=34
Mass test: TS0(OOxxOxOx)TS7 MS_Class=35
Mass test: TS0(OOxxOxOx)TS7 MS_Class=36
Mass test: TS0(OOxxOxOx)TS7 MS_Class=37
Mass test: TS0(OOxxOxOx)TS7 MS_Class=38
Mass test: TS0(OOxxOxOx)TS7 MS_Class=39
Mass test: TS0(OOxxOxOx)TS7 MS_Class=40
Mass test: TS0(OOxxOxOx)TS7 MS_Class=41
Mass test: TS0(OOxxOxOx)TS7 MS_Class=42
Mass test: TS0(OOxxOxOx)TS7 MS_Class=43
Mass test: TS0(OOxxOxOx)TS7 MS_Class=44
Mass test: TS0(OOxxOxOx)TS7 MS_Class=45
Mass test: TS0(OOxxOxOO)TS7 MS_Class=0
Mass test: TS0(OOxxOxOO)TS7 MS_Class=1
Mass test: TS0(OOxxOxOO)TS7 MS_Class=2
Mass test: TS0(OOxxOxOO)TS7 MS_Class=3
Mass test: TS0(OOxxOxOO)TS7 MS_Class=4
Mass test: TS0(OOxxOxOO)TS7 MS_Class=5
Mass test: TS0(OOxxOxOO)TS7 MS_Class=6
Mass test: TS0(OOxxOxOO)TS7 MS_Class=7
Mass test: TS0(OOxxOxOO)TS7 MS_Class=8
Mass test: TS0(OOxxOxOO)TS7 MS_Class=9
Mass test: TS0(OOxxOxOO)TS7 MS_Class=10
Mass test: TS0(OOxxOxOO)TS7 MS_Class=11
Mass test: TS0(OOxxOxOO)TS7 MS_Class=12
Mass test: TS0(OOxxOxOO)TS7 MS_Class=13
Mass test: TS0(OOxxOxOO)TS7 MS_Class=14
Mass test: TS0(OOxxOxOO)TS7 MS_Class=15
Mass test: TS0(OOxxOxOO)TS7 MS_Class=16
Mass test: TS0(OOxxOxOO)TS7 MS_Class=17
Mass test: TS0(OOxxOxOO)TS7 MS_Class=18
Mass test: TS0(OOxxOxOO)TS7 MS_Class=19
Mass test: TS0(OOxxOxOO)TS7 MS_Class=20
Mass test: TS0(OOxxOxOO)TS7 MS_Class=21
Mass test: TS0(OOxxOxOO)TS7 MS_Class=22
Mass test: TS0(OOxxOxOO)TS7 MS_Class=23
Mass test: TS0(OOxxOxOO)TS7 MS_Class=24
Mass test: TS0(OOxxOxOO)TS7 MS_Class=25
Mass test: TS0(OOxxOxOO)TS7 MS_Class=26
Mass test: TS0(OOxxOxOO)TS7 MS_Class=27
Mass test: TS0(OOxxOxOO)TS7 MS_Class=28
Mass test: TS0(OOxxOxOO)TS7 MS_Class=29
Mass test: TS0(OOxxOxOO)TS7 MS_Class=30
Mass test: TS0(OOxxOxOO)TS7 MS_Class=31
Mass test: TS0(OOxxOxOO)TS7 MS_Class=32
Mass test: TS0(OOxxOxOO)TS7 MS_Class=33
Mass test: TS0(OOxxOxOO)TS7 MS_Class=34
Mass test: TS0(OOxxOxOO)TS7 MS_Class=35
Mass test: TS0(OOxxOxOO)TS7 MS_Class=36
Mass test: TS0(OOxxOxOO)TS7 MS_Class=37
Mass test: TS0(OOxxOxOO)TS7 MS_Class=38
Mass test: TS0(OOxxOxOO)TS7 MS_Class=39
Mass test: TS0(OOxxOxOO)TS7 MS_Class=40
Mass test: TS0(OOxxOxOO)TS7 MS_Class=41
Mass test: TS0(OOxxOxOO)TS7 MS_Class=42
Mass test: TS0(OOxxOxOO)TS7 MS_Class=43
Mass test: TS0(OOxxOxOO)TS7 MS_Class=44
Mass test: TS0(OOxxOxOO)TS7 MS_Class=45
Mass test: TS0(OOxxOOxx)TS7 MS_Class=0
Mass test: TS0(OOxxOOxx)TS7 MS_Class=1
Mass test: TS0(OOxxOOxx)TS7 MS_Class=2
Mass test: TS0(OOxxOOxx)TS7 MS_Class=3
Mass test: TS0(OOxxOOxx)TS7 MS_Class=4
Mass test: TS0(OOxxOOxx)TS7 MS_Class=5
Mass test: TS0(OOxxOOxx)TS7 MS_Class=6
Mass test: TS0(OOxxOOxx)TS7 MS_Class=7
Mass test: TS0(OOxxOOxx)TS7 MS_Class=8
Mass test: TS0(OOxxOOxx)TS7 MS_Class=9
Mass test: TS0(OOxxOOxx)TS7 MS_Class=10
Mass test: TS0(OOxxOOxx)TS7 MS_Class=11
Mass test: TS0(OOxxOOxx)TS7 MS_Class=12
Mass test: TS0(OOxxOOxx)TS7 MS_Class=13
Mass test: TS0(OOxxOOxx)TS7 MS_Class=14
Mass test: TS0(OOxxOOxx)TS7 MS_Class=15
Mass test: TS0(OOxxOOxx)TS7 MS_Class=16
Mass test: TS0(OOxxOOxx)TS7 MS_Class=17
Mass test: TS0(OOxxOOxx)TS7 MS_Class=18
Mass test: TS0(OOxxOOxx)TS7 MS_Class=19
Mass test: TS0(OOxxOOxx)TS7 MS_Class=20
Mass test: TS0(OOxxOOxx)TS7 MS_Class=21
Mass test: TS0(OOxxOOxx)TS7 MS_Class=22
Mass test: TS0(OOxxOOxx)TS7 MS_Class=23
Mass test: TS0(OOxxOOxx)TS7 MS_Class=24
Mass test: TS0(OOxxOOxx)TS7 MS_Class=25
Mass test: TS0(OOxxOOxx)TS7 MS_Class=26
Mass test: TS0(OOxxOOxx)TS7 MS_Class=27
Mass test: TS0(OOxxOOxx)TS7 MS_Class=28
Mass test: TS0(OOxxOOxx)TS7 MS_Class=29
Mass test: TS0(OOxxOOxx)TS7 MS_Class=30
Mass test: TS0(OOxxOOxx)TS7 MS_Class=31
Mass test: TS0(OOxxOOxx)TS7 MS_Class=32
Mass test: TS0(OOxxOOxx)TS7 MS_Class=33
Mass test: TS0(OOxxOOxx)TS7 MS_Class=34
Mass test: TS0(OOxxOOxx)TS7 MS_Class=35
Mass test: TS0(OOxxOOxx)TS7 MS_Class=36
Mass test: TS0(OOxxOOxx)TS7 MS_Class=37
Mass test: TS0(OOxxOOxx)TS7 MS_Class=38
Mass test: TS0(OOxxOOxx)TS7 MS_Class=39
Mass test: TS0(OOxxOOxx)TS7 MS_Class=40
Mass test: TS0(OOxxOOxx)TS7 MS_Class=41
Mass test: TS0(OOxxOOxx)TS7 MS_Class=42
Mass test: TS0(OOxxOOxx)TS7 MS_Class=43
Mass test: TS0(OOxxOOxx)TS7 MS_Class=44
Mass test: TS0(OOxxOOxx)TS7 MS_Class=45
Mass test: TS0(OOxxOOxO)TS7 MS_Class=0
Mass test: TS0(OOxxOOxO)TS7 MS_Class=1
Mass test: TS0(OOxxOOxO)TS7 MS_Class=2
Mass test: TS0(OOxxOOxO)TS7 MS_Class=3
Mass test: TS0(OOxxOOxO)TS7 MS_Class=4
Mass test: TS0(OOxxOOxO)TS7 MS_Class=5
Mass test: TS0(OOxxOOxO)TS7 MS_Class=6
Mass test: TS0(OOxxOOxO)TS7 MS_Class=7
Mass test: TS0(OOxxOOxO)TS7 MS_Class=8
Mass test: TS0(OOxxOOxO)TS7 MS_Class=9
Mass test: TS0(OOxxOOxO)TS7 MS_Class=10
Mass test: TS0(OOxxOOxO)TS7 MS_Class=11
Mass test: TS0(OOxxOOxO)TS7 MS_Class=12
Mass test: TS0(OOxxOOxO)TS7 MS_Class=13
Mass test: TS0(OOxxOOxO)TS7 MS_Class=14
Mass test: TS0(OOxxOOxO)TS7 MS_Class=15
Mass test: TS0(OOxxOOxO)TS7 MS_Class=16
Mass test: TS0(OOxxOOxO)TS7 MS_Class=17
Mass test: TS0(OOxxOOxO)TS7 MS_Class=18
Mass test: TS0(OOxxOOxO)TS7 MS_Class=19
Mass test: TS0(OOxxOOxO)TS7 MS_Class=20
Mass test: TS0(OOxxOOxO)TS7 MS_Class=21
Mass test: TS0(OOxxOOxO)TS7 MS_Class=22
Mass test: TS0(OOxxOOxO)TS7 MS_Class=23
Mass test: TS0(OOxxOOxO)TS7 MS_Class=24
Mass test: TS0(OOxxOOxO)TS7 MS_Class=25
Mass test: TS0(OOxxOOxO)TS7 MS_Class=26
Mass test: TS0(OOxxOOxO)TS7 MS_Class=27
Mass test: TS0(OOxxOOxO)TS7 MS_Class=28
Mass test: TS0(OOxxOOxO)TS7 MS_Class=29
Mass test: TS0(OOxxOOxO)TS7 MS_Class=30
Mass test: TS0(OOxxOOxO)TS7 MS_Class=31
Mass test: TS0(OOxxOOxO)TS7 MS_Class=32
Mass test: TS0(OOxxOOxO)TS7 MS_Class=33
Mass test: TS0(OOxxOOxO)TS7 MS_Class=34
Mass test: TS0(OOxxOOxO)TS7 MS_Class=35
Mass test: TS0(OOxxOOxO)TS7 MS_Class=36
Mass test: TS0(OOxxOOxO)TS7 MS_Class=37
Mass test: TS0(OOxxOOxO)TS7 MS_Class=38
Mass test: TS0(OOxxOOxO)TS7 MS_Class=39
Mass test: TS0(OOxxOOxO)TS7 MS_Class=40
Mass test: TS0(OOxxOOxO)TS7 MS_Class=41
Mass test: TS0(OOxxOOxO)TS7 MS_Class=42
Mass test: TS0(OOxxOOxO)TS7 MS_Class=43
Mass test: TS0(OOxxOOxO)TS7 MS_Class=44
Mass test: TS0(OOxxOOxO)TS7 MS_Class=45
Mass test: TS0(OOxxOOOx)TS7 MS_Class=0
Mass test: TS0(OOxxOOOx)TS7 MS_Class=1
Mass test: TS0(OOxxOOOx)TS7 MS_Class=2
Mass test: TS0(OOxxOOOx)TS7 MS_Class=3
Mass test: TS0(OOxxOOOx)TS7 MS_Class=4
Mass test: TS0(OOxxOOOx)TS7 MS_Class=5
Mass test: TS0(OOxxOOOx)TS7 MS_Class=6
Mass test: TS0(OOxxOOOx)TS7 MS_Class=7
Mass test: TS0(OOxxOOOx)TS7 MS_Class=8
Mass test: TS0(OOxxOOOx)TS7 MS_Class=9
Mass test: TS0(OOxxOOOx)TS7 MS_Class=10
Mass test: TS0(OOxxOOOx)TS7 MS_Class=11
Mass test: TS0(OOxxOOOx)TS7 MS_Class=12
Mass test: TS0(OOxxOOOx)TS7 MS_Class=13
Mass test: TS0(OOxxOOOx)TS7 MS_Class=14
Mass test: TS0(OOxxOOOx)TS7 MS_Class=15
Mass test: TS0(OOxxOOOx)TS7 MS_Class=16
Mass test: TS0(OOxxOOOx)TS7 MS_Class=17
Mass test: TS0(OOxxOOOx)TS7 MS_Class=18
Mass test: TS0(OOxxOOOx)TS7 MS_Class=19
Mass test: TS0(OOxxOOOx)TS7 MS_Class=20
Mass test: TS0(OOxxOOOx)TS7 MS_Class=21
Mass test: TS0(OOxxOOOx)TS7 MS_Class=22
Mass test: TS0(OOxxOOOx)TS7 MS_Class=23
Mass test: TS0(OOxxOOOx)TS7 MS_Class=24
Mass test: TS0(OOxxOOOx)TS7 MS_Class=25
Mass test: TS0(OOxxOOOx)TS7 MS_Class=26
Mass test: TS0(OOxxOOOx)TS7 MS_Class=27
Mass test: TS0(OOxxOOOx)TS7 MS_Class=28
Mass test: TS0(OOxxOOOx)TS7 MS_Class=29
Mass test: TS0(OOxxOOOx)TS7 MS_Class=30
Mass test: TS0(OOxxOOOx)TS7 MS_Class=31
Mass test: TS0(OOxxOOOx)TS7 MS_Class=32
Mass test: TS0(OOxxOOOx)TS7 MS_Class=33
Mass test: TS0(OOxxOOOx)TS7 MS_Class=34
Mass test: TS0(OOxxOOOx)TS7 MS_Class=35
Mass test: TS0(OOxxOOOx)TS7 MS_Class=36
Mass test: TS0(OOxxOOOx)TS7 MS_Class=37
Mass test: TS0(OOxxOOOx)TS7 MS_Class=38
Mass test: TS0(OOxxOOOx)TS7 MS_Class=39
Mass test: TS0(OOxxOOOx)TS7 MS_Class=40
Mass test: TS0(OOxxOOOx)TS7 MS_Class=41
Mass test: TS0(OOxxOOOx)TS7 MS_Class=42
Mass test: TS0(OOxxOOOx)TS7 MS_Class=43
Mass test: TS0(OOxxOOOx)TS7 MS_Class=44
Mass test: TS0(OOxxOOOx)TS7 MS_Class=45
Mass test: TS0(OOxxOOOO)TS7 MS_Class=0
Mass test: TS0(OOxxOOOO)TS7 MS_Class=1
Mass test: TS0(OOxxOOOO)TS7 MS_Class=2
Mass test: TS0(OOxxOOOO)TS7 MS_Class=3
Mass test: TS0(OOxxOOOO)TS7 MS_Class=4
Mass test: TS0(OOxxOOOO)TS7 MS_Class=5
Mass test: TS0(OOxxOOOO)TS7 MS_Class=6
Mass test: TS0(OOxxOOOO)TS7 MS_Class=7
Mass test: TS0(OOxxOOOO)TS7 MS_Class=8
Mass test: TS0(OOxxOOOO)TS7 MS_Class=9
Mass test: TS0(OOxxOOOO)TS7 MS_Class=10
Mass test: TS0(OOxxOOOO)TS7 MS_Class=11
Mass test: TS0(OOxxOOOO)TS7 MS_Class=12
Mass test: TS0(OOxxOOOO)TS7 MS_Class=13
Mass test: TS0(OOxxOOOO)TS7 MS_Class=14
Mass test: TS0(OOxxOOOO)TS7 MS_Class=15
Mass test: TS0(OOxxOOOO)TS7 MS_Class=16
Mass test: TS0(OOxxOOOO)TS7 MS_Class=17
Mass test: TS0(OOxxOOOO)TS7 MS_Class=18
Mass test: TS0(OOxxOOOO)TS7 MS_Class=19
Mass test: TS0(OOxxOOOO)TS7 MS_Class=20
Mass test: TS0(OOxxOOOO)TS7 MS_Class=21
Mass test: TS0(OOxxOOOO)TS7 MS_Class=22
Mass test: TS0(OOxxOOOO)TS7 MS_Class=23
Mass test: TS0(OOxxOOOO)TS7 MS_Class=24
Mass test: TS0(OOxxOOOO)TS7 MS_Class=25
Mass test: TS0(OOxxOOOO)TS7 MS_Class=26
Mass test: TS0(OOxxOOOO)TS7 MS_Class=27
Mass test: TS0(OOxxOOOO)TS7 MS_Class=28
Mass test: TS0(OOxxOOOO)TS7 MS_Class=29
Mass test: TS0(OOxxOOOO)TS7 MS_Class=30
Mass test: TS0(OOxxOOOO)TS7 MS_Class=31
Mass test: TS0(OOxxOOOO)TS7 MS_Class=32
Mass test: TS0(OOxxOOOO)TS7 MS_Class=33
Mass test: TS0(OOxxOOOO)TS7 MS_Class=34
Mass test: TS0(OOxxOOOO)TS7 MS_Class=35
Mass test: TS0(OOxxOOOO)TS7 MS_Class=36
Mass test: TS0(OOxxOOOO)TS7 MS_Class=37
Mass test: TS0(OOxxOOOO)TS7 MS_Class=38
Mass test: TS0(OOxxOOOO)TS7 MS_Class=39
Mass test: TS0(OOxxOOOO)TS7 MS_Class=40
Mass test: TS0(OOxxOOOO)TS7 MS_Class=41
Mass test: TS0(OOxxOOOO)TS7 MS_Class=42
Mass test: TS0(OOxxOOOO)TS7 MS_Class=43
Mass test: TS0(OOxxOOOO)TS7 MS_Class=44
Mass test: TS0(OOxxOOOO)TS7 MS_Class=45
Mass test: TS0(OOxOxxxx)TS7 MS_Class=0
Mass test: TS0(OOxOxxxx)TS7 MS_Class=1
Mass test: TS0(OOxOxxxx)TS7 MS_Class=2
Mass test: TS0(OOxOxxxx)TS7 MS_Class=3
Mass test: TS0(OOxOxxxx)TS7 MS_Class=4
Mass test: TS0(OOxOxxxx)TS7 MS_Class=5
Mass test: TS0(OOxOxxxx)TS7 MS_Class=6
Mass test: TS0(OOxOxxxx)TS7 MS_Class=7
Mass test: TS0(OOxOxxxx)TS7 MS_Class=8
Mass test: TS0(OOxOxxxx)TS7 MS_Class=9
Mass test: TS0(OOxOxxxx)TS7 MS_Class=10
Mass test: TS0(OOxOxxxx)TS7 MS_Class=11
Mass test: TS0(OOxOxxxx)TS7 MS_Class=12
Mass test: TS0(OOxOxxxx)TS7 MS_Class=13
Mass test: TS0(OOxOxxxx)TS7 MS_Class=14
Mass test: TS0(OOxOxxxx)TS7 MS_Class=15
Mass test: TS0(OOxOxxxx)TS7 MS_Class=16
Mass test: TS0(OOxOxxxx)TS7 MS_Class=17
Mass test: TS0(OOxOxxxx)TS7 MS_Class=18
Mass test: TS0(OOxOxxxx)TS7 MS_Class=19
Mass test: TS0(OOxOxxxx)TS7 MS_Class=20
Mass test: TS0(OOxOxxxx)TS7 MS_Class=21
Mass test: TS0(OOxOxxxx)TS7 MS_Class=22
Mass test: TS0(OOxOxxxx)TS7 MS_Class=23
Mass test: TS0(OOxOxxxx)TS7 MS_Class=24
Mass test: TS0(OOxOxxxx)TS7 MS_Class=25
Mass test: TS0(OOxOxxxx)TS7 MS_Class=26
Mass test: TS0(OOxOxxxx)TS7 MS_Class=27
Mass test: TS0(OOxOxxxx)TS7 MS_Class=28
Mass test: TS0(OOxOxxxx)TS7 MS_Class=29
Mass test: TS0(OOxOxxxx)TS7 MS_Class=30
Mass test: TS0(OOxOxxxx)TS7 MS_Class=31
Mass test: TS0(OOxOxxxx)TS7 MS_Class=32
Mass test: TS0(OOxOxxxx)TS7 MS_Class=33
Mass test: TS0(OOxOxxxx)TS7 MS_Class=34
Mass test: TS0(OOxOxxxx)TS7 MS_Class=35
Mass test: TS0(OOxOxxxx)TS7 MS_Class=36
Mass test: TS0(OOxOxxxx)TS7 MS_Class=37
Mass test: TS0(OOxOxxxx)TS7 MS_Class=38
Mass test: TS0(OOxOxxxx)TS7 MS_Class=39
Mass test: TS0(OOxOxxxx)TS7 MS_Class=40
Mass test: TS0(OOxOxxxx)TS7 MS_Class=41
Mass test: TS0(OOxOxxxx)TS7 MS_Class=42
Mass test: TS0(OOxOxxxx)TS7 MS_Class=43
Mass test: TS0(OOxOxxxx)TS7 MS_Class=44
Mass test: TS0(OOxOxxxx)TS7 MS_Class=45
Mass test: TS0(OOxOxxxO)TS7 MS_Class=0
Mass test: TS0(OOxOxxxO)TS7 MS_Class=1
Mass test: TS0(OOxOxxxO)TS7 MS_Class=2
Mass test: TS0(OOxOxxxO)TS7 MS_Class=3
Mass test: TS0(OOxOxxxO)TS7 MS_Class=4
Mass test: TS0(OOxOxxxO)TS7 MS_Class=5
Mass test: TS0(OOxOxxxO)TS7 MS_Class=6
Mass test: TS0(OOxOxxxO)TS7 MS_Class=7
Mass test: TS0(OOxOxxxO)TS7 MS_Class=8
Mass test: TS0(OOxOxxxO)TS7 MS_Class=9
Mass test: TS0(OOxOxxxO)TS7 MS_Class=10
Mass test: TS0(OOxOxxxO)TS7 MS_Class=11
Mass test: TS0(OOxOxxxO)TS7 MS_Class=12
Mass test: TS0(OOxOxxxO)TS7 MS_Class=13
Mass test: TS0(OOxOxxxO)TS7 MS_Class=14
Mass test: TS0(OOxOxxxO)TS7 MS_Class=15
Mass test: TS0(OOxOxxxO)TS7 MS_Class=16
Mass test: TS0(OOxOxxxO)TS7 MS_Class=17
Mass test: TS0(OOxOxxxO)TS7 MS_Class=18
Mass test: TS0(OOxOxxxO)TS7 MS_Class=19
Mass test: TS0(OOxOxxxO)TS7 MS_Class=20
Mass test: TS0(OOxOxxxO)TS7 MS_Class=21
Mass test: TS0(OOxOxxxO)TS7 MS_Class=22
Mass test: TS0(OOxOxxxO)TS7 MS_Class=23
Mass test: TS0(OOxOxxxO)TS7 MS_Class=24
Mass test: TS0(OOxOxxxO)TS7 MS_Class=25
Mass test: TS0(OOxOxxxO)TS7 MS_Class=26
Mass test: TS0(OOxOxxxO)TS7 MS_Class=27
Mass test: TS0(OOxOxxxO)TS7 MS_Class=28
Mass test: TS0(OOxOxxxO)TS7 MS_Class=29
Mass test: TS0(OOxOxxxO)TS7 MS_Class=30
Mass test: TS0(OOxOxxxO)TS7 MS_Class=31
Mass test: TS0(OOxOxxxO)TS7 MS_Class=32
Mass test: TS0(OOxOxxxO)TS7 MS_Class=33
Mass test: TS0(OOxOxxxO)TS7 MS_Class=34
Mass test: TS0(OOxOxxxO)TS7 MS_Class=35
Mass test: TS0(OOxOxxxO)TS7 MS_Class=36
Mass test: TS0(OOxOxxxO)TS7 MS_Class=37
Mass test: TS0(OOxOxxxO)TS7 MS_Class=38
Mass test: TS0(OOxOxxxO)TS7 MS_Class=39
Mass test: TS0(OOxOxxxO)TS7 MS_Class=40
Mass test: TS0(OOxOxxxO)TS7 MS_Class=41
Mass test: TS0(OOxOxxxO)TS7 MS_Class=42
Mass test: TS0(OOxOxxxO)TS7 MS_Class=43
Mass test: TS0(OOxOxxxO)TS7 MS_Class=44
Mass test: TS0(OOxOxxxO)TS7 MS_Class=45
Mass test: TS0(OOxOxxOx)TS7 MS_Class=0
Mass test: TS0(OOxOxxOx)TS7 MS_Class=1
Mass test: TS0(OOxOxxOx)TS7 MS_Class=2
Mass test: TS0(OOxOxxOx)TS7 MS_Class=3
Mass test: TS0(OOxOxxOx)TS7 MS_Class=4
Mass test: TS0(OOxOxxOx)TS7 MS_Class=5
Mass test: TS0(OOxOxxOx)TS7 MS_Class=6
Mass test: TS0(OOxOxxOx)TS7 MS_Class=7
Mass test: TS0(OOxOxxOx)TS7 MS_Class=8
Mass test: TS0(OOxOxxOx)TS7 MS_Class=9
Mass test: TS0(OOxOxxOx)TS7 MS_Class=10
Mass test: TS0(OOxOxxOx)TS7 MS_Class=11
Mass test: TS0(OOxOxxOx)TS7 MS_Class=12
Mass test: TS0(OOxOxxOx)TS7 MS_Class=13
Mass test: TS0(OOxOxxOx)TS7 MS_Class=14
Mass test: TS0(OOxOxxOx)TS7 MS_Class=15
Mass test: TS0(OOxOxxOx)TS7 MS_Class=16
Mass test: TS0(OOxOxxOx)TS7 MS_Class=17
Mass test: TS0(OOxOxxOx)TS7 MS_Class=18
Mass test: TS0(OOxOxxOx)TS7 MS_Class=19
Mass test: TS0(OOxOxxOx)TS7 MS_Class=20
Mass test: TS0(OOxOxxOx)TS7 MS_Class=21
Mass test: TS0(OOxOxxOx)TS7 MS_Class=22
Mass test: TS0(OOxOxxOx)TS7 MS_Class=23
Mass test: TS0(OOxOxxOx)TS7 MS_Class=24
Mass test: TS0(OOxOxxOx)TS7 MS_Class=25
Mass test: TS0(OOxOxxOx)TS7 MS_Class=26
Mass test: TS0(OOxOxxOx)TS7 MS_Class=27
Mass test: TS0(OOxOxxOx)TS7 MS_Class=28
Mass test: TS0(OOxOxxOx)TS7 MS_Class=29
Mass test: TS0(OOxOxxOx)TS7 MS_Class=30
Mass test: TS0(OOxOxxOx)TS7 MS_Class=31
Mass test: TS0(OOxOxxOx)TS7 MS_Class=32
Mass test: TS0(OOxOxxOx)TS7 MS_Class=33
Mass test: TS0(OOxOxxOx)TS7 MS_Class=34
Mass test: TS0(OOxOxxOx)TS7 MS_Class=35
Mass test: TS0(OOxOxxOx)TS7 MS_Class=36
Mass test: TS0(OOxOxxOx)TS7 MS_Class=37
Mass test: TS0(OOxOxxOx)TS7 MS_Class=38
Mass test: TS0(OOxOxxOx)TS7 MS_Class=39
Mass test: TS0(OOxOxxOx)TS7 MS_Class=40
Mass test: TS0(OOxOxxOx)TS7 MS_Class=41
Mass test: TS0(OOxOxxOx)TS7 MS_Class=42
Mass test: TS0(OOxOxxOx)TS7 MS_Class=43
Mass test: TS0(OOxOxxOx)TS7 MS_Class=44
Mass test: TS0(OOxOxxOx)TS7 MS_Class=45
Mass test: TS0(OOxOxxOO)TS7 MS_Class=0
Mass test: TS0(OOxOxxOO)TS7 MS_Class=1
Mass test: TS0(OOxOxxOO)TS7 MS_Class=2
Mass test: TS0(OOxOxxOO)TS7 MS_Class=3
Mass test: TS0(OOxOxxOO)TS7 MS_Class=4
Mass test: TS0(OOxOxxOO)TS7 MS_Class=5
Mass test: TS0(OOxOxxOO)TS7 MS_Class=6
Mass test: TS0(OOxOxxOO)TS7 MS_Class=7
Mass test: TS0(OOxOxxOO)TS7 MS_Class=8
Mass test: TS0(OOxOxxOO)TS7 MS_Class=9
Mass test: TS0(OOxOxxOO)TS7 MS_Class=10
Mass test: TS0(OOxOxxOO)TS7 MS_Class=11
Mass test: TS0(OOxOxxOO)TS7 MS_Class=12
Mass test: TS0(OOxOxxOO)TS7 MS_Class=13
Mass test: TS0(OOxOxxOO)TS7 MS_Class=14
Mass test: TS0(OOxOxxOO)TS7 MS_Class=15
Mass test: TS0(OOxOxxOO)TS7 MS_Class=16
Mass test: TS0(OOxOxxOO)TS7 MS_Class=17
Mass test: TS0(OOxOxxOO)TS7 MS_Class=18
Mass test: TS0(OOxOxxOO)TS7 MS_Class=19
Mass test: TS0(OOxOxxOO)TS7 MS_Class=20
Mass test: TS0(OOxOxxOO)TS7 MS_Class=21
Mass test: TS0(OOxOxxOO)TS7 MS_Class=22
Mass test: TS0(OOxOxxOO)TS7 MS_Class=23
Mass test: TS0(OOxOxxOO)TS7 MS_Class=24
Mass test: TS0(OOxOxxOO)TS7 MS_Class=25
Mass test: TS0(OOxOxxOO)TS7 MS_Class=26
Mass test: TS0(OOxOxxOO)TS7 MS_Class=27
Mass test: TS0(OOxOxxOO)TS7 MS_Class=28
Mass test: TS0(OOxOxxOO)TS7 MS_Class=29
Mass test: TS0(OOxOxxOO)TS7 MS_Class=30
Mass test: TS0(OOxOxxOO)TS7 MS_Class=31
Mass test: TS0(OOxOxxOO)TS7 MS_Class=32
Mass test: TS0(OOxOxxOO)TS7 MS_Class=33
Mass test: TS0(OOxOxxOO)TS7 MS_Class=34
Mass test: TS0(OOxOxxOO)TS7 MS_Class=35
Mass test: TS0(OOxOxxOO)TS7 MS_Class=36
Mass test: TS0(OOxOxxOO)TS7 MS_Class=37
Mass test: TS0(OOxOxxOO)TS7 MS_Class=38
Mass test: TS0(OOxOxxOO)TS7 MS_Class=39
Mass test: TS0(OOxOxxOO)TS7 MS_Class=40
Mass test: TS0(OOxOxxOO)TS7 MS_Class=41
Mass test: TS0(OOxOxxOO)TS7 MS_Class=42
Mass test: TS0(OOxOxxOO)TS7 MS_Class=43
Mass test: TS0(OOxOxxOO)TS7 MS_Class=44
Mass test: TS0(OOxOxxOO)TS7 MS_Class=45
Mass test: TS0(OOxOxOxx)TS7 MS_Class=0
Mass test: TS0(OOxOxOxx)TS7 MS_Class=1
Mass test: TS0(OOxOxOxx)TS7 MS_Class=2
Mass test: TS0(OOxOxOxx)TS7 MS_Class=3
Mass test: TS0(OOxOxOxx)TS7 MS_Class=4
Mass test: TS0(OOxOxOxx)TS7 MS_Class=5
Mass test: TS0(OOxOxOxx)TS7 MS_Class=6
Mass test: TS0(OOxOxOxx)TS7 MS_Class=7
Mass test: TS0(OOxOxOxx)TS7 MS_Class=8
Mass test: TS0(OOxOxOxx)TS7 MS_Class=9
Mass test: TS0(OOxOxOxx)TS7 MS_Class=10
Mass test: TS0(OOxOxOxx)TS7 MS_Class=11
Mass test: TS0(OOxOxOxx)TS7 MS_Class=12
Mass test: TS0(OOxOxOxx)TS7 MS_Class=13
Mass test: TS0(OOxOxOxx)TS7 MS_Class=14
Mass test: TS0(OOxOxOxx)TS7 MS_Class=15
Mass test: TS0(OOxOxOxx)TS7 MS_Class=16
Mass test: TS0(OOxOxOxx)TS7 MS_Class=17
Mass test: TS0(OOxOxOxx)TS7 MS_Class=18
Mass test: TS0(OOxOxOxx)TS7 MS_Class=19
Mass test: TS0(OOxOxOxx)TS7 MS_Class=20
Mass test: TS0(OOxOxOxx)TS7 MS_Class=21
Mass test: TS0(OOxOxOxx)TS7 MS_Class=22
Mass test: TS0(OOxOxOxx)TS7 MS_Class=23
Mass test: TS0(OOxOxOxx)TS7 MS_Class=24
Mass test: TS0(OOxOxOxx)TS7 MS_Class=25
Mass test: TS0(OOxOxOxx)TS7 MS_Class=26
Mass test: TS0(OOxOxOxx)TS7 MS_Class=27
Mass test: TS0(OOxOxOxx)TS7 MS_Class=28
Mass test: TS0(OOxOxOxx)TS7 MS_Class=29
Mass test: TS0(OOxOxOxx)TS7 MS_Class=30
Mass test: TS0(OOxOxOxx)TS7 MS_Class=31
Mass test: TS0(OOxOxOxx)TS7 MS_Class=32
Mass test: TS0(OOxOxOxx)TS7 MS_Class=33
Mass test: TS0(OOxOxOxx)TS7 MS_Class=34
Mass test: TS0(OOxOxOxx)TS7 MS_Class=35
Mass test: TS0(OOxOxOxx)TS7 MS_Class=36
Mass test: TS0(OOxOxOxx)TS7 MS_Class=37
Mass test: TS0(OOxOxOxx)TS7 MS_Class=38
Mass test: TS0(OOxOxOxx)TS7 MS_Class=39
Mass test: TS0(OOxOxOxx)TS7 MS_Class=40
Mass test: TS0(OOxOxOxx)TS7 MS_Class=41
Mass test: TS0(OOxOxOxx)TS7 MS_Class=42
Mass test: TS0(OOxOxOxx)TS7 MS_Class=43
Mass test: TS0(OOxOxOxx)TS7 MS_Class=44
Mass test: TS0(OOxOxOxx)TS7 MS_Class=45
Mass test: TS0(OOxOxOxO)TS7 MS_Class=0
Mass test: TS0(OOxOxOxO)TS7 MS_Class=1
Mass test: TS0(OOxOxOxO)TS7 MS_Class=2
Mass test: TS0(OOxOxOxO)TS7 MS_Class=3
Mass test: TS0(OOxOxOxO)TS7 MS_Class=4
Mass test: TS0(OOxOxOxO)TS7 MS_Class=5
Mass test: TS0(OOxOxOxO)TS7 MS_Class=6
Mass test: TS0(OOxOxOxO)TS7 MS_Class=7
Mass test: TS0(OOxOxOxO)TS7 MS_Class=8
Mass test: TS0(OOxOxOxO)TS7 MS_Class=9
Mass test: TS0(OOxOxOxO)TS7 MS_Class=10
Mass test: TS0(OOxOxOxO)TS7 MS_Class=11
Mass test: TS0(OOxOxOxO)TS7 MS_Class=12
Mass test: TS0(OOxOxOxO)TS7 MS_Class=13
Mass test: TS0(OOxOxOxO)TS7 MS_Class=14
Mass test: TS0(OOxOxOxO)TS7 MS_Class=15
Mass test: TS0(OOxOxOxO)TS7 MS_Class=16
Mass test: TS0(OOxOxOxO)TS7 MS_Class=17
Mass test: TS0(OOxOxOxO)TS7 MS_Class=18
Mass test: TS0(OOxOxOxO)TS7 MS_Class=19
Mass test: TS0(OOxOxOxO)TS7 MS_Class=20
Mass test: TS0(OOxOxOxO)TS7 MS_Class=21
Mass test: TS0(OOxOxOxO)TS7 MS_Class=22
Mass test: TS0(OOxOxOxO)TS7 MS_Class=23
Mass test: TS0(OOxOxOxO)TS7 MS_Class=24
Mass test: TS0(OOxOxOxO)TS7 MS_Class=25
Mass test: TS0(OOxOxOxO)TS7 MS_Class=26
Mass test: TS0(OOxOxOxO)TS7 MS_Class=27
Mass test: TS0(OOxOxOxO)TS7 MS_Class=28
Mass test: TS0(OOxOxOxO)TS7 MS_Class=29
Mass test: TS0(OOxOxOxO)TS7 MS_Class=30
Mass test: TS0(OOxOxOxO)TS7 MS_Class=31
Mass test: TS0(OOxOxOxO)TS7 MS_Class=32
Mass test: TS0(OOxOxOxO)TS7 MS_Class=33
Mass test: TS0(OOxOxOxO)TS7 MS_Class=34
Mass test: TS0(OOxOxOxO)TS7 MS_Class=35
Mass test: TS0(OOxOxOxO)TS7 MS_Class=36
Mass test: TS0(OOxOxOxO)TS7 MS_Class=37
Mass test: TS0(OOxOxOxO)TS7 MS_Class=38
Mass test: TS0(OOxOxOxO)TS7 MS_Class=39
Mass test: TS0(OOxOxOxO)TS7 MS_Class=40
Mass test: TS0(OOxOxOxO)TS7 MS_Class=41
Mass test: TS0(OOxOxOxO)TS7 MS_Class=42
Mass test: TS0(OOxOxOxO)TS7 MS_Class=43
Mass test: TS0(OOxOxOxO)TS7 MS_Class=44
Mass test: TS0(OOxOxOxO)TS7 MS_Class=45
Mass test: TS0(OOxOxOOx)TS7 MS_Class=0
Mass test: TS0(OOxOxOOx)TS7 MS_Class=1
Mass test: TS0(OOxOxOOx)TS7 MS_Class=2
Mass test: TS0(OOxOxOOx)TS7 MS_Class=3
Mass test: TS0(OOxOxOOx)TS7 MS_Class=4
Mass test: TS0(OOxOxOOx)TS7 MS_Class=5
Mass test: TS0(OOxOxOOx)TS7 MS_Class=6
Mass test: TS0(OOxOxOOx)TS7 MS_Class=7
Mass test: TS0(OOxOxOOx)TS7 MS_Class=8
Mass test: TS0(OOxOxOOx)TS7 MS_Class=9
Mass test: TS0(OOxOxOOx)TS7 MS_Class=10
Mass test: TS0(OOxOxOOx)TS7 MS_Class=11
Mass test: TS0(OOxOxOOx)TS7 MS_Class=12
Mass test: TS0(OOxOxOOx)TS7 MS_Class=13
Mass test: TS0(OOxOxOOx)TS7 MS_Class=14
Mass test: TS0(OOxOxOOx)TS7 MS_Class=15
Mass test: TS0(OOxOxOOx)TS7 MS_Class=16
Mass test: TS0(OOxOxOOx)TS7 MS_Class=17
Mass test: TS0(OOxOxOOx)TS7 MS_Class=18
Mass test: TS0(OOxOxOOx)TS7 MS_Class=19
Mass test: TS0(OOxOxOOx)TS7 MS_Class=20
Mass test: TS0(OOxOxOOx)TS7 MS_Class=21
Mass test: TS0(OOxOxOOx)TS7 MS_Class=22
Mass test: TS0(OOxOxOOx)TS7 MS_Class=23
Mass test: TS0(OOxOxOOx)TS7 MS_Class=24
Mass test: TS0(OOxOxOOx)TS7 MS_Class=25
Mass test: TS0(OOxOxOOx)TS7 MS_Class=26
Mass test: TS0(OOxOxOOx)TS7 MS_Class=27
Mass test: TS0(OOxOxOOx)TS7 MS_Class=28
Mass test: TS0(OOxOxOOx)TS7 MS_Class=29
Mass test: TS0(OOxOxOOx)TS7 MS_Class=30
Mass test: TS0(OOxOxOOx)TS7 MS_Class=31
Mass test: TS0(OOxOxOOx)TS7 MS_Class=32
Mass test: TS0(OOxOxOOx)TS7 MS_Class=33
Mass test: TS0(OOxOxOOx)TS7 MS_Class=34
Mass test: TS0(OOxOxOOx)TS7 MS_Class=35
Mass test: TS0(OOxOxOOx)TS7 MS_Class=36
Mass test: TS0(OOxOxOOx)TS7 MS_Class=37
Mass test: TS0(OOxOxOOx)TS7 MS_Class=38
Mass test: TS0(OOxOxOOx)TS7 MS_Class=39
Mass test: TS0(OOxOxOOx)TS7 MS_Class=40
Mass test: TS0(OOxOxOOx)TS7 MS_Class=41
Mass test: TS0(OOxOxOOx)TS7 MS_Class=42
Mass test: TS0(OOxOxOOx)TS7 MS_Class=43
Mass test: TS0(OOxOxOOx)TS7 MS_Class=44
Mass test: TS0(OOxOxOOx)TS7 MS_Class=45
Mass test: TS0(OOxOxOOO)TS7 MS_Class=0
Mass test: TS0(OOxOxOOO)TS7 MS_Class=1
Mass test: TS0(OOxOxOOO)TS7 MS_Class=2
Mass test: TS0(OOxOxOOO)TS7 MS_Class=3
Mass test: TS0(OOxOxOOO)TS7 MS_Class=4
Mass test: TS0(OOxOxOOO)TS7 MS_Class=5
Mass test: TS0(OOxOxOOO)TS7 MS_Class=6
Mass test: TS0(OOxOxOOO)TS7 MS_Class=7
Mass test: TS0(OOxOxOOO)TS7 MS_Class=8
Mass test: TS0(OOxOxOOO)TS7 MS_Class=9
Mass test: TS0(OOxOxOOO)TS7 MS_Class=10
Mass test: TS0(OOxOxOOO)TS7 MS_Class=11
Mass test: TS0(OOxOxOOO)TS7 MS_Class=12
Mass test: TS0(OOxOxOOO)TS7 MS_Class=13
Mass test: TS0(OOxOxOOO)TS7 MS_Class=14
Mass test: TS0(OOxOxOOO)TS7 MS_Class=15
Mass test: TS0(OOxOxOOO)TS7 MS_Class=16
Mass test: TS0(OOxOxOOO)TS7 MS_Class=17
Mass test: TS0(OOxOxOOO)TS7 MS_Class=18
Mass test: TS0(OOxOxOOO)TS7 MS_Class=19
Mass test: TS0(OOxOxOOO)TS7 MS_Class=20
Mass test: TS0(OOxOxOOO)TS7 MS_Class=21
Mass test: TS0(OOxOxOOO)TS7 MS_Class=22
Mass test: TS0(OOxOxOOO)TS7 MS_Class=23
Mass test: TS0(OOxOxOOO)TS7 MS_Class=24
Mass test: TS0(OOxOxOOO)TS7 MS_Class=25
Mass test: TS0(OOxOxOOO)TS7 MS_Class=26
Mass test: TS0(OOxOxOOO)TS7 MS_Class=27
Mass test: TS0(OOxOxOOO)TS7 MS_Class=28
Mass test: TS0(OOxOxOOO)TS7 MS_Class=29
Mass test: TS0(OOxOxOOO)TS7 MS_Class=30
Mass test: TS0(OOxOxOOO)TS7 MS_Class=31
Mass test: TS0(OOxOxOOO)TS7 MS_Class=32
Mass test: TS0(OOxOxOOO)TS7 MS_Class=33
Mass test: TS0(OOxOxOOO)TS7 MS_Class=34
Mass test: TS0(OOxOxOOO)TS7 MS_Class=35
Mass test: TS0(OOxOxOOO)TS7 MS_Class=36
Mass test: TS0(OOxOxOOO)TS7 MS_Class=37
Mass test: TS0(OOxOxOOO)TS7 MS_Class=38
Mass test: TS0(OOxOxOOO)TS7 MS_Class=39
Mass test: TS0(OOxOxOOO)TS7 MS_Class=40
Mass test: TS0(OOxOxOOO)TS7 MS_Class=41
Mass test: TS0(OOxOxOOO)TS7 MS_Class=42
Mass test: TS0(OOxOxOOO)TS7 MS_Class=43
Mass test: TS0(OOxOxOOO)TS7 MS_Class=44
Mass test: TS0(OOxOxOOO)TS7 MS_Class=45
Mass test: TS0(OOxOOxxx)TS7 MS_Class=0
Mass test: TS0(OOxOOxxx)TS7 MS_Class=1
Mass test: TS0(OOxOOxxx)TS7 MS_Class=2
Mass test: TS0(OOxOOxxx)TS7 MS_Class=3
Mass test: TS0(OOxOOxxx)TS7 MS_Class=4
Mass test: TS0(OOxOOxxx)TS7 MS_Class=5
Mass test: TS0(OOxOOxxx)TS7 MS_Class=6
Mass test: TS0(OOxOOxxx)TS7 MS_Class=7
Mass test: TS0(OOxOOxxx)TS7 MS_Class=8
Mass test: TS0(OOxOOxxx)TS7 MS_Class=9
Mass test: TS0(OOxOOxxx)TS7 MS_Class=10
Mass test: TS0(OOxOOxxx)TS7 MS_Class=11
Mass test: TS0(OOxOOxxx)TS7 MS_Class=12
Mass test: TS0(OOxOOxxx)TS7 MS_Class=13
Mass test: TS0(OOxOOxxx)TS7 MS_Class=14
Mass test: TS0(OOxOOxxx)TS7 MS_Class=15
Mass test: TS0(OOxOOxxx)TS7 MS_Class=16
Mass test: TS0(OOxOOxxx)TS7 MS_Class=17
Mass test: TS0(OOxOOxxx)TS7 MS_Class=18
Mass test: TS0(OOxOOxxx)TS7 MS_Class=19
Mass test: TS0(OOxOOxxx)TS7 MS_Class=20
Mass test: TS0(OOxOOxxx)TS7 MS_Class=21
Mass test: TS0(OOxOOxxx)TS7 MS_Class=22
Mass test: TS0(OOxOOxxx)TS7 MS_Class=23
Mass test: TS0(OOxOOxxx)TS7 MS_Class=24
Mass test: TS0(OOxOOxxx)TS7 MS_Class=25
Mass test: TS0(OOxOOxxx)TS7 MS_Class=26
Mass test: TS0(OOxOOxxx)TS7 MS_Class=27
Mass test: TS0(OOxOOxxx)TS7 MS_Class=28
Mass test: TS0(OOxOOxxx)TS7 MS_Class=29
Mass test: TS0(OOxOOxxx)TS7 MS_Class=30
Mass test: TS0(OOxOOxxx)TS7 MS_Class=31
Mass test: TS0(OOxOOxxx)TS7 MS_Class=32
Mass test: TS0(OOxOOxxx)TS7 MS_Class=33
Mass test: TS0(OOxOOxxx)TS7 MS_Class=34
Mass test: TS0(OOxOOxxx)TS7 MS_Class=35
Mass test: TS0(OOxOOxxx)TS7 MS_Class=36
Mass test: TS0(OOxOOxxx)TS7 MS_Class=37
Mass test: TS0(OOxOOxxx)TS7 MS_Class=38
Mass test: TS0(OOxOOxxx)TS7 MS_Class=39
Mass test: TS0(OOxOOxxx)TS7 MS_Class=40
Mass test: TS0(OOxOOxxx)TS7 MS_Class=41
Mass test: TS0(OOxOOxxx)TS7 MS_Class=42
Mass test: TS0(OOxOOxxx)TS7 MS_Class=43
Mass test: TS0(OOxOOxxx)TS7 MS_Class=44
Mass test: TS0(OOxOOxxx)TS7 MS_Class=45
Mass test: TS0(OOxOOxxO)TS7 MS_Class=0
Mass test: TS0(OOxOOxxO)TS7 MS_Class=1
Mass test: TS0(OOxOOxxO)TS7 MS_Class=2
Mass test: TS0(OOxOOxxO)TS7 MS_Class=3
Mass test: TS0(OOxOOxxO)TS7 MS_Class=4
Mass test: TS0(OOxOOxxO)TS7 MS_Class=5
Mass test: TS0(OOxOOxxO)TS7 MS_Class=6
Mass test: TS0(OOxOOxxO)TS7 MS_Class=7
Mass test: TS0(OOxOOxxO)TS7 MS_Class=8
Mass test: TS0(OOxOOxxO)TS7 MS_Class=9
Mass test: TS0(OOxOOxxO)TS7 MS_Class=10
Mass test: TS0(OOxOOxxO)TS7 MS_Class=11
Mass test: TS0(OOxOOxxO)TS7 MS_Class=12
Mass test: TS0(OOxOOxxO)TS7 MS_Class=13
Mass test: TS0(OOxOOxxO)TS7 MS_Class=14
Mass test: TS0(OOxOOxxO)TS7 MS_Class=15
Mass test: TS0(OOxOOxxO)TS7 MS_Class=16
Mass test: TS0(OOxOOxxO)TS7 MS_Class=17
Mass test: TS0(OOxOOxxO)TS7 MS_Class=18
Mass test: TS0(OOxOOxxO)TS7 MS_Class=19
Mass test: TS0(OOxOOxxO)TS7 MS_Class=20
Mass test: TS0(OOxOOxxO)TS7 MS_Class=21
Mass test: TS0(OOxOOxxO)TS7 MS_Class=22
Mass test: TS0(OOxOOxxO)TS7 MS_Class=23
Mass test: TS0(OOxOOxxO)TS7 MS_Class=24
Mass test: TS0(OOxOOxxO)TS7 MS_Class=25
Mass test: TS0(OOxOOxxO)TS7 MS_Class=26
Mass test: TS0(OOxOOxxO)TS7 MS_Class=27
Mass test: TS0(OOxOOxxO)TS7 MS_Class=28
Mass test: TS0(OOxOOxxO)TS7 MS_Class=29
Mass test: TS0(OOxOOxxO)TS7 MS_Class=30
Mass test: TS0(OOxOOxxO)TS7 MS_Class=31
Mass test: TS0(OOxOOxxO)TS7 MS_Class=32
Mass test: TS0(OOxOOxxO)TS7 MS_Class=33
Mass test: TS0(OOxOOxxO)TS7 MS_Class=34
Mass test: TS0(OOxOOxxO)TS7 MS_Class=35
Mass test: TS0(OOxOOxxO)TS7 MS_Class=36
Mass test: TS0(OOxOOxxO)TS7 MS_Class=37
Mass test: TS0(OOxOOxxO)TS7 MS_Class=38
Mass test: TS0(OOxOOxxO)TS7 MS_Class=39
Mass test: TS0(OOxOOxxO)TS7 MS_Class=40
Mass test: TS0(OOxOOxxO)TS7 MS_Class=41
Mass test: TS0(OOxOOxxO)TS7 MS_Class=42
Mass test: TS0(OOxOOxxO)TS7 MS_Class=43
Mass test: TS0(OOxOOxxO)TS7 MS_Class=44
Mass test: TS0(OOxOOxxO)TS7 MS_Class=45
Mass test: TS0(OOxOOxOx)TS7 MS_Class=0
Mass test: TS0(OOxOOxOx)TS7 MS_Class=1
Mass test: TS0(OOxOOxOx)TS7 MS_Class=2
Mass test: TS0(OOxOOxOx)TS7 MS_Class=3
Mass test: TS0(OOxOOxOx)TS7 MS_Class=4
Mass test: TS0(OOxOOxOx)TS7 MS_Class=5
Mass test: TS0(OOxOOxOx)TS7 MS_Class=6
Mass test: TS0(OOxOOxOx)TS7 MS_Class=7
Mass test: TS0(OOxOOxOx)TS7 MS_Class=8
Mass test: TS0(OOxOOxOx)TS7 MS_Class=9
Mass test: TS0(OOxOOxOx)TS7 MS_Class=10
Mass test: TS0(OOxOOxOx)TS7 MS_Class=11
Mass test: TS0(OOxOOxOx)TS7 MS_Class=12
Mass test: TS0(OOxOOxOx)TS7 MS_Class=13
Mass test: TS0(OOxOOxOx)TS7 MS_Class=14
Mass test: TS0(OOxOOxOx)TS7 MS_Class=15
Mass test: TS0(OOxOOxOx)TS7 MS_Class=16
Mass test: TS0(OOxOOxOx)TS7 MS_Class=17
Mass test: TS0(OOxOOxOx)TS7 MS_Class=18
Mass test: TS0(OOxOOxOx)TS7 MS_Class=19
Mass test: TS0(OOxOOxOx)TS7 MS_Class=20
Mass test: TS0(OOxOOxOx)TS7 MS_Class=21
Mass test: TS0(OOxOOxOx)TS7 MS_Class=22
Mass test: TS0(OOxOOxOx)TS7 MS_Class=23
Mass test: TS0(OOxOOxOx)TS7 MS_Class=24
Mass test: TS0(OOxOOxOx)TS7 MS_Class=25
Mass test: TS0(OOxOOxOx)TS7 MS_Class=26
Mass test: TS0(OOxOOxOx)TS7 MS_Class=27
Mass test: TS0(OOxOOxOx)TS7 MS_Class=28
Mass test: TS0(OOxOOxOx)TS7 MS_Class=29
Mass test: TS0(OOxOOxOx)TS7 MS_Class=30
Mass test: TS0(OOxOOxOx)TS7 MS_Class=31
Mass test: TS0(OOxOOxOx)TS7 MS_Class=32
Mass test: TS0(OOxOOxOx)TS7 MS_Class=33
Mass test: TS0(OOxOOxOx)TS7 MS_Class=34
Mass test: TS0(OOxOOxOx)TS7 MS_Class=35
Mass test: TS0(OOxOOxOx)TS7 MS_Class=36
Mass test: TS0(OOxOOxOx)TS7 MS_Class=37
Mass test: TS0(OOxOOxOx)TS7 MS_Class=38
Mass test: TS0(OOxOOxOx)TS7 MS_Class=39
Mass test: TS0(OOxOOxOx)TS7 MS_Class=40
Mass test: TS0(OOxOOxOx)TS7 MS_Class=41
Mass test: TS0(OOxOOxOx)TS7 MS_Class=42
Mass test: TS0(OOxOOxOx)TS7 MS_Class=43
Mass test: TS0(OOxOOxOx)TS7 MS_Class=44
Mass test: TS0(OOxOOxOx)TS7 MS_Class=45
Mass test: TS0(OOxOOxOO)TS7 MS_Class=0
Mass test: TS0(OOxOOxOO)TS7 MS_Class=1
Mass test: TS0(OOxOOxOO)TS7 MS_Class=2
Mass test: TS0(OOxOOxOO)TS7 MS_Class=3
Mass test: TS0(OOxOOxOO)TS7 MS_Class=4
Mass test: TS0(OOxOOxOO)TS7 MS_Class=5
Mass test: TS0(OOxOOxOO)TS7 MS_Class=6
Mass test: TS0(OOxOOxOO)TS7 MS_Class=7
Mass test: TS0(OOxOOxOO)TS7 MS_Class=8
Mass test: TS0(OOxOOxOO)TS7 MS_Class=9
Mass test: TS0(OOxOOxOO)TS7 MS_Class=10
Mass test: TS0(OOxOOxOO)TS7 MS_Class=11
Mass test: TS0(OOxOOxOO)TS7 MS_Class=12
Mass test: TS0(OOxOOxOO)TS7 MS_Class=13
Mass test: TS0(OOxOOxOO)TS7 MS_Class=14
Mass test: TS0(OOxOOxOO)TS7 MS_Class=15
Mass test: TS0(OOxOOxOO)TS7 MS_Class=16
Mass test: TS0(OOxOOxOO)TS7 MS_Class=17
Mass test: TS0(OOxOOxOO)TS7 MS_Class=18
Mass test: TS0(OOxOOxOO)TS7 MS_Class=19
Mass test: TS0(OOxOOxOO)TS7 MS_Class=20
Mass test: TS0(OOxOOxOO)TS7 MS_Class=21
Mass test: TS0(OOxOOxOO)TS7 MS_Class=22
Mass test: TS0(OOxOOxOO)TS7 MS_Class=23
Mass test: TS0(OOxOOxOO)TS7 MS_Class=24
Mass test: TS0(OOxOOxOO)TS7 MS_Class=25
Mass test: TS0(OOxOOxOO)TS7 MS_Class=26
Mass test: TS0(OOxOOxOO)TS7 MS_Class=27
Mass test: TS0(OOxOOxOO)TS7 MS_Class=28
Mass test: TS0(OOxOOxOO)TS7 MS_Class=29
Mass test: TS0(OOxOOxOO)TS7 MS_Class=30
Mass test: TS0(OOxOOxOO)TS7 MS_Class=31
Mass test: TS0(OOxOOxOO)TS7 MS_Class=32
Mass test: TS0(OOxOOxOO)TS7 MS_Class=33
Mass test: TS0(OOxOOxOO)TS7 MS_Class=34
Mass test: TS0(OOxOOxOO)TS7 MS_Class=35
Mass test: TS0(OOxOOxOO)TS7 MS_Class=36
Mass test: TS0(OOxOOxOO)TS7 MS_Class=37
Mass test: TS0(OOxOOxOO)TS7 MS_Class=38
Mass test: TS0(OOxOOxOO)TS7 MS_Class=39
Mass test: TS0(OOxOOxOO)TS7 MS_Class=40
Mass test: TS0(OOxOOxOO)TS7 MS_Class=41
Mass test: TS0(OOxOOxOO)TS7 MS_Class=42
Mass test: TS0(OOxOOxOO)TS7 MS_Class=43
Mass test: TS0(OOxOOxOO)TS7 MS_Class=44
Mass test: TS0(OOxOOxOO)TS7 MS_Class=45
Mass test: TS0(OOxOOOxx)TS7 MS_Class=0
Mass test: TS0(OOxOOOxx)TS7 MS_Class=1
Mass test: TS0(OOxOOOxx)TS7 MS_Class=2
Mass test: TS0(OOxOOOxx)TS7 MS_Class=3
Mass test: TS0(OOxOOOxx)TS7 MS_Class=4
Mass test: TS0(OOxOOOxx)TS7 MS_Class=5
Mass test: TS0(OOxOOOxx)TS7 MS_Class=6
Mass test: TS0(OOxOOOxx)TS7 MS_Class=7
Mass test: TS0(OOxOOOxx)TS7 MS_Class=8
Mass test: TS0(OOxOOOxx)TS7 MS_Class=9
Mass test: TS0(OOxOOOxx)TS7 MS_Class=10
Mass test: TS0(OOxOOOxx)TS7 MS_Class=11
Mass test: TS0(OOxOOOxx)TS7 MS_Class=12
Mass test: TS0(OOxOOOxx)TS7 MS_Class=13
Mass test: TS0(OOxOOOxx)TS7 MS_Class=14
Mass test: TS0(OOxOOOxx)TS7 MS_Class=15
Mass test: TS0(OOxOOOxx)TS7 MS_Class=16
Mass test: TS0(OOxOOOxx)TS7 MS_Class=17
Mass test: TS0(OOxOOOxx)TS7 MS_Class=18
Mass test: TS0(OOxOOOxx)TS7 MS_Class=19
Mass test: TS0(OOxOOOxx)TS7 MS_Class=20
Mass test: TS0(OOxOOOxx)TS7 MS_Class=21
Mass test: TS0(OOxOOOxx)TS7 MS_Class=22
Mass test: TS0(OOxOOOxx)TS7 MS_Class=23
Mass test: TS0(OOxOOOxx)TS7 MS_Class=24
Mass test: TS0(OOxOOOxx)TS7 MS_Class=25
Mass test: TS0(OOxOOOxx)TS7 MS_Class=26
Mass test: TS0(OOxOOOxx)TS7 MS_Class=27
Mass test: TS0(OOxOOOxx)TS7 MS_Class=28
Mass test: TS0(OOxOOOxx)TS7 MS_Class=29
Mass test: TS0(OOxOOOxx)TS7 MS_Class=30
Mass test: TS0(OOxOOOxx)TS7 MS_Class=31
Mass test: TS0(OOxOOOxx)TS7 MS_Class=32
Mass test: TS0(OOxOOOxx)TS7 MS_Class=33
Mass test: TS0(OOxOOOxx)TS7 MS_Class=34
Mass test: TS0(OOxOOOxx)TS7 MS_Class=35
Mass test: TS0(OOxOOOxx)TS7 MS_Class=36
Mass test: TS0(OOxOOOxx)TS7 MS_Class=37
Mass test: TS0(OOxOOOxx)TS7 MS_Class=38
Mass test: TS0(OOxOOOxx)TS7 MS_Class=39
Mass test: TS0(OOxOOOxx)TS7 MS_Class=40
Mass test: TS0(OOxOOOxx)TS7 MS_Class=41
Mass test: TS0(OOxOOOxx)TS7 MS_Class=42
Mass test: TS0(OOxOOOxx)TS7 MS_Class=43
Mass test: TS0(OOxOOOxx)TS7 MS_Class=44
Mass test: TS0(OOxOOOxx)TS7 MS_Class=45
Mass test: TS0(OOxOOOxO)TS7 MS_Class=0
Mass test: TS0(OOxOOOxO)TS7 MS_Class=1
Mass test: TS0(OOxOOOxO)TS7 MS_Class=2
Mass test: TS0(OOxOOOxO)TS7 MS_Class=3
Mass test: TS0(OOxOOOxO)TS7 MS_Class=4
Mass test: TS0(OOxOOOxO)TS7 MS_Class=5
Mass test: TS0(OOxOOOxO)TS7 MS_Class=6
Mass test: TS0(OOxOOOxO)TS7 MS_Class=7
Mass test: TS0(OOxOOOxO)TS7 MS_Class=8
Mass test: TS0(OOxOOOxO)TS7 MS_Class=9
Mass test: TS0(OOxOOOxO)TS7 MS_Class=10
Mass test: TS0(OOxOOOxO)TS7 MS_Class=11
Mass test: TS0(OOxOOOxO)TS7 MS_Class=12
Mass test: TS0(OOxOOOxO)TS7 MS_Class=13
Mass test: TS0(OOxOOOxO)TS7 MS_Class=14
Mass test: TS0(OOxOOOxO)TS7 MS_Class=15
Mass test: TS0(OOxOOOxO)TS7 MS_Class=16
Mass test: TS0(OOxOOOxO)TS7 MS_Class=17
Mass test: TS0(OOxOOOxO)TS7 MS_Class=18
Mass test: TS0(OOxOOOxO)TS7 MS_Class=19
Mass test: TS0(OOxOOOxO)TS7 MS_Class=20
Mass test: TS0(OOxOOOxO)TS7 MS_Class=21
Mass test: TS0(OOxOOOxO)TS7 MS_Class=22
Mass test: TS0(OOxOOOxO)TS7 MS_Class=23
Mass test: TS0(OOxOOOxO)TS7 MS_Class=24
Mass test: TS0(OOxOOOxO)TS7 MS_Class=25
Mass test: TS0(OOxOOOxO)TS7 MS_Class=26
Mass test: TS0(OOxOOOxO)TS7 MS_Class=27
Mass test: TS0(OOxOOOxO)TS7 MS_Class=28
Mass test: TS0(OOxOOOxO)TS7 MS_Class=29
Mass test: TS0(OOxOOOxO)TS7 MS_Class=30
Mass test: TS0(OOxOOOxO)TS7 MS_Class=31
Mass test: TS0(OOxOOOxO)TS7 MS_Class=32
Mass test: TS0(OOxOOOxO)TS7 MS_Class=33
Mass test: TS0(OOxOOOxO)TS7 MS_Class=34
Mass test: TS0(OOxOOOxO)TS7 MS_Class=35
Mass test: TS0(OOxOOOxO)TS7 MS_Class=36
Mass test: TS0(OOxOOOxO)TS7 MS_Class=37
Mass test: TS0(OOxOOOxO)TS7 MS_Class=38
Mass test: TS0(OOxOOOxO)TS7 MS_Class=39
Mass test: TS0(OOxOOOxO)TS7 MS_Class=40
Mass test: TS0(OOxOOOxO)TS7 MS_Class=41
Mass test: TS0(OOxOOOxO)TS7 MS_Class=42
Mass test: TS0(OOxOOOxO)TS7 MS_Class=43
Mass test: TS0(OOxOOOxO)TS7 MS_Class=44
Mass test: TS0(OOxOOOxO)TS7 MS_Class=45
Mass test: TS0(OOxOOOOx)TS7 MS_Class=0
Mass test: TS0(OOxOOOOx)TS7 MS_Class=1
Mass test: TS0(OOxOOOOx)TS7 MS_Class=2
Mass test: TS0(OOxOOOOx)TS7 MS_Class=3
Mass test: TS0(OOxOOOOx)TS7 MS_Class=4
Mass test: TS0(OOxOOOOx)TS7 MS_Class=5
Mass test: TS0(OOxOOOOx)TS7 MS_Class=6
Mass test: TS0(OOxOOOOx)TS7 MS_Class=7
Mass test: TS0(OOxOOOOx)TS7 MS_Class=8
Mass test: TS0(OOxOOOOx)TS7 MS_Class=9
Mass test: TS0(OOxOOOOx)TS7 MS_Class=10
Mass test: TS0(OOxOOOOx)TS7 MS_Class=11
Mass test: TS0(OOxOOOOx)TS7 MS_Class=12
Mass test: TS0(OOxOOOOx)TS7 MS_Class=13
Mass test: TS0(OOxOOOOx)TS7 MS_Class=14
Mass test: TS0(OOxOOOOx)TS7 MS_Class=15
Mass test: TS0(OOxOOOOx)TS7 MS_Class=16
Mass test: TS0(OOxOOOOx)TS7 MS_Class=17
Mass test: TS0(OOxOOOOx)TS7 MS_Class=18
Mass test: TS0(OOxOOOOx)TS7 MS_Class=19
Mass test: TS0(OOxOOOOx)TS7 MS_Class=20
Mass test: TS0(OOxOOOOx)TS7 MS_Class=21
Mass test: TS0(OOxOOOOx)TS7 MS_Class=22
Mass test: TS0(OOxOOOOx)TS7 MS_Class=23
Mass test: TS0(OOxOOOOx)TS7 MS_Class=24
Mass test: TS0(OOxOOOOx)TS7 MS_Class=25
Mass test: TS0(OOxOOOOx)TS7 MS_Class=26
Mass test: TS0(OOxOOOOx)TS7 MS_Class=27
Mass test: TS0(OOxOOOOx)TS7 MS_Class=28
Mass test: TS0(OOxOOOOx)TS7 MS_Class=29
Mass test: TS0(OOxOOOOx)TS7 MS_Class=30
Mass test: TS0(OOxOOOOx)TS7 MS_Class=31
Mass test: TS0(OOxOOOOx)TS7 MS_Class=32
Mass test: TS0(OOxOOOOx)TS7 MS_Class=33
Mass test: TS0(OOxOOOOx)TS7 MS_Class=34
Mass test: TS0(OOxOOOOx)TS7 MS_Class=35
Mass test: TS0(OOxOOOOx)TS7 MS_Class=36
Mass test: TS0(OOxOOOOx)TS7 MS_Class=37
Mass test: TS0(OOxOOOOx)TS7 MS_Class=38
Mass test: TS0(OOxOOOOx)TS7 MS_Class=39
Mass test: TS0(OOxOOOOx)TS7 MS_Class=40
Mass test: TS0(OOxOOOOx)TS7 MS_Class=41
Mass test: TS0(OOxOOOOx)TS7 MS_Class=42
Mass test: TS0(OOxOOOOx)TS7 MS_Class=43
Mass test: TS0(OOxOOOOx)TS7 MS_Class=44
Mass test: TS0(OOxOOOOx)TS7 MS_Class=45
Mass test: TS0(OOxOOOOO)TS7 MS_Class=0
Mass test: TS0(OOxOOOOO)TS7 MS_Class=1
Mass test: TS0(OOxOOOOO)TS7 MS_Class=2
Mass test: TS0(OOxOOOOO)TS7 MS_Class=3
Mass test: TS0(OOxOOOOO)TS7 MS_Class=4
Mass test: TS0(OOxOOOOO)TS7 MS_Class=5
Mass test: TS0(OOxOOOOO)TS7 MS_Class=6
Mass test: TS0(OOxOOOOO)TS7 MS_Class=7
Mass test: TS0(OOxOOOOO)TS7 MS_Class=8
Mass test: TS0(OOxOOOOO)TS7 MS_Class=9
Mass test: TS0(OOxOOOOO)TS7 MS_Class=10
Mass test: TS0(OOxOOOOO)TS7 MS_Class=11
Mass test: TS0(OOxOOOOO)TS7 MS_Class=12
Mass test: TS0(OOxOOOOO)TS7 MS_Class=13
Mass test: TS0(OOxOOOOO)TS7 MS_Class=14
Mass test: TS0(OOxOOOOO)TS7 MS_Class=15
Mass test: TS0(OOxOOOOO)TS7 MS_Class=16
Mass test: TS0(OOxOOOOO)TS7 MS_Class=17
Mass test: TS0(OOxOOOOO)TS7 MS_Class=18
Mass test: TS0(OOxOOOOO)TS7 MS_Class=19
Mass test: TS0(OOxOOOOO)TS7 MS_Class=20
Mass test: TS0(OOxOOOOO)TS7 MS_Class=21
Mass test: TS0(OOxOOOOO)TS7 MS_Class=22
Mass test: TS0(OOxOOOOO)TS7 MS_Class=23
Mass test: TS0(OOxOOOOO)TS7 MS_Class=24
Mass test: TS0(OOxOOOOO)TS7 MS_Class=25
Mass test: TS0(OOxOOOOO)TS7 MS_Class=26
Mass test: TS0(OOxOOOOO)TS7 MS_Class=27
Mass test: TS0(OOxOOOOO)TS7 MS_Class=28
Mass test: TS0(OOxOOOOO)TS7 MS_Class=29
Mass test: TS0(OOxOOOOO)TS7 MS_Class=30
Mass test: TS0(OOxOOOOO)TS7 MS_Class=31
Mass test: TS0(OOxOOOOO)TS7 MS_Class=32
Mass test: TS0(OOxOOOOO)TS7 MS_Class=33
Mass test: TS0(OOxOOOOO)TS7 MS_Class=34
Mass test: TS0(OOxOOOOO)TS7 MS_Class=35
Mass test: TS0(OOxOOOOO)TS7 MS_Class=36
Mass test: TS0(OOxOOOOO)TS7 MS_Class=37
Mass test: TS0(OOxOOOOO)TS7 MS_Class=38
Mass test: TS0(OOxOOOOO)TS7 MS_Class=39
Mass test: TS0(OOxOOOOO)TS7 MS_Class=40
Mass test: TS0(OOxOOOOO)TS7 MS_Class=41
Mass test: TS0(OOxOOOOO)TS7 MS_Class=42
Mass test: TS0(OOxOOOOO)TS7 MS_Class=43
Mass test: TS0(OOxOOOOO)TS7 MS_Class=44
Mass test: TS0(OOxOOOOO)TS7 MS_Class=45
Mass test: TS0(OOOxxxxx)TS7 MS_Class=0
Mass test: TS0(OOOxxxxx)TS7 MS_Class=1
Mass test: TS0(OOOxxxxx)TS7 MS_Class=2
Mass test: TS0(OOOxxxxx)TS7 MS_Class=3
Mass test: TS0(OOOxxxxx)TS7 MS_Class=4
Mass test: TS0(OOOxxxxx)TS7 MS_Class=5
Mass test: TS0(OOOxxxxx)TS7 MS_Class=6
Mass test: TS0(OOOxxxxx)TS7 MS_Class=7
Mass test: TS0(OOOxxxxx)TS7 MS_Class=8
Mass test: TS0(OOOxxxxx)TS7 MS_Class=9
Mass test: TS0(OOOxxxxx)TS7 MS_Class=10
Mass test: TS0(OOOxxxxx)TS7 MS_Class=11
Mass test: TS0(OOOxxxxx)TS7 MS_Class=12
Mass test: TS0(OOOxxxxx)TS7 MS_Class=13
Mass test: TS0(OOOxxxxx)TS7 MS_Class=14
Mass test: TS0(OOOxxxxx)TS7 MS_Class=15
Mass test: TS0(OOOxxxxx)TS7 MS_Class=16
Mass test: TS0(OOOxxxxx)TS7 MS_Class=17
Mass test: TS0(OOOxxxxx)TS7 MS_Class=18
Mass test: TS0(OOOxxxxx)TS7 MS_Class=19
Mass test: TS0(OOOxxxxx)TS7 MS_Class=20
Mass test: TS0(OOOxxxxx)TS7 MS_Class=21
Mass test: TS0(OOOxxxxx)TS7 MS_Class=22
Mass test: TS0(OOOxxxxx)TS7 MS_Class=23
Mass test: TS0(OOOxxxxx)TS7 MS_Class=24
Mass test: TS0(OOOxxxxx)TS7 MS_Class=25
Mass test: TS0(OOOxxxxx)TS7 MS_Class=26
Mass test: TS0(OOOxxxxx)TS7 MS_Class=27
Mass test: TS0(OOOxxxxx)TS7 MS_Class=28
Mass test: TS0(OOOxxxxx)TS7 MS_Class=29
Mass test: TS0(OOOxxxxx)TS7 MS_Class=30
Mass test: TS0(OOOxxxxx)TS7 MS_Class=31
Mass test: TS0(OOOxxxxx)TS7 MS_Class=32
Mass test: TS0(OOOxxxxx)TS7 MS_Class=33
Mass test: TS0(OOOxxxxx)TS7 MS_Class=34
Mass test: TS0(OOOxxxxx)TS7 MS_Class=35
Mass test: TS0(OOOxxxxx)TS7 MS_Class=36
Mass test: TS0(OOOxxxxx)TS7 MS_Class=37
Mass test: TS0(OOOxxxxx)TS7 MS_Class=38
Mass test: TS0(OOOxxxxx)TS7 MS_Class=39
Mass test: TS0(OOOxxxxx)TS7 MS_Class=40
Mass test: TS0(OOOxxxxx)TS7 MS_Class=41
Mass test: TS0(OOOxxxxx)TS7 MS_Class=42
Mass test: TS0(OOOxxxxx)TS7 MS_Class=43
Mass test: TS0(OOOxxxxx)TS7 MS_Class=44
Mass test: TS0(OOOxxxxx)TS7 MS_Class=45
Mass test: TS0(OOOxxxxO)TS7 MS_Class=0
Mass test: TS0(OOOxxxxO)TS7 MS_Class=1
Mass test: TS0(OOOxxxxO)TS7 MS_Class=2
Mass test: TS0(OOOxxxxO)TS7 MS_Class=3
Mass test: TS0(OOOxxxxO)TS7 MS_Class=4
Mass test: TS0(OOOxxxxO)TS7 MS_Class=5
Mass test: TS0(OOOxxxxO)TS7 MS_Class=6
Mass test: TS0(OOOxxxxO)TS7 MS_Class=7
Mass test: TS0(OOOxxxxO)TS7 MS_Class=8
Mass test: TS0(OOOxxxxO)TS7 MS_Class=9
Mass test: TS0(OOOxxxxO)TS7 MS_Class=10
Mass test: TS0(OOOxxxxO)TS7 MS_Class=11
Mass test: TS0(OOOxxxxO)TS7 MS_Class=12
Mass test: TS0(OOOxxxxO)TS7 MS_Class=13
Mass test: TS0(OOOxxxxO)TS7 MS_Class=14
Mass test: TS0(OOOxxxxO)TS7 MS_Class=15
Mass test: TS0(OOOxxxxO)TS7 MS_Class=16
Mass test: TS0(OOOxxxxO)TS7 MS_Class=17
Mass test: TS0(OOOxxxxO)TS7 MS_Class=18
Mass test: TS0(OOOxxxxO)TS7 MS_Class=19
Mass test: TS0(OOOxxxxO)TS7 MS_Class=20
Mass test: TS0(OOOxxxxO)TS7 MS_Class=21
Mass test: TS0(OOOxxxxO)TS7 MS_Class=22
Mass test: TS0(OOOxxxxO)TS7 MS_Class=23
Mass test: TS0(OOOxxxxO)TS7 MS_Class=24
Mass test: TS0(OOOxxxxO)TS7 MS_Class=25
Mass test: TS0(OOOxxxxO)TS7 MS_Class=26
Mass test: TS0(OOOxxxxO)TS7 MS_Class=27
Mass test: TS0(OOOxxxxO)TS7 MS_Class=28
Mass test: TS0(OOOxxxxO)TS7 MS_Class=29
Mass test: TS0(OOOxxxxO)TS7 MS_Class=30
Mass test: TS0(OOOxxxxO)TS7 MS_Class=31
Mass test: TS0(OOOxxxxO)TS7 MS_Class=32
Mass test: TS0(OOOxxxxO)TS7 MS_Class=33
Mass test: TS0(OOOxxxxO)TS7 MS_Class=34
Mass test: TS0(OOOxxxxO)TS7 MS_Class=35
Mass test: TS0(OOOxxxxO)TS7 MS_Class=36
Mass test: TS0(OOOxxxxO)TS7 MS_Class=37
Mass test: TS0(OOOxxxxO)TS7 MS_Class=38
Mass test: TS0(OOOxxxxO)TS7 MS_Class=39
Mass test: TS0(OOOxxxxO)TS7 MS_Class=40
Mass test: TS0(OOOxxxxO)TS7 MS_Class=41
Mass test: TS0(OOOxxxxO)TS7 MS_Class=42
Mass test: TS0(OOOxxxxO)TS7 MS_Class=43
Mass test: TS0(OOOxxxxO)TS7 MS_Class=44
Mass test: TS0(OOOxxxxO)TS7 MS_Class=45
Mass test: TS0(OOOxxxOx)TS7 MS_Class=0
Mass test: TS0(OOOxxxOx)TS7 MS_Class=1
Mass test: TS0(OOOxxxOx)TS7 MS_Class=2
Mass test: TS0(OOOxxxOx)TS7 MS_Class=3
Mass test: TS0(OOOxxxOx)TS7 MS_Class=4
Mass test: TS0(OOOxxxOx)TS7 MS_Class=5
Mass test: TS0(OOOxxxOx)TS7 MS_Class=6
Mass test: TS0(OOOxxxOx)TS7 MS_Class=7
Mass test: TS0(OOOxxxOx)TS7 MS_Class=8
Mass test: TS0(OOOxxxOx)TS7 MS_Class=9
Mass test: TS0(OOOxxxOx)TS7 MS_Class=10
Mass test: TS0(OOOxxxOx)TS7 MS_Class=11
Mass test: TS0(OOOxxxOx)TS7 MS_Class=12
Mass test: TS0(OOOxxxOx)TS7 MS_Class=13
Mass test: TS0(OOOxxxOx)TS7 MS_Class=14
Mass test: TS0(OOOxxxOx)TS7 MS_Class=15
Mass test: TS0(OOOxxxOx)TS7 MS_Class=16
Mass test: TS0(OOOxxxOx)TS7 MS_Class=17
Mass test: TS0(OOOxxxOx)TS7 MS_Class=18
Mass test: TS0(OOOxxxOx)TS7 MS_Class=19
Mass test: TS0(OOOxxxOx)TS7 MS_Class=20
Mass test: TS0(OOOxxxOx)TS7 MS_Class=21
Mass test: TS0(OOOxxxOx)TS7 MS_Class=22
Mass test: TS0(OOOxxxOx)TS7 MS_Class=23
Mass test: TS0(OOOxxxOx)TS7 MS_Class=24
Mass test: TS0(OOOxxxOx)TS7 MS_Class=25
Mass test: TS0(OOOxxxOx)TS7 MS_Class=26
Mass test: TS0(OOOxxxOx)TS7 MS_Class=27
Mass test: TS0(OOOxxxOx)TS7 MS_Class=28
Mass test: TS0(OOOxxxOx)TS7 MS_Class=29
Mass test: TS0(OOOxxxOx)TS7 MS_Class=30
Mass test: TS0(OOOxxxOx)TS7 MS_Class=31
Mass test: TS0(OOOxxxOx)TS7 MS_Class=32
Mass test: TS0(OOOxxxOx)TS7 MS_Class=33
Mass test: TS0(OOOxxxOx)TS7 MS_Class=34
Mass test: TS0(OOOxxxOx)TS7 MS_Class=35
Mass test: TS0(OOOxxxOx)TS7 MS_Class=36
Mass test: TS0(OOOxxxOx)TS7 MS_Class=37
Mass test: TS0(OOOxxxOx)TS7 MS_Class=38
Mass test: TS0(OOOxxxOx)TS7 MS_Class=39
Mass test: TS0(OOOxxxOx)TS7 MS_Class=40
Mass test: TS0(OOOxxxOx)TS7 MS_Class=41
Mass test: TS0(OOOxxxOx)TS7 MS_Class=42
Mass test: TS0(OOOxxxOx)TS7 MS_Class=43
Mass test: TS0(OOOxxxOx)TS7 MS_Class=44
Mass test: TS0(OOOxxxOx)TS7 MS_Class=45
Mass test: TS0(OOOxxxOO)TS7 MS_Class=0
Mass test: TS0(OOOxxxOO)TS7 MS_Class=1
Mass test: TS0(OOOxxxOO)TS7 MS_Class=2
Mass test: TS0(OOOxxxOO)TS7 MS_Class=3
Mass test: TS0(OOOxxxOO)TS7 MS_Class=4
Mass test: TS0(OOOxxxOO)TS7 MS_Class=5
Mass test: TS0(OOOxxxOO)TS7 MS_Class=6
Mass test: TS0(OOOxxxOO)TS7 MS_Class=7
Mass test: TS0(OOOxxxOO)TS7 MS_Class=8
Mass test: TS0(OOOxxxOO)TS7 MS_Class=9
Mass test: TS0(OOOxxxOO)TS7 MS_Class=10
Mass test: TS0(OOOxxxOO)TS7 MS_Class=11
Mass test: TS0(OOOxxxOO)TS7 MS_Class=12
Mass test: TS0(OOOxxxOO)TS7 MS_Class=13
Mass test: TS0(OOOxxxOO)TS7 MS_Class=14
Mass test: TS0(OOOxxxOO)TS7 MS_Class=15
Mass test: TS0(OOOxxxOO)TS7 MS_Class=16
Mass test: TS0(OOOxxxOO)TS7 MS_Class=17
Mass test: TS0(OOOxxxOO)TS7 MS_Class=18
Mass test: TS0(OOOxxxOO)TS7 MS_Class=19
Mass test: TS0(OOOxxxOO)TS7 MS_Class=20
Mass test: TS0(OOOxxxOO)TS7 MS_Class=21
Mass test: TS0(OOOxxxOO)TS7 MS_Class=22
Mass test: TS0(OOOxxxOO)TS7 MS_Class=23
Mass test: TS0(OOOxxxOO)TS7 MS_Class=24
Mass test: TS0(OOOxxxOO)TS7 MS_Class=25
Mass test: TS0(OOOxxxOO)TS7 MS_Class=26
Mass test: TS0(OOOxxxOO)TS7 MS_Class=27
Mass test: TS0(OOOxxxOO)TS7 MS_Class=28
Mass test: TS0(OOOxxxOO)TS7 MS_Class=29
Mass test: TS0(OOOxxxOO)TS7 MS_Class=30
Mass test: TS0(OOOxxxOO)TS7 MS_Class=31
Mass test: TS0(OOOxxxOO)TS7 MS_Class=32
Mass test: TS0(OOOxxxOO)TS7 MS_Class=33
Mass test: TS0(OOOxxxOO)TS7 MS_Class=34
Mass test: TS0(OOOxxxOO)TS7 MS_Class=35
Mass test: TS0(OOOxxxOO)TS7 MS_Class=36
Mass test: TS0(OOOxxxOO)TS7 MS_Class=37
Mass test: TS0(OOOxxxOO)TS7 MS_Class=38
Mass test: TS0(OOOxxxOO)TS7 MS_Class=39
Mass test: TS0(OOOxxxOO)TS7 MS_Class=40
Mass test: TS0(OOOxxxOO)TS7 MS_Class=41
Mass test: TS0(OOOxxxOO)TS7 MS_Class=42
Mass test: TS0(OOOxxxOO)TS7 MS_Class=43
Mass test: TS0(OOOxxxOO)TS7 MS_Class=44
Mass test: TS0(OOOxxxOO)TS7 MS_Class=45
Mass test: TS0(OOOxxOxx)TS7 MS_Class=0
Mass test: TS0(OOOxxOxx)TS7 MS_Class=1
Mass test: TS0(OOOxxOxx)TS7 MS_Class=2
Mass test: TS0(OOOxxOxx)TS7 MS_Class=3
Mass test: TS0(OOOxxOxx)TS7 MS_Class=4
Mass test: TS0(OOOxxOxx)TS7 MS_Class=5
Mass test: TS0(OOOxxOxx)TS7 MS_Class=6
Mass test: TS0(OOOxxOxx)TS7 MS_Class=7
Mass test: TS0(OOOxxOxx)TS7 MS_Class=8
Mass test: TS0(OOOxxOxx)TS7 MS_Class=9
Mass test: TS0(OOOxxOxx)TS7 MS_Class=10
Mass test: TS0(OOOxxOxx)TS7 MS_Class=11
Mass test: TS0(OOOxxOxx)TS7 MS_Class=12
Mass test: TS0(OOOxxOxx)TS7 MS_Class=13
Mass test: TS0(OOOxxOxx)TS7 MS_Class=14
Mass test: TS0(OOOxxOxx)TS7 MS_Class=15
Mass test: TS0(OOOxxOxx)TS7 MS_Class=16
Mass test: TS0(OOOxxOxx)TS7 MS_Class=17
Mass test: TS0(OOOxxOxx)TS7 MS_Class=18
Mass test: TS0(OOOxxOxx)TS7 MS_Class=19
Mass test: TS0(OOOxxOxx)TS7 MS_Class=20
Mass test: TS0(OOOxxOxx)TS7 MS_Class=21
Mass test: TS0(OOOxxOxx)TS7 MS_Class=22
Mass test: TS0(OOOxxOxx)TS7 MS_Class=23
Mass test: TS0(OOOxxOxx)TS7 MS_Class=24
Mass test: TS0(OOOxxOxx)TS7 MS_Class=25
Mass test: TS0(OOOxxOxx)TS7 MS_Class=26
Mass test: TS0(OOOxxOxx)TS7 MS_Class=27
Mass test: TS0(OOOxxOxx)TS7 MS_Class=28
Mass test: TS0(OOOxxOxx)TS7 MS_Class=29
Mass test: TS0(OOOxxOxx)TS7 MS_Class=30
Mass test: TS0(OOOxxOxx)TS7 MS_Class=31
Mass test: TS0(OOOxxOxx)TS7 MS_Class=32
Mass test: TS0(OOOxxOxx)TS7 MS_Class=33
Mass test: TS0(OOOxxOxx)TS7 MS_Class=34
Mass test: TS0(OOOxxOxx)TS7 MS_Class=35
Mass test: TS0(OOOxxOxx)TS7 MS_Class=36
Mass test: TS0(OOOxxOxx)TS7 MS_Class=37
Mass test: TS0(OOOxxOxx)TS7 MS_Class=38
Mass test: TS0(OOOxxOxx)TS7 MS_Class=39
Mass test: TS0(OOOxxOxx)TS7 MS_Class=40
Mass test: TS0(OOOxxOxx)TS7 MS_Class=41
Mass test: TS0(OOOxxOxx)TS7 MS_Class=42
Mass test: TS0(OOOxxOxx)TS7 MS_Class=43
Mass test: TS0(OOOxxOxx)TS7 MS_Class=44
Mass test: TS0(OOOxxOxx)TS7 MS_Class=45
Mass test: TS0(OOOxxOxO)TS7 MS_Class=0
Mass test: TS0(OOOxxOxO)TS7 MS_Class=1
Mass test: TS0(OOOxxOxO)TS7 MS_Class=2
Mass test: TS0(OOOxxOxO)TS7 MS_Class=3
Mass test: TS0(OOOxxOxO)TS7 MS_Class=4
Mass test: TS0(OOOxxOxO)TS7 MS_Class=5
Mass test: TS0(OOOxxOxO)TS7 MS_Class=6
Mass test: TS0(OOOxxOxO)TS7 MS_Class=7
Mass test: TS0(OOOxxOxO)TS7 MS_Class=8
Mass test: TS0(OOOxxOxO)TS7 MS_Class=9
Mass test: TS0(OOOxxOxO)TS7 MS_Class=10
Mass test: TS0(OOOxxOxO)TS7 MS_Class=11
Mass test: TS0(OOOxxOxO)TS7 MS_Class=12
Mass test: TS0(OOOxxOxO)TS7 MS_Class=13
Mass test: TS0(OOOxxOxO)TS7 MS_Class=14
Mass test: TS0(OOOxxOxO)TS7 MS_Class=15
Mass test: TS0(OOOxxOxO)TS7 MS_Class=16
Mass test: TS0(OOOxxOxO)TS7 MS_Class=17
Mass test: TS0(OOOxxOxO)TS7 MS_Class=18
Mass test: TS0(OOOxxOxO)TS7 MS_Class=19
Mass test: TS0(OOOxxOxO)TS7 MS_Class=20
Mass test: TS0(OOOxxOxO)TS7 MS_Class=21
Mass test: TS0(OOOxxOxO)TS7 MS_Class=22
Mass test: TS0(OOOxxOxO)TS7 MS_Class=23
Mass test: TS0(OOOxxOxO)TS7 MS_Class=24
Mass test: TS0(OOOxxOxO)TS7 MS_Class=25
Mass test: TS0(OOOxxOxO)TS7 MS_Class=26
Mass test: TS0(OOOxxOxO)TS7 MS_Class=27
Mass test: TS0(OOOxxOxO)TS7 MS_Class=28
Mass test: TS0(OOOxxOxO)TS7 MS_Class=29
Mass test: TS0(OOOxxOxO)TS7 MS_Class=30
Mass test: TS0(OOOxxOxO)TS7 MS_Class=31
Mass test: TS0(OOOxxOxO)TS7 MS_Class=32
Mass test: TS0(OOOxxOxO)TS7 MS_Class=33
Mass test: TS0(OOOxxOxO)TS7 MS_Class=34
Mass test: TS0(OOOxxOxO)TS7 MS_Class=35
Mass test: TS0(OOOxxOxO)TS7 MS_Class=36
Mass test: TS0(OOOxxOxO)TS7 MS_Class=37
Mass test: TS0(OOOxxOxO)TS7 MS_Class=38
Mass test: TS0(OOOxxOxO)TS7 MS_Class=39
Mass test: TS0(OOOxxOxO)TS7 MS_Class=40
Mass test: TS0(OOOxxOxO)TS7 MS_Class=41
Mass test: TS0(OOOxxOxO)TS7 MS_Class=42
Mass test: TS0(OOOxxOxO)TS7 MS_Class=43
Mass test: TS0(OOOxxOxO)TS7 MS_Class=44
Mass test: TS0(OOOxxOxO)TS7 MS_Class=45
Mass test: TS0(OOOxxOOx)TS7 MS_Class=0
Mass test: TS0(OOOxxOOx)TS7 MS_Class=1
Mass test: TS0(OOOxxOOx)TS7 MS_Class=2
Mass test: TS0(OOOxxOOx)TS7 MS_Class=3
Mass test: TS0(OOOxxOOx)TS7 MS_Class=4
Mass test: TS0(OOOxxOOx)TS7 MS_Class=5
Mass test: TS0(OOOxxOOx)TS7 MS_Class=6
Mass test: TS0(OOOxxOOx)TS7 MS_Class=7
Mass test: TS0(OOOxxOOx)TS7 MS_Class=8
Mass test: TS0(OOOxxOOx)TS7 MS_Class=9
Mass test: TS0(OOOxxOOx)TS7 MS_Class=10
Mass test: TS0(OOOxxOOx)TS7 MS_Class=11
Mass test: TS0(OOOxxOOx)TS7 MS_Class=12
Mass test: TS0(OOOxxOOx)TS7 MS_Class=13
Mass test: TS0(OOOxxOOx)TS7 MS_Class=14
Mass test: TS0(OOOxxOOx)TS7 MS_Class=15
Mass test: TS0(OOOxxOOx)TS7 MS_Class=16
Mass test: TS0(OOOxxOOx)TS7 MS_Class=17
Mass test: TS0(OOOxxOOx)TS7 MS_Class=18
Mass test: TS0(OOOxxOOx)TS7 MS_Class=19
Mass test: TS0(OOOxxOOx)TS7 MS_Class=20
Mass test: TS0(OOOxxOOx)TS7 MS_Class=21
Mass test: TS0(OOOxxOOx)TS7 MS_Class=22
Mass test: TS0(OOOxxOOx)TS7 MS_Class=23
Mass test: TS0(OOOxxOOx)TS7 MS_Class=24
Mass test: TS0(OOOxxOOx)TS7 MS_Class=25
Mass test: TS0(OOOxxOOx)TS7 MS_Class=26
Mass test: TS0(OOOxxOOx)TS7 MS_Class=27
Mass test: TS0(OOOxxOOx)TS7 MS_Class=28
Mass test: TS0(OOOxxOOx)TS7 MS_Class=29
Mass test: TS0(OOOxxOOx)TS7 MS_Class=30
Mass test: TS0(OOOxxOOx)TS7 MS_Class=31
Mass test: TS0(OOOxxOOx)TS7 MS_Class=32
Mass test: TS0(OOOxxOOx)TS7 MS_Class=33
Mass test: TS0(OOOxxOOx)TS7 MS_Class=34
Mass test: TS0(OOOxxOOx)TS7 MS_Class=35
Mass test: TS0(OOOxxOOx)TS7 MS_Class=36
Mass test: TS0(OOOxxOOx)TS7 MS_Class=37
Mass test: TS0(OOOxxOOx)TS7 MS_Class=38
Mass test: TS0(OOOxxOOx)TS7 MS_Class=39
Mass test: TS0(OOOxxOOx)TS7 MS_Class=40
Mass test: TS0(OOOxxOOx)TS7 MS_Class=41
Mass test: TS0(OOOxxOOx)TS7 MS_Class=42
Mass test: TS0(OOOxxOOx)TS7 MS_Class=43
Mass test: TS0(OOOxxOOx)TS7 MS_Class=44
Mass test: TS0(OOOxxOOx)TS7 MS_Class=45
Mass test: TS0(OOOxxOOO)TS7 MS_Class=0
Mass test: TS0(OOOxxOOO)TS7 MS_Class=1
Mass test: TS0(OOOxxOOO)TS7 MS_Class=2
Mass test: TS0(OOOxxOOO)TS7 MS_Class=3
Mass test: TS0(OOOxxOOO)TS7 MS_Class=4
Mass test: TS0(OOOxxOOO)TS7 MS_Class=5
Mass test: TS0(OOOxxOOO)TS7 MS_Class=6
Mass test: TS0(OOOxxOOO)TS7 MS_Class=7
Mass test: TS0(OOOxxOOO)TS7 MS_Class=8
Mass test: TS0(OOOxxOOO)TS7 MS_Class=9
Mass test: TS0(OOOxxOOO)TS7 MS_Class=10
Mass test: TS0(OOOxxOOO)TS7 MS_Class=11
Mass test: TS0(OOOxxOOO)TS7 MS_Class=12
Mass test: TS0(OOOxxOOO)TS7 MS_Class=13
Mass test: TS0(OOOxxOOO)TS7 MS_Class=14
Mass test: TS0(OOOxxOOO)TS7 MS_Class=15
Mass test: TS0(OOOxxOOO)TS7 MS_Class=16
Mass test: TS0(OOOxxOOO)TS7 MS_Class=17
Mass test: TS0(OOOxxOOO)TS7 MS_Class=18
Mass test: TS0(OOOxxOOO)TS7 MS_Class=19
Mass test: TS0(OOOxxOOO)TS7 MS_Class=20
Mass test: TS0(OOOxxOOO)TS7 MS_Class=21
Mass test: TS0(OOOxxOOO)TS7 MS_Class=22
Mass test: TS0(OOOxxOOO)TS7 MS_Class=23
Mass test: TS0(OOOxxOOO)TS7 MS_Class=24
Mass test: TS0(OOOxxOOO)TS7 MS_Class=25
Mass test: TS0(OOOxxOOO)TS7 MS_Class=26
Mass test: TS0(OOOxxOOO)TS7 MS_Class=27
Mass test: TS0(OOOxxOOO)TS7 MS_Class=28
Mass test: TS0(OOOxxOOO)TS7 MS_Class=29
Mass test: TS0(OOOxxOOO)TS7 MS_Class=30
Mass test: TS0(OOOxxOOO)TS7 MS_Class=31
Mass test: TS0(OOOxxOOO)TS7 MS_Class=32
Mass test: TS0(OOOxxOOO)TS7 MS_Class=33
Mass test: TS0(OOOxxOOO)TS7 MS_Class=34
Mass test: TS0(OOOxxOOO)TS7 MS_Class=35
Mass test: TS0(OOOxxOOO)TS7 MS_Class=36
Mass test: TS0(OOOxxOOO)TS7 MS_Class=37
Mass test: TS0(OOOxxOOO)TS7 MS_Class=38
Mass test: TS0(OOOxxOOO)TS7 MS_Class=39
Mass test: TS0(OOOxxOOO)TS7 MS_Class=40
Mass test: TS0(OOOxxOOO)TS7 MS_Class=41
Mass test: TS0(OOOxxOOO)TS7 MS_Class=42
Mass test: TS0(OOOxxOOO)TS7 MS_Class=43
Mass test: TS0(OOOxxOOO)TS7 MS_Class=44
Mass test: TS0(OOOxxOOO)TS7 MS_Class=45
Mass test: TS0(OOOxOxxx)TS7 MS_Class=0
Mass test: TS0(OOOxOxxx)TS7 MS_Class=1
Mass test: TS0(OOOxOxxx)TS7 MS_Class=2
Mass test: TS0(OOOxOxxx)TS7 MS_Class=3
Mass test: TS0(OOOxOxxx)TS7 MS_Class=4
Mass test: TS0(OOOxOxxx)TS7 MS_Class=5
Mass test: TS0(OOOxOxxx)TS7 MS_Class=6
Mass test: TS0(OOOxOxxx)TS7 MS_Class=7
Mass test: TS0(OOOxOxxx)TS7 MS_Class=8
Mass test: TS0(OOOxOxxx)TS7 MS_Class=9
Mass test: TS0(OOOxOxxx)TS7 MS_Class=10
Mass test: TS0(OOOxOxxx)TS7 MS_Class=11
Mass test: TS0(OOOxOxxx)TS7 MS_Class=12
Mass test: TS0(OOOxOxxx)TS7 MS_Class=13
Mass test: TS0(OOOxOxxx)TS7 MS_Class=14
Mass test: TS0(OOOxOxxx)TS7 MS_Class=15
Mass test: TS0(OOOxOxxx)TS7 MS_Class=16
Mass test: TS0(OOOxOxxx)TS7 MS_Class=17
Mass test: TS0(OOOxOxxx)TS7 MS_Class=18
Mass test: TS0(OOOxOxxx)TS7 MS_Class=19
Mass test: TS0(OOOxOxxx)TS7 MS_Class=20
Mass test: TS0(OOOxOxxx)TS7 MS_Class=21
Mass test: TS0(OOOxOxxx)TS7 MS_Class=22
Mass test: TS0(OOOxOxxx)TS7 MS_Class=23
Mass test: TS0(OOOxOxxx)TS7 MS_Class=24
Mass test: TS0(OOOxOxxx)TS7 MS_Class=25
Mass test: TS0(OOOxOxxx)TS7 MS_Class=26
Mass test: TS0(OOOxOxxx)TS7 MS_Class=27
Mass test: TS0(OOOxOxxx)TS7 MS_Class=28
Mass test: TS0(OOOxOxxx)TS7 MS_Class=29
Mass test: TS0(OOOxOxxx)TS7 MS_Class=30
Mass test: TS0(OOOxOxxx)TS7 MS_Class=31
Mass test: TS0(OOOxOxxx)TS7 MS_Class=32
Mass test: TS0(OOOxOxxx)TS7 MS_Class=33
Mass test: TS0(OOOxOxxx)TS7 MS_Class=34
Mass test: TS0(OOOxOxxx)TS7 MS_Class=35
Mass test: TS0(OOOxOxxx)TS7 MS_Class=36
Mass test: TS0(OOOxOxxx)TS7 MS_Class=37
Mass test: TS0(OOOxOxxx)TS7 MS_Class=38
Mass test: TS0(OOOxOxxx)TS7 MS_Class=39
Mass test: TS0(OOOxOxxx)TS7 MS_Class=40
Mass test: TS0(OOOxOxxx)TS7 MS_Class=41
Mass test: TS0(OOOxOxxx)TS7 MS_Class=42
Mass test: TS0(OOOxOxxx)TS7 MS_Class=43
Mass test: TS0(OOOxOxxx)TS7 MS_Class=44
Mass test: TS0(OOOxOxxx)TS7 MS_Class=45
Mass test: TS0(OOOxOxxO)TS7 MS_Class=0
Mass test: TS0(OOOxOxxO)TS7 MS_Class=1
Mass test: TS0(OOOxOxxO)TS7 MS_Class=2
Mass test: TS0(OOOxOxxO)TS7 MS_Class=3
Mass test: TS0(OOOxOxxO)TS7 MS_Class=4
Mass test: TS0(OOOxOxxO)TS7 MS_Class=5
Mass test: TS0(OOOxOxxO)TS7 MS_Class=6
Mass test: TS0(OOOxOxxO)TS7 MS_Class=7
Mass test: TS0(OOOxOxxO)TS7 MS_Class=8
Mass test: TS0(OOOxOxxO)TS7 MS_Class=9
Mass test: TS0(OOOxOxxO)TS7 MS_Class=10
Mass test: TS0(OOOxOxxO)TS7 MS_Class=11
Mass test: TS0(OOOxOxxO)TS7 MS_Class=12
Mass test: TS0(OOOxOxxO)TS7 MS_Class=13
Mass test: TS0(OOOxOxxO)TS7 MS_Class=14
Mass test: TS0(OOOxOxxO)TS7 MS_Class=15
Mass test: TS0(OOOxOxxO)TS7 MS_Class=16
Mass test: TS0(OOOxOxxO)TS7 MS_Class=17
Mass test: TS0(OOOxOxxO)TS7 MS_Class=18
Mass test: TS0(OOOxOxxO)TS7 MS_Class=19
Mass test: TS0(OOOxOxxO)TS7 MS_Class=20
Mass test: TS0(OOOxOxxO)TS7 MS_Class=21
Mass test: TS0(OOOxOxxO)TS7 MS_Class=22
Mass test: TS0(OOOxOxxO)TS7 MS_Class=23
Mass test: TS0(OOOxOxxO)TS7 MS_Class=24
Mass test: TS0(OOOxOxxO)TS7 MS_Class=25
Mass test: TS0(OOOxOxxO)TS7 MS_Class=26
Mass test: TS0(OOOxOxxO)TS7 MS_Class=27
Mass test: TS0(OOOxOxxO)TS7 MS_Class=28
Mass test: TS0(OOOxOxxO)TS7 MS_Class=29
Mass test: TS0(OOOxOxxO)TS7 MS_Class=30
Mass test: TS0(OOOxOxxO)TS7 MS_Class=31
Mass test: TS0(OOOxOxxO)TS7 MS_Class=32
Mass test: TS0(OOOxOxxO)TS7 MS_Class=33
Mass test: TS0(OOOxOxxO)TS7 MS_Class=34
Mass test: TS0(OOOxOxxO)TS7 MS_Class=35
Mass test: TS0(OOOxOxxO)TS7 MS_Class=36
Mass test: TS0(OOOxOxxO)TS7 MS_Class=37
Mass test: TS0(OOOxOxxO)TS7 MS_Class=38
Mass test: TS0(OOOxOxxO)TS7 MS_Class=39
Mass test: TS0(OOOxOxxO)TS7 MS_Class=40
Mass test: TS0(OOOxOxxO)TS7 MS_Class=41
Mass test: TS0(OOOxOxxO)TS7 MS_Class=42
Mass test: TS0(OOOxOxxO)TS7 MS_Class=43
Mass test: TS0(OOOxOxxO)TS7 MS_Class=44
Mass test: TS0(OOOxOxxO)TS7 MS_Class=45
Mass test: TS0(OOOxOxOx)TS7 MS_Class=0
Mass test: TS0(OOOxOxOx)TS7 MS_Class=1
Mass test: TS0(OOOxOxOx)TS7 MS_Class=2
Mass test: TS0(OOOxOxOx)TS7 MS_Class=3
Mass test: TS0(OOOxOxOx)TS7 MS_Class=4
Mass test: TS0(OOOxOxOx)TS7 MS_Class=5
Mass test: TS0(OOOxOxOx)TS7 MS_Class=6
Mass test: TS0(OOOxOxOx)TS7 MS_Class=7
Mass test: TS0(OOOxOxOx)TS7 MS_Class=8
Mass test: TS0(OOOxOxOx)TS7 MS_Class=9
Mass test: TS0(OOOxOxOx)TS7 MS_Class=10
Mass test: TS0(OOOxOxOx)TS7 MS_Class=11
Mass test: TS0(OOOxOxOx)TS7 MS_Class=12
Mass test: TS0(OOOxOxOx)TS7 MS_Class=13
Mass test: TS0(OOOxOxOx)TS7 MS_Class=14
Mass test: TS0(OOOxOxOx)TS7 MS_Class=15
Mass test: TS0(OOOxOxOx)TS7 MS_Class=16
Mass test: TS0(OOOxOxOx)TS7 MS_Class=17
Mass test: TS0(OOOxOxOx)TS7 MS_Class=18
Mass test: TS0(OOOxOxOx)TS7 MS_Class=19
Mass test: TS0(OOOxOxOx)TS7 MS_Class=20
Mass test: TS0(OOOxOxOx)TS7 MS_Class=21
Mass test: TS0(OOOxOxOx)TS7 MS_Class=22
Mass test: TS0(OOOxOxOx)TS7 MS_Class=23
Mass test: TS0(OOOxOxOx)TS7 MS_Class=24
Mass test: TS0(OOOxOxOx)TS7 MS_Class=25
Mass test: TS0(OOOxOxOx)TS7 MS_Class=26
Mass test: TS0(OOOxOxOx)TS7 MS_Class=27
Mass test: TS0(OOOxOxOx)TS7 MS_Class=28
Mass test: TS0(OOOxOxOx)TS7 MS_Class=29
Mass test: TS0(OOOxOxOx)TS7 MS_Class=30
Mass test: TS0(OOOxOxOx)TS7 MS_Class=31
Mass test: TS0(OOOxOxOx)TS7 MS_Class=32
Mass test: TS0(OOOxOxOx)TS7 MS_Class=33
Mass test: TS0(OOOxOxOx)TS7 MS_Class=34
Mass test: TS0(OOOxOxOx)TS7 MS_Class=35
Mass test: TS0(OOOxOxOx)TS7 MS_Class=36
Mass test: TS0(OOOxOxOx)TS7 MS_Class=37
Mass test: TS0(OOOxOxOx)TS7 MS_Class=38
Mass test: TS0(OOOxOxOx)TS7 MS_Class=39
Mass test: TS0(OOOxOxOx)TS7 MS_Class=40
Mass test: TS0(OOOxOxOx)TS7 MS_Class=41
Mass test: TS0(OOOxOxOx)TS7 MS_Class=42
Mass test: TS0(OOOxOxOx)TS7 MS_Class=43
Mass test: TS0(OOOxOxOx)TS7 MS_Class=44
Mass test: TS0(OOOxOxOx)TS7 MS_Class=45
Mass test: TS0(OOOxOxOO)TS7 MS_Class=0
Mass test: TS0(OOOxOxOO)TS7 MS_Class=1
Mass test: TS0(OOOxOxOO)TS7 MS_Class=2
Mass test: TS0(OOOxOxOO)TS7 MS_Class=3
Mass test: TS0(OOOxOxOO)TS7 MS_Class=4
Mass test: TS0(OOOxOxOO)TS7 MS_Class=5
Mass test: TS0(OOOxOxOO)TS7 MS_Class=6
Mass test: TS0(OOOxOxOO)TS7 MS_Class=7
Mass test: TS0(OOOxOxOO)TS7 MS_Class=8
Mass test: TS0(OOOxOxOO)TS7 MS_Class=9
Mass test: TS0(OOOxOxOO)TS7 MS_Class=10
Mass test: TS0(OOOxOxOO)TS7 MS_Class=11
Mass test: TS0(OOOxOxOO)TS7 MS_Class=12
Mass test: TS0(OOOxOxOO)TS7 MS_Class=13
Mass test: TS0(OOOxOxOO)TS7 MS_Class=14
Mass test: TS0(OOOxOxOO)TS7 MS_Class=15
Mass test: TS0(OOOxOxOO)TS7 MS_Class=16
Mass test: TS0(OOOxOxOO)TS7 MS_Class=17
Mass test: TS0(OOOxOxOO)TS7 MS_Class=18
Mass test: TS0(OOOxOxOO)TS7 MS_Class=19
Mass test: TS0(OOOxOxOO)TS7 MS_Class=20
Mass test: TS0(OOOxOxOO)TS7 MS_Class=21
Mass test: TS0(OOOxOxOO)TS7 MS_Class=22
Mass test: TS0(OOOxOxOO)TS7 MS_Class=23
Mass test: TS0(OOOxOxOO)TS7 MS_Class=24
Mass test: TS0(OOOxOxOO)TS7 MS_Class=25
Mass test: TS0(OOOxOxOO)TS7 MS_Class=26
Mass test: TS0(OOOxOxOO)TS7 MS_Class=27
Mass test: TS0(OOOxOxOO)TS7 MS_Class=28
Mass test: TS0(OOOxOxOO)TS7 MS_Class=29
Mass test: TS0(OOOxOxOO)TS7 MS_Class=30
Mass test: TS0(OOOxOxOO)TS7 MS_Class=31
Mass test: TS0(OOOxOxOO)TS7 MS_Class=32
Mass test: TS0(OOOxOxOO)TS7 MS_Class=33
Mass test: TS0(OOOxOxOO)TS7 MS_Class=34
Mass test: TS0(OOOxOxOO)TS7 MS_Class=35
Mass test: TS0(OOOxOxOO)TS7 MS_Class=36
Mass test: TS0(OOOxOxOO)TS7 MS_Class=37
Mass test: TS0(OOOxOxOO)TS7 MS_Class=38
Mass test: TS0(OOOxOxOO)TS7 MS_Class=39
Mass test: TS0(OOOxOxOO)TS7 MS_Class=40
Mass test: TS0(OOOxOxOO)TS7 MS_Class=41
Mass test: TS0(OOOxOxOO)TS7 MS_Class=42
Mass test: TS0(OOOxOxOO)TS7 MS_Class=43
Mass test: TS0(OOOxOxOO)TS7 MS_Class=44
Mass test: TS0(OOOxOxOO)TS7 MS_Class=45
Mass test: TS0(OOOxOOxx)TS7 MS_Class=0
Mass test: TS0(OOOxOOxx)TS7 MS_Class=1
Mass test: TS0(OOOxOOxx)TS7 MS_Class=2
Mass test: TS0(OOOxOOxx)TS7 MS_Class=3
Mass test: TS0(OOOxOOxx)TS7 MS_Class=4
Mass test: TS0(OOOxOOxx)TS7 MS_Class=5
Mass test: TS0(OOOxOOxx)TS7 MS_Class=6
Mass test: TS0(OOOxOOxx)TS7 MS_Class=7
Mass test: TS0(OOOxOOxx)TS7 MS_Class=8
Mass test: TS0(OOOxOOxx)TS7 MS_Class=9
Mass test: TS0(OOOxOOxx)TS7 MS_Class=10
Mass test: TS0(OOOxOOxx)TS7 MS_Class=11
Mass test: TS0(OOOxOOxx)TS7 MS_Class=12
Mass test: TS0(OOOxOOxx)TS7 MS_Class=13
Mass test: TS0(OOOxOOxx)TS7 MS_Class=14
Mass test: TS0(OOOxOOxx)TS7 MS_Class=15
Mass test: TS0(OOOxOOxx)TS7 MS_Class=16
Mass test: TS0(OOOxOOxx)TS7 MS_Class=17
Mass test: TS0(OOOxOOxx)TS7 MS_Class=18
Mass test: TS0(OOOxOOxx)TS7 MS_Class=19
Mass test: TS0(OOOxOOxx)TS7 MS_Class=20
Mass test: TS0(OOOxOOxx)TS7 MS_Class=21
Mass test: TS0(OOOxOOxx)TS7 MS_Class=22
Mass test: TS0(OOOxOOxx)TS7 MS_Class=23
Mass test: TS0(OOOxOOxx)TS7 MS_Class=24
Mass test: TS0(OOOxOOxx)TS7 MS_Class=25
Mass test: TS0(OOOxOOxx)TS7 MS_Class=26
Mass test: TS0(OOOxOOxx)TS7 MS_Class=27
Mass test: TS0(OOOxOOxx)TS7 MS_Class=28
Mass test: TS0(OOOxOOxx)TS7 MS_Class=29
Mass test: TS0(OOOxOOxx)TS7 MS_Class=30
Mass test: TS0(OOOxOOxx)TS7 MS_Class=31
Mass test: TS0(OOOxOOxx)TS7 MS_Class=32
Mass test: TS0(OOOxOOxx)TS7 MS_Class=33
Mass test: TS0(OOOxOOxx)TS7 MS_Class=34
Mass test: TS0(OOOxOOxx)TS7 MS_Class=35
Mass test: TS0(OOOxOOxx)TS7 MS_Class=36
Mass test: TS0(OOOxOOxx)TS7 MS_Class=37
Mass test: TS0(OOOxOOxx)TS7 MS_Class=38
Mass test: TS0(OOOxOOxx)TS7 MS_Class=39
Mass test: TS0(OOOxOOxx)TS7 MS_Class=40
Mass test: TS0(OOOxOOxx)TS7 MS_Class=41
Mass test: TS0(OOOxOOxx)TS7 MS_Class=42
Mass test: TS0(OOOxOOxx)TS7 MS_Class=43
Mass test: TS0(OOOxOOxx)TS7 MS_Class=44
Mass test: TS0(OOOxOOxx)TS7 MS_Class=45
Mass test: TS0(OOOxOOxO)TS7 MS_Class=0
Mass test: TS0(OOOxOOxO)TS7 MS_Class=1
Mass test: TS0(OOOxOOxO)TS7 MS_Class=2
Mass test: TS0(OOOxOOxO)TS7 MS_Class=3
Mass test: TS0(OOOxOOxO)TS7 MS_Class=4
Mass test: TS0(OOOxOOxO)TS7 MS_Class=5
Mass test: TS0(OOOxOOxO)TS7 MS_Class=6
Mass test: TS0(OOOxOOxO)TS7 MS_Class=7
Mass test: TS0(OOOxOOxO)TS7 MS_Class=8
Mass test: TS0(OOOxOOxO)TS7 MS_Class=9
Mass test: TS0(OOOxOOxO)TS7 MS_Class=10
Mass test: TS0(OOOxOOxO)TS7 MS_Class=11
Mass test: TS0(OOOxOOxO)TS7 MS_Class=12
Mass test: TS0(OOOxOOxO)TS7 MS_Class=13
Mass test: TS0(OOOxOOxO)TS7 MS_Class=14
Mass test: TS0(OOOxOOxO)TS7 MS_Class=15
Mass test: TS0(OOOxOOxO)TS7 MS_Class=16
Mass test: TS0(OOOxOOxO)TS7 MS_Class=17
Mass test: TS0(OOOxOOxO)TS7 MS_Class=18
Mass test: TS0(OOOxOOxO)TS7 MS_Class=19
Mass test: TS0(OOOxOOxO)TS7 MS_Class=20
Mass test: TS0(OOOxOOxO)TS7 MS_Class=21
Mass test: TS0(OOOxOOxO)TS7 MS_Class=22
Mass test: TS0(OOOxOOxO)TS7 MS_Class=23
Mass test: TS0(OOOxOOxO)TS7 MS_Class=24
Mass test: TS0(OOOxOOxO)TS7 MS_Class=25
Mass test: TS0(OOOxOOxO)TS7 MS_Class=26
Mass test: TS0(OOOxOOxO)TS7 MS_Class=27
Mass test: TS0(OOOxOOxO)TS7 MS_Class=28
Mass test: TS0(OOOxOOxO)TS7 MS_Class=29
Mass test: TS0(OOOxOOxO)TS7 MS_Class=30
Mass test: TS0(OOOxOOxO)TS7 MS_Class=31
Mass test: TS0(OOOxOOxO)TS7 MS_Class=32
Mass test: TS0(OOOxOOxO)TS7 MS_Class=33
Mass test: TS0(OOOxOOxO)TS7 MS_Class=34
Mass test: TS0(OOOxOOxO)TS7 MS_Class=35
Mass test: TS0(OOOxOOxO)TS7 MS_Class=36
Mass test: TS0(OOOxOOxO)TS7 MS_Class=37
Mass test: TS0(OOOxOOxO)TS7 MS_Class=38
Mass test: TS0(OOOxOOxO)TS7 MS_Class=39
Mass test: TS0(OOOxOOxO)TS7 MS_Class=40
Mass test: TS0(OOOxOOxO)TS7 MS_Class=41
Mass test: TS0(OOOxOOxO)TS7 MS_Class=42
Mass test: TS0(OOOxOOxO)TS7 MS_Class=43
Mass test: TS0(OOOxOOxO)TS7 MS_Class=44
Mass test: TS0(OOOxOOxO)TS7 MS_Class=45
Mass test: TS0(OOOxOOOx)TS7 MS_Class=0
Mass test: TS0(OOOxOOOx)TS7 MS_Class=1
Mass test: TS0(OOOxOOOx)TS7 MS_Class=2
Mass test: TS0(OOOxOOOx)TS7 MS_Class=3
Mass test: TS0(OOOxOOOx)TS7 MS_Class=4
Mass test: TS0(OOOxOOOx)TS7 MS_Class=5
Mass test: TS0(OOOxOOOx)TS7 MS_Class=6
Mass test: TS0(OOOxOOOx)TS7 MS_Class=7
Mass test: TS0(OOOxOOOx)TS7 MS_Class=8
Mass test: TS0(OOOxOOOx)TS7 MS_Class=9
Mass test: TS0(OOOxOOOx)TS7 MS_Class=10
Mass test: TS0(OOOxOOOx)TS7 MS_Class=11
Mass test: TS0(OOOxOOOx)TS7 MS_Class=12
Mass test: TS0(OOOxOOOx)TS7 MS_Class=13
Mass test: TS0(OOOxOOOx)TS7 MS_Class=14
Mass test: TS0(OOOxOOOx)TS7 MS_Class=15
Mass test: TS0(OOOxOOOx)TS7 MS_Class=16
Mass test: TS0(OOOxOOOx)TS7 MS_Class=17
Mass test: TS0(OOOxOOOx)TS7 MS_Class=18
Mass test: TS0(OOOxOOOx)TS7 MS_Class=19
Mass test: TS0(OOOxOOOx)TS7 MS_Class=20
Mass test: TS0(OOOxOOOx)TS7 MS_Class=21
Mass test: TS0(OOOxOOOx)TS7 MS_Class=22
Mass test: TS0(OOOxOOOx)TS7 MS_Class=23
Mass test: TS0(OOOxOOOx)TS7 MS_Class=24
Mass test: TS0(OOOxOOOx)TS7 MS_Class=25
Mass test: TS0(OOOxOOOx)TS7 MS_Class=26
Mass test: TS0(OOOxOOOx)TS7 MS_Class=27
Mass test: TS0(OOOxOOOx)TS7 MS_Class=28
Mass test: TS0(OOOxOOOx)TS7 MS_Class=29
Mass test: TS0(OOOxOOOx)TS7 MS_Class=30
Mass test: TS0(OOOxOOOx)TS7 MS_Class=31
Mass test: TS0(OOOxOOOx)TS7 MS_Class=32
Mass test: TS0(OOOxOOOx)TS7 MS_Class=33
Mass test: TS0(OOOxOOOx)TS7 MS_Class=34
Mass test: TS0(OOOxOOOx)TS7 MS_Class=35
Mass test: TS0(OOOxOOOx)TS7 MS_Class=36
Mass test: TS0(OOOxOOOx)TS7 MS_Class=37
Mass test: TS0(OOOxOOOx)TS7 MS_Class=38
Mass test: TS0(OOOxOOOx)TS7 MS_Class=39
Mass test: TS0(OOOxOOOx)TS7 MS_Class=40
Mass test: TS0(OOOxOOOx)TS7 MS_Class=41
Mass test: TS0(OOOxOOOx)TS7 MS_Class=42
Mass test: TS0(OOOxOOOx)TS7 MS_Class=43
Mass test: TS0(OOOxOOOx)TS7 MS_Class=44
Mass test: TS0(OOOxOOOx)TS7 MS_Class=45
Mass test: TS0(OOOxOOOO)TS7 MS_Class=0
Mass test: TS0(OOOxOOOO)TS7 MS_Class=1
Mass test: TS0(OOOxOOOO)TS7 MS_Class=2
Mass test: TS0(OOOxOOOO)TS7 MS_Class=3
Mass test: TS0(OOOxOOOO)TS7 MS_Class=4
Mass test: TS0(OOOxOOOO)TS7 MS_Class=5
Mass test: TS0(OOOxOOOO)TS7 MS_Class=6
Mass test: TS0(OOOxOOOO)TS7 MS_Class=7
Mass test: TS0(OOOxOOOO)TS7 MS_Class=8
Mass test: TS0(OOOxOOOO)TS7 MS_Class=9
Mass test: TS0(OOOxOOOO)TS7 MS_Class=10
Mass test: TS0(OOOxOOOO)TS7 MS_Class=11
Mass test: TS0(OOOxOOOO)TS7 MS_Class=12
Mass test: TS0(OOOxOOOO)TS7 MS_Class=13
Mass test: TS0(OOOxOOOO)TS7 MS_Class=14
Mass test: TS0(OOOxOOOO)TS7 MS_Class=15
Mass test: TS0(OOOxOOOO)TS7 MS_Class=16
Mass test: TS0(OOOxOOOO)TS7 MS_Class=17
Mass test: TS0(OOOxOOOO)TS7 MS_Class=18
Mass test: TS0(OOOxOOOO)TS7 MS_Class=19
Mass test: TS0(OOOxOOOO)TS7 MS_Class=20
Mass test: TS0(OOOxOOOO)TS7 MS_Class=21
Mass test: TS0(OOOxOOOO)TS7 MS_Class=22
Mass test: TS0(OOOxOOOO)TS7 MS_Class=23
Mass test: TS0(OOOxOOOO)TS7 MS_Class=24
Mass test: TS0(OOOxOOOO)TS7 MS_Class=25
Mass test: TS0(OOOxOOOO)TS7 MS_Class=26
Mass test: TS0(OOOxOOOO)TS7 MS_Class=27
Mass test: TS0(OOOxOOOO)TS7 MS_Class=28
Mass test: TS0(OOOxOOOO)TS7 MS_Class=29
Mass test: TS0(OOOxOOOO)TS7 MS_Class=30
Mass test: TS0(OOOxOOOO)TS7 MS_Class=31
Mass test: TS0(OOOxOOOO)TS7 MS_Class=32
Mass test: TS0(OOOxOOOO)TS7 MS_Class=33
Mass test: TS0(OOOxOOOO)TS7 MS_Class=34
Mass test: TS0(OOOxOOOO)TS7 MS_Class=35
Mass test: TS0(OOOxOOOO)TS7 MS_Class=36
Mass test: TS0(OOOxOOOO)TS7 MS_Class=37
Mass test: TS0(OOOxOOOO)TS7 MS_Class=38
Mass test: TS0(OOOxOOOO)TS7 MS_Class=39
Mass test: TS0(OOOxOOOO)TS7 MS_Class=40
Mass test: TS0(OOOxOOOO)TS7 MS_Class=41
Mass test: TS0(OOOxOOOO)TS7 MS_Class=42
Mass test: TS0(OOOxOOOO)TS7 MS_Class=43
Mass test: TS0(OOOxOOOO)TS7 MS_Class=44
Mass test: TS0(OOOxOOOO)TS7 MS_Class=45
Mass test: TS0(OOOOxxxx)TS7 MS_Class=0
Mass test: TS0(OOOOxxxx)TS7 MS_Class=1
Mass test: TS0(OOOOxxxx)TS7 MS_Class=2
Mass test: TS0(OOOOxxxx)TS7 MS_Class=3
Mass test: TS0(OOOOxxxx)TS7 MS_Class=4
Mass test: TS0(OOOOxxxx)TS7 MS_Class=5
Mass test: TS0(OOOOxxxx)TS7 MS_Class=6
Mass test: TS0(OOOOxxxx)TS7 MS_Class=7
Mass test: TS0(OOOOxxxx)TS7 MS_Class=8
Mass test: TS0(OOOOxxxx)TS7 MS_Class=9
Mass test: TS0(OOOOxxxx)TS7 MS_Class=10
Mass test: TS0(OOOOxxxx)TS7 MS_Class=11
Mass test: TS0(OOOOxxxx)TS7 MS_Class=12
Mass test: TS0(OOOOxxxx)TS7 MS_Class=13
Mass test: TS0(OOOOxxxx)TS7 MS_Class=14
Mass test: TS0(OOOOxxxx)TS7 MS_Class=15
Mass test: TS0(OOOOxxxx)TS7 MS_Class=16
Mass test: TS0(OOOOxxxx)TS7 MS_Class=17
Mass test: TS0(OOOOxxxx)TS7 MS_Class=18
Mass test: TS0(OOOOxxxx)TS7 MS_Class=19
Mass test: TS0(OOOOxxxx)TS7 MS_Class=20
Mass test: TS0(OOOOxxxx)TS7 MS_Class=21
Mass test: TS0(OOOOxxxx)TS7 MS_Class=22
Mass test: TS0(OOOOxxxx)TS7 MS_Class=23
Mass test: TS0(OOOOxxxx)TS7 MS_Class=24
Mass test: TS0(OOOOxxxx)TS7 MS_Class=25
Mass test: TS0(OOOOxxxx)TS7 MS_Class=26
Mass test: TS0(OOOOxxxx)TS7 MS_Class=27
Mass test: TS0(OOOOxxxx)TS7 MS_Class=28
Mass test: TS0(OOOOxxxx)TS7 MS_Class=29
Mass test: TS0(OOOOxxxx)TS7 MS_Class=30
Mass test: TS0(OOOOxxxx)TS7 MS_Class=31
Mass test: TS0(OOOOxxxx)TS7 MS_Class=32
Mass test: TS0(OOOOxxxx)TS7 MS_Class=33
Mass test: TS0(OOOOxxxx)TS7 MS_Class=34
Mass test: TS0(OOOOxxxx)TS7 MS_Class=35
Mass test: TS0(OOOOxxxx)TS7 MS_Class=36
Mass test: TS0(OOOOxxxx)TS7 MS_Class=37
Mass test: TS0(OOOOxxxx)TS7 MS_Class=38
Mass test: TS0(OOOOxxxx)TS7 MS_Class=39
Mass test: TS0(OOOOxxxx)TS7 MS_Class=40
Mass test: TS0(OOOOxxxx)TS7 MS_Class=41
Mass test: TS0(OOOOxxxx)TS7 MS_Class=42
Mass test: TS0(OOOOxxxx)TS7 MS_Class=43
Mass test: TS0(OOOOxxxx)TS7 MS_Class=44
Mass test: TS0(OOOOxxxx)TS7 MS_Class=45
Mass test: TS0(OOOOxxxO)TS7 MS_Class=0
Mass test: TS0(OOOOxxxO)TS7 MS_Class=1
Mass test: TS0(OOOOxxxO)TS7 MS_Class=2
Mass test: TS0(OOOOxxxO)TS7 MS_Class=3
Mass test: TS0(OOOOxxxO)TS7 MS_Class=4
Mass test: TS0(OOOOxxxO)TS7 MS_Class=5
Mass test: TS0(OOOOxxxO)TS7 MS_Class=6
Mass test: TS0(OOOOxxxO)TS7 MS_Class=7
Mass test: TS0(OOOOxxxO)TS7 MS_Class=8
Mass test: TS0(OOOOxxxO)TS7 MS_Class=9
Mass test: TS0(OOOOxxxO)TS7 MS_Class=10
Mass test: TS0(OOOOxxxO)TS7 MS_Class=11
Mass test: TS0(OOOOxxxO)TS7 MS_Class=12
Mass test: TS0(OOOOxxxO)TS7 MS_Class=13
Mass test: TS0(OOOOxxxO)TS7 MS_Class=14
Mass test: TS0(OOOOxxxO)TS7 MS_Class=15
Mass test: TS0(OOOOxxxO)TS7 MS_Class=16
Mass test: TS0(OOOOxxxO)TS7 MS_Class=17
Mass test: TS0(OOOOxxxO)TS7 MS_Class=18
Mass test: TS0(OOOOxxxO)TS7 MS_Class=19
Mass test: TS0(OOOOxxxO)TS7 MS_Class=20
Mass test: TS0(OOOOxxxO)TS7 MS_Class=21
Mass test: TS0(OOOOxxxO)TS7 MS_Class=22
Mass test: TS0(OOOOxxxO)TS7 MS_Class=23
Mass test: TS0(OOOOxxxO)TS7 MS_Class=24
Mass test: TS0(OOOOxxxO)TS7 MS_Class=25
Mass test: TS0(OOOOxxxO)TS7 MS_Class=26
Mass test: TS0(OOOOxxxO)TS7 MS_Class=27
Mass test: TS0(OOOOxxxO)TS7 MS_Class=28
Mass test: TS0(OOOOxxxO)TS7 MS_Class=29
Mass test: TS0(OOOOxxxO)TS7 MS_Class=30
Mass test: TS0(OOOOxxxO)TS7 MS_Class=31
Mass test: TS0(OOOOxxxO)TS7 MS_Class=32
Mass test: TS0(OOOOxxxO)TS7 MS_Class=33
Mass test: TS0(OOOOxxxO)TS7 MS_Class=34
Mass test: TS0(OOOOxxxO)TS7 MS_Class=35
Mass test: TS0(OOOOxxxO)TS7 MS_Class=36
Mass test: TS0(OOOOxxxO)TS7 MS_Class=37
Mass test: TS0(OOOOxxxO)TS7 MS_Class=38
Mass test: TS0(OOOOxxxO)TS7 MS_Class=39
Mass test: TS0(OOOOxxxO)TS7 MS_Class=40
Mass test: TS0(OOOOxxxO)TS7 MS_Class=41
Mass test: TS0(OOOOxxxO)TS7 MS_Class=42
Mass test: TS0(OOOOxxxO)TS7 MS_Class=43
Mass test: TS0(OOOOxxxO)TS7 MS_Class=44
Mass test: TS0(OOOOxxxO)TS7 MS_Class=45
Mass test: TS0(OOOOxxOx)TS7 MS_Class=0
Mass test: TS0(OOOOxxOx)TS7 MS_Class=1
Mass test: TS0(OOOOxxOx)TS7 MS_Class=2
Mass test: TS0(OOOOxxOx)TS7 MS_Class=3
Mass test: TS0(OOOOxxOx)TS7 MS_Class=4
Mass test: TS0(OOOOxxOx)TS7 MS_Class=5
Mass test: TS0(OOOOxxOx)TS7 MS_Class=6
Mass test: TS0(OOOOxxOx)TS7 MS_Class=7
Mass test: TS0(OOOOxxOx)TS7 MS_Class=8
Mass test: TS0(OOOOxxOx)TS7 MS_Class=9
Mass test: TS0(OOOOxxOx)TS7 MS_Class=10
Mass test: TS0(OOOOxxOx)TS7 MS_Class=11
Mass test: TS0(OOOOxxOx)TS7 MS_Class=12
Mass test: TS0(OOOOxxOx)TS7 MS_Class=13
Mass test: TS0(OOOOxxOx)TS7 MS_Class=14
Mass test: TS0(OOOOxxOx)TS7 MS_Class=15
Mass test: TS0(OOOOxxOx)TS7 MS_Class=16
Mass test: TS0(OOOOxxOx)TS7 MS_Class=17
Mass test: TS0(OOOOxxOx)TS7 MS_Class=18
Mass test: TS0(OOOOxxOx)TS7 MS_Class=19
Mass test: TS0(OOOOxxOx)TS7 MS_Class=20
Mass test: TS0(OOOOxxOx)TS7 MS_Class=21
Mass test: TS0(OOOOxxOx)TS7 MS_Class=22
Mass test: TS0(OOOOxxOx)TS7 MS_Class=23
Mass test: TS0(OOOOxxOx)TS7 MS_Class=24
Mass test: TS0(OOOOxxOx)TS7 MS_Class=25
Mass test: TS0(OOOOxxOx)TS7 MS_Class=26
Mass test: TS0(OOOOxxOx)TS7 MS_Class=27
Mass test: TS0(OOOOxxOx)TS7 MS_Class=28
Mass test: TS0(OOOOxxOx)TS7 MS_Class=29
Mass test: TS0(OOOOxxOx)TS7 MS_Class=30
Mass test: TS0(OOOOxxOx)TS7 MS_Class=31
Mass test: TS0(OOOOxxOx)TS7 MS_Class=32
Mass test: TS0(OOOOxxOx)TS7 MS_Class=33
Mass test: TS0(OOOOxxOx)TS7 MS_Class=34
Mass test: TS0(OOOOxxOx)TS7 MS_Class=35
Mass test: TS0(OOOOxxOx)TS7 MS_Class=36
Mass test: TS0(OOOOxxOx)TS7 MS_Class=37
Mass test: TS0(OOOOxxOx)TS7 MS_Class=38
Mass test: TS0(OOOOxxOx)TS7 MS_Class=39
Mass test: TS0(OOOOxxOx)TS7 MS_Class=40
Mass test: TS0(OOOOxxOx)TS7 MS_Class=41
Mass test: TS0(OOOOxxOx)TS7 MS_Class=42
Mass test: TS0(OOOOxxOx)TS7 MS_Class=43
Mass test: TS0(OOOOxxOx)TS7 MS_Class=44
Mass test: TS0(OOOOxxOx)TS7 MS_Class=45
Mass test: TS0(OOOOxxOO)TS7 MS_Class=0
Mass test: TS0(OOOOxxOO)TS7 MS_Class=1
Mass test: TS0(OOOOxxOO)TS7 MS_Class=2
Mass test: TS0(OOOOxxOO)TS7 MS_Class=3
Mass test: TS0(OOOOxxOO)TS7 MS_Class=4
Mass test: TS0(OOOOxxOO)TS7 MS_Class=5
Mass test: TS0(OOOOxxOO)TS7 MS_Class=6
Mass test: TS0(OOOOxxOO)TS7 MS_Class=7
Mass test: TS0(OOOOxxOO)TS7 MS_Class=8
Mass test: TS0(OOOOxxOO)TS7 MS_Class=9
Mass test: TS0(OOOOxxOO)TS7 MS_Class=10
Mass test: TS0(OOOOxxOO)TS7 MS_Class=11
Mass test: TS0(OOOOxxOO)TS7 MS_Class=12
Mass test: TS0(OOOOxxOO)TS7 MS_Class=13
Mass test: TS0(OOOOxxOO)TS7 MS_Class=14
Mass test: TS0(OOOOxxOO)TS7 MS_Class=15
Mass test: TS0(OOOOxxOO)TS7 MS_Class=16
Mass test: TS0(OOOOxxOO)TS7 MS_Class=17
Mass test: TS0(OOOOxxOO)TS7 MS_Class=18
Mass test: TS0(OOOOxxOO)TS7 MS_Class=19
Mass test: TS0(OOOOxxOO)TS7 MS_Class=20
Mass test: TS0(OOOOxxOO)TS7 MS_Class=21
Mass test: TS0(OOOOxxOO)TS7 MS_Class=22
Mass test: TS0(OOOOxxOO)TS7 MS_Class=23
Mass test: TS0(OOOOxxOO)TS7 MS_Class=24
Mass test: TS0(OOOOxxOO)TS7 MS_Class=25
Mass test: TS0(OOOOxxOO)TS7 MS_Class=26
Mass test: TS0(OOOOxxOO)TS7 MS_Class=27
Mass test: TS0(OOOOxxOO)TS7 MS_Class=28
Mass test: TS0(OOOOxxOO)TS7 MS_Class=29
Mass test: TS0(OOOOxxOO)TS7 MS_Class=30
Mass test: TS0(OOOOxxOO)TS7 MS_Class=31
Mass test: TS0(OOOOxxOO)TS7 MS_Class=32
Mass test: TS0(OOOOxxOO)TS7 MS_Class=33
Mass test: TS0(OOOOxxOO)TS7 MS_Class=34
Mass test: TS0(OOOOxxOO)TS7 MS_Class=35
Mass test: TS0(OOOOxxOO)TS7 MS_Class=36
Mass test: TS0(OOOOxxOO)TS7 MS_Class=37
Mass test: TS0(OOOOxxOO)TS7 MS_Class=38
Mass test: TS0(OOOOxxOO)TS7 MS_Class=39
Mass test: TS0(OOOOxxOO)TS7 MS_Class=40
Mass test: TS0(OOOOxxOO)TS7 MS_Class=41
Mass test: TS0(OOOOxxOO)TS7 MS_Class=42
Mass test: TS0(OOOOxxOO)TS7 MS_Class=43
Mass test: TS0(OOOOxxOO)TS7 MS_Class=44
Mass test: TS0(OOOOxxOO)TS7 MS_Class=45
Mass test: TS0(OOOOxOxx)TS7 MS_Class=0
Mass test: TS0(OOOOxOxx)TS7 MS_Class=1
Mass test: TS0(OOOOxOxx)TS7 MS_Class=2
Mass test: TS0(OOOOxOxx)TS7 MS_Class=3
Mass test: TS0(OOOOxOxx)TS7 MS_Class=4
Mass test: TS0(OOOOxOxx)TS7 MS_Class=5
Mass test: TS0(OOOOxOxx)TS7 MS_Class=6
Mass test: TS0(OOOOxOxx)TS7 MS_Class=7
Mass test: TS0(OOOOxOxx)TS7 MS_Class=8
Mass test: TS0(OOOOxOxx)TS7 MS_Class=9
Mass test: TS0(OOOOxOxx)TS7 MS_Class=10
Mass test: TS0(OOOOxOxx)TS7 MS_Class=11
Mass test: TS0(OOOOxOxx)TS7 MS_Class=12
Mass test: TS0(OOOOxOxx)TS7 MS_Class=13
Mass test: TS0(OOOOxOxx)TS7 MS_Class=14
Mass test: TS0(OOOOxOxx)TS7 MS_Class=15
Mass test: TS0(OOOOxOxx)TS7 MS_Class=16
Mass test: TS0(OOOOxOxx)TS7 MS_Class=17
Mass test: TS0(OOOOxOxx)TS7 MS_Class=18
Mass test: TS0(OOOOxOxx)TS7 MS_Class=19
Mass test: TS0(OOOOxOxx)TS7 MS_Class=20
Mass test: TS0(OOOOxOxx)TS7 MS_Class=21
Mass test: TS0(OOOOxOxx)TS7 MS_Class=22
Mass test: TS0(OOOOxOxx)TS7 MS_Class=23
Mass test: TS0(OOOOxOxx)TS7 MS_Class=24
Mass test: TS0(OOOOxOxx)TS7 MS_Class=25
Mass test: TS0(OOOOxOxx)TS7 MS_Class=26
Mass test: TS0(OOOOxOxx)TS7 MS_Class=27
Mass test: TS0(OOOOxOxx)TS7 MS_Class=28
Mass test: TS0(OOOOxOxx)TS7 MS_Class=29
Mass test: TS0(OOOOxOxx)TS7 MS_Class=30
Mass test: TS0(OOOOxOxx)TS7 MS_Class=31
Mass test: TS0(OOOOxOxx)TS7 MS_Class=32
Mass test: TS0(OOOOxOxx)TS7 MS_Class=33
Mass test: TS0(OOOOxOxx)TS7 MS_Class=34
Mass test: TS0(OOOOxOxx)TS7 MS_Class=35
Mass test: TS0(OOOOxOxx)TS7 MS_Class=36
Mass test: TS0(OOOOxOxx)TS7 MS_Class=37
Mass test: TS0(OOOOxOxx)TS7 MS_Class=38
Mass test: TS0(OOOOxOxx)TS7 MS_Class=39
Mass test: TS0(OOOOxOxx)TS7 MS_Class=40
Mass test: TS0(OOOOxOxx)TS7 MS_Class=41
Mass test: TS0(OOOOxOxx)TS7 MS_Class=42
Mass test: TS0(OOOOxOxx)TS7 MS_Class=43
Mass test: TS0(OOOOxOxx)TS7 MS_Class=44
Mass test: TS0(OOOOxOxx)TS7 MS_Class=45
Mass test: TS0(OOOOxOxO)TS7 MS_Class=0
Mass test: TS0(OOOOxOxO)TS7 MS_Class=1
Mass test: TS0(OOOOxOxO)TS7 MS_Class=2
Mass test: TS0(OOOOxOxO)TS7 MS_Class=3
Mass test: TS0(OOOOxOxO)TS7 MS_Class=4
Mass test: TS0(OOOOxOxO)TS7 MS_Class=5
Mass test: TS0(OOOOxOxO)TS7 MS_Class=6
Mass test: TS0(OOOOxOxO)TS7 MS_Class=7
Mass test: TS0(OOOOxOxO)TS7 MS_Class=8
Mass test: TS0(OOOOxOxO)TS7 MS_Class=9
Mass test: TS0(OOOOxOxO)TS7 MS_Class=10
Mass test: TS0(OOOOxOxO)TS7 MS_Class=11
Mass test: TS0(OOOOxOxO)TS7 MS_Class=12
Mass test: TS0(OOOOxOxO)TS7 MS_Class=13
Mass test: TS0(OOOOxOxO)TS7 MS_Class=14
Mass test: TS0(OOOOxOxO)TS7 MS_Class=15
Mass test: TS0(OOOOxOxO)TS7 MS_Class=16
Mass test: TS0(OOOOxOxO)TS7 MS_Class=17
Mass test: TS0(OOOOxOxO)TS7 MS_Class=18
Mass test: TS0(OOOOxOxO)TS7 MS_Class=19
Mass test: TS0(OOOOxOxO)TS7 MS_Class=20
Mass test: TS0(OOOOxOxO)TS7 MS_Class=21
Mass test: TS0(OOOOxOxO)TS7 MS_Class=22
Mass test: TS0(OOOOxOxO)TS7 MS_Class=23
Mass test: TS0(OOOOxOxO)TS7 MS_Class=24
Mass test: TS0(OOOOxOxO)TS7 MS_Class=25
Mass test: TS0(OOOOxOxO)TS7 MS_Class=26
Mass test: TS0(OOOOxOxO)TS7 MS_Class=27
Mass test: TS0(OOOOxOxO)TS7 MS_Class=28
Mass test: TS0(OOOOxOxO)TS7 MS_Class=29
Mass test: TS0(OOOOxOxO)TS7 MS_Class=30
Mass test: TS0(OOOOxOxO)TS7 MS_Class=31
Mass test: TS0(OOOOxOxO)TS7 MS_Class=32
Mass test: TS0(OOOOxOxO)TS7 MS_Class=33
Mass test: TS0(OOOOxOxO)TS7 MS_Class=34
Mass test: TS0(OOOOxOxO)TS7 MS_Class=35
Mass test: TS0(OOOOxOxO)TS7 MS_Class=36
Mass test: TS0(OOOOxOxO)TS7 MS_Class=37
Mass test: TS0(OOOOxOxO)TS7 MS_Class=38
Mass test: TS0(OOOOxOxO)TS7 MS_Class=39
Mass test: TS0(OOOOxOxO)TS7 MS_Class=40
Mass test: TS0(OOOOxOxO)TS7 MS_Class=41
Mass test: TS0(OOOOxOxO)TS7 MS_Class=42
Mass test: TS0(OOOOxOxO)TS7 MS_Class=43
Mass test: TS0(OOOOxOxO)TS7 MS_Class=44
Mass test: TS0(OOOOxOxO)TS7 MS_Class=45
Mass test: TS0(OOOOxOOx)TS7 MS_Class=0
Mass test: TS0(OOOOxOOx)TS7 MS_Class=1
Mass test: TS0(OOOOxOOx)TS7 MS_Class=2
Mass test: TS0(OOOOxOOx)TS7 MS_Class=3
Mass test: TS0(OOOOxOOx)TS7 MS_Class=4
Mass test: TS0(OOOOxOOx)TS7 MS_Class=5
Mass test: TS0(OOOOxOOx)TS7 MS_Class=6
Mass test: TS0(OOOOxOOx)TS7 MS_Class=7
Mass test: TS0(OOOOxOOx)TS7 MS_Class=8
Mass test: TS0(OOOOxOOx)TS7 MS_Class=9
Mass test: TS0(OOOOxOOx)TS7 MS_Class=10
Mass test: TS0(OOOOxOOx)TS7 MS_Class=11
Mass test: TS0(OOOOxOOx)TS7 MS_Class=12
Mass test: TS0(OOOOxOOx)TS7 MS_Class=13
Mass test: TS0(OOOOxOOx)TS7 MS_Class=14
Mass test: TS0(OOOOxOOx)TS7 MS_Class=15
Mass test: TS0(OOOOxOOx)TS7 MS_Class=16
Mass test: TS0(OOOOxOOx)TS7 MS_Class=17
Mass test: TS0(OOOOxOOx)TS7 MS_Class=18
Mass test: TS0(OOOOxOOx)TS7 MS_Class=19
Mass test: TS0(OOOOxOOx)TS7 MS_Class=20
Mass test: TS0(OOOOxOOx)TS7 MS_Class=21
Mass test: TS0(OOOOxOOx)TS7 MS_Class=22
Mass test: TS0(OOOOxOOx)TS7 MS_Class=23
Mass test: TS0(OOOOxOOx)TS7 MS_Class=24
Mass test: TS0(OOOOxOOx)TS7 MS_Class=25
Mass test: TS0(OOOOxOOx)TS7 MS_Class=26
Mass test: TS0(OOOOxOOx)TS7 MS_Class=27
Mass test: TS0(OOOOxOOx)TS7 MS_Class=28
Mass test: TS0(OOOOxOOx)TS7 MS_Class=29
Mass test: TS0(OOOOxOOx)TS7 MS_Class=30
Mass test: TS0(OOOOxOOx)TS7 MS_Class=31
Mass test: TS0(OOOOxOOx)TS7 MS_Class=32
Mass test: TS0(OOOOxOOx)TS7 MS_Class=33
Mass test: TS0(OOOOxOOx)TS7 MS_Class=34
Mass test: TS0(OOOOxOOx)TS7 MS_Class=35
Mass test: TS0(OOOOxOOx)TS7 MS_Class=36
Mass test: TS0(OOOOxOOx)TS7 MS_Class=37
Mass test: TS0(OOOOxOOx)TS7 MS_Class=38
Mass test: TS0(OOOOxOOx)TS7 MS_Class=39
Mass test: TS0(OOOOxOOx)TS7 MS_Class=40
Mass test: TS0(OOOOxOOx)TS7 MS_Class=41
Mass test: TS0(OOOOxOOx)TS7 MS_Class=42
Mass test: TS0(OOOOxOOx)TS7 MS_Class=43
Mass test: TS0(OOOOxOOx)TS7 MS_Class=44
Mass test: TS0(OOOOxOOx)TS7 MS_Class=45
Mass test: TS0(OOOOxOOO)TS7 MS_Class=0
Mass test: TS0(OOOOxOOO)TS7 MS_Class=1
Mass test: TS0(OOOOxOOO)TS7 MS_Class=2
Mass test: TS0(OOOOxOOO)TS7 MS_Class=3
Mass test: TS0(OOOOxOOO)TS7 MS_Class=4
Mass test: TS0(OOOOxOOO)TS7 MS_Class=5
Mass test: TS0(OOOOxOOO)TS7 MS_Class=6
Mass test: TS0(OOOOxOOO)TS7 MS_Class=7
Mass test: TS0(OOOOxOOO)TS7 MS_Class=8
Mass test: TS0(OOOOxOOO)TS7 MS_Class=9
Mass test: TS0(OOOOxOOO)TS7 MS_Class=10
Mass test: TS0(OOOOxOOO)TS7 MS_Class=11
Mass test: TS0(OOOOxOOO)TS7 MS_Class=12
Mass test: TS0(OOOOxOOO)TS7 MS_Class=13
Mass test: TS0(OOOOxOOO)TS7 MS_Class=14
Mass test: TS0(OOOOxOOO)TS7 MS_Class=15
Mass test: TS0(OOOOxOOO)TS7 MS_Class=16
Mass test: TS0(OOOOxOOO)TS7 MS_Class=17
Mass test: TS0(OOOOxOOO)TS7 MS_Class=18
Mass test: TS0(OOOOxOOO)TS7 MS_Class=19
Mass test: TS0(OOOOxOOO)TS7 MS_Class=20
Mass test: TS0(OOOOxOOO)TS7 MS_Class=21
Mass test: TS0(OOOOxOOO)TS7 MS_Class=22
Mass test: TS0(OOOOxOOO)TS7 MS_Class=23
Mass test: TS0(OOOOxOOO)TS7 MS_Class=24
Mass test: TS0(OOOOxOOO)TS7 MS_Class=25
Mass test: TS0(OOOOxOOO)TS7 MS_Class=26
Mass test: TS0(OOOOxOOO)TS7 MS_Class=27
Mass test: TS0(OOOOxOOO)TS7 MS_Class=28
Mass test: TS0(OOOOxOOO)TS7 MS_Class=29
Mass test: TS0(OOOOxOOO)TS7 MS_Class=30
Mass test: TS0(OOOOxOOO)TS7 MS_Class=31
Mass test: TS0(OOOOxOOO)TS7 MS_Class=32
Mass test: TS0(OOOOxOOO)TS7 MS_Class=33
Mass test: TS0(OOOOxOOO)TS7 MS_Class=34
Mass test: TS0(OOOOxOOO)TS7 MS_Class=35
Mass test: TS0(OOOOxOOO)TS7 MS_Class=36
Mass test: TS0(OOOOxOOO)TS7 MS_Class=37
Mass test: TS0(OOOOxOOO)TS7 MS_Class=38
Mass test: TS0(OOOOxOOO)TS7 MS_Class=39
Mass test: TS0(OOOOxOOO)TS7 MS_Class=40
Mass test: TS0(OOOOxOOO)TS7 MS_Class=41
Mass test: TS0(OOOOxOOO)TS7 MS_Class=42
Mass test: TS0(OOOOxOOO)TS7 MS_Class=43
Mass test: TS0(OOOOxOOO)TS7 MS_Class=44
Mass test: TS0(OOOOxOOO)TS7 MS_Class=45
Mass test: TS0(OOOOOxxx)TS7 MS_Class=0
Mass test: TS0(OOOOOxxx)TS7 MS_Class=1
Mass test: TS0(OOOOOxxx)TS7 MS_Class=2
Mass test: TS0(OOOOOxxx)TS7 MS_Class=3
Mass test: TS0(OOOOOxxx)TS7 MS_Class=4
Mass test: TS0(OOOOOxxx)TS7 MS_Class=5
Mass test: TS0(OOOOOxxx)TS7 MS_Class=6
Mass test: TS0(OOOOOxxx)TS7 MS_Class=7
Mass test: TS0(OOOOOxxx)TS7 MS_Class=8
Mass test: TS0(OOOOOxxx)TS7 MS_Class=9
Mass test: TS0(OOOOOxxx)TS7 MS_Class=10
Mass test: TS0(OOOOOxxx)TS7 MS_Class=11
Mass test: TS0(OOOOOxxx)TS7 MS_Class=12
Mass test: TS0(OOOOOxxx)TS7 MS_Class=13
Mass test: TS0(OOOOOxxx)TS7 MS_Class=14
Mass test: TS0(OOOOOxxx)TS7 MS_Class=15
Mass test: TS0(OOOOOxxx)TS7 MS_Class=16
Mass test: TS0(OOOOOxxx)TS7 MS_Class=17
Mass test: TS0(OOOOOxxx)TS7 MS_Class=18
Mass test: TS0(OOOOOxxx)TS7 MS_Class=19
Mass test: TS0(OOOOOxxx)TS7 MS_Class=20
Mass test: TS0(OOOOOxxx)TS7 MS_Class=21
Mass test: TS0(OOOOOxxx)TS7 MS_Class=22
Mass test: TS0(OOOOOxxx)TS7 MS_Class=23
Mass test: TS0(OOOOOxxx)TS7 MS_Class=24
Mass test: TS0(OOOOOxxx)TS7 MS_Class=25
Mass test: TS0(OOOOOxxx)TS7 MS_Class=26
Mass test: TS0(OOOOOxxx)TS7 MS_Class=27
Mass test: TS0(OOOOOxxx)TS7 MS_Class=28
Mass test: TS0(OOOOOxxx)TS7 MS_Class=29
Mass test: TS0(OOOOOxxx)TS7 MS_Class=30
Mass test: TS0(OOOOOxxx)TS7 MS_Class=31
Mass test: TS0(OOOOOxxx)TS7 MS_Class=32
Mass test: TS0(OOOOOxxx)TS7 MS_Class=33
Mass test: TS0(OOOOOxxx)TS7 MS_Class=34
Mass test: TS0(OOOOOxxx)TS7 MS_Class=35
Mass test: TS0(OOOOOxxx)TS7 MS_Class=36
Mass test: TS0(OOOOOxxx)TS7 MS_Class=37
Mass test: TS0(OOOOOxxx)TS7 MS_Class=38
Mass test: TS0(OOOOOxxx)TS7 MS_Class=39
Mass test: TS0(OOOOOxxx)TS7 MS_Class=40
Mass test: TS0(OOOOOxxx)TS7 MS_Class=41
Mass test: TS0(OOOOOxxx)TS7 MS_Class=42
Mass test: TS0(OOOOOxxx)TS7 MS_Class=43
Mass test: TS0(OOOOOxxx)TS7 MS_Class=44
Mass test: TS0(OOOOOxxx)TS7 MS_Class=45
Mass test: TS0(OOOOOxxO)TS7 MS_Class=0
Mass test: TS0(OOOOOxxO)TS7 MS_Class=1
Mass test: TS0(OOOOOxxO)TS7 MS_Class=2
Mass test: TS0(OOOOOxxO)TS7 MS_Class=3
Mass test: TS0(OOOOOxxO)TS7 MS_Class=4
Mass test: TS0(OOOOOxxO)TS7 MS_Class=5
Mass test: TS0(OOOOOxxO)TS7 MS_Class=6
Mass test: TS0(OOOOOxxO)TS7 MS_Class=7
Mass test: TS0(OOOOOxxO)TS7 MS_Class=8
Mass test: TS0(OOOOOxxO)TS7 MS_Class=9
Mass test: TS0(OOOOOxxO)TS7 MS_Class=10
Mass test: TS0(OOOOOxxO)TS7 MS_Class=11
Mass test: TS0(OOOOOxxO)TS7 MS_Class=12
Mass test: TS0(OOOOOxxO)TS7 MS_Class=13
Mass test: TS0(OOOOOxxO)TS7 MS_Class=14
Mass test: TS0(OOOOOxxO)TS7 MS_Class=15
Mass test: TS0(OOOOOxxO)TS7 MS_Class=16
Mass test: TS0(OOOOOxxO)TS7 MS_Class=17
Mass test: TS0(OOOOOxxO)TS7 MS_Class=18
Mass test: TS0(OOOOOxxO)TS7 MS_Class=19
Mass test: TS0(OOOOOxxO)TS7 MS_Class=20
Mass test: TS0(OOOOOxxO)TS7 MS_Class=21
Mass test: TS0(OOOOOxxO)TS7 MS_Class=22
Mass test: TS0(OOOOOxxO)TS7 MS_Class=23
Mass test: TS0(OOOOOxxO)TS7 MS_Class=24
Mass test: TS0(OOOOOxxO)TS7 MS_Class=25
Mass test: TS0(OOOOOxxO)TS7 MS_Class=26
Mass test: TS0(OOOOOxxO)TS7 MS_Class=27
Mass test: TS0(OOOOOxxO)TS7 MS_Class=28
Mass test: TS0(OOOOOxxO)TS7 MS_Class=29
Mass test: TS0(OOOOOxxO)TS7 MS_Class=30
Mass test: TS0(OOOOOxxO)TS7 MS_Class=31
Mass test: TS0(OOOOOxxO)TS7 MS_Class=32
Mass test: TS0(OOOOOxxO)TS7 MS_Class=33
Mass test: TS0(OOOOOxxO)TS7 MS_Class=34
Mass test: TS0(OOOOOxxO)TS7 MS_Class=35
Mass test: TS0(OOOOOxxO)TS7 MS_Class=36
Mass test: TS0(OOOOOxxO)TS7 MS_Class=37
Mass test: TS0(OOOOOxxO)TS7 MS_Class=38
Mass test: TS0(OOOOOxxO)TS7 MS_Class=39
Mass test: TS0(OOOOOxxO)TS7 MS_Class=40
Mass test: TS0(OOOOOxxO)TS7 MS_Class=41
Mass test: TS0(OOOOOxxO)TS7 MS_Class=42
Mass test: TS0(OOOOOxxO)TS7 MS_Class=43
Mass test: TS0(OOOOOxxO)TS7 MS_Class=44
Mass test: TS0(OOOOOxxO)TS7 MS_Class=45
Mass test: TS0(OOOOOxOx)TS7 MS_Class=0
Mass test: TS0(OOOOOxOx)TS7 MS_Class=1
Mass test: TS0(OOOOOxOx)TS7 MS_Class=2
Mass test: TS0(OOOOOxOx)TS7 MS_Class=3
Mass test: TS0(OOOOOxOx)TS7 MS_Class=4
Mass test: TS0(OOOOOxOx)TS7 MS_Class=5
Mass test: TS0(OOOOOxOx)TS7 MS_Class=6
Mass test: TS0(OOOOOxOx)TS7 MS_Class=7
Mass test: TS0(OOOOOxOx)TS7 MS_Class=8
Mass test: TS0(OOOOOxOx)TS7 MS_Class=9
Mass test: TS0(OOOOOxOx)TS7 MS_Class=10
Mass test: TS0(OOOOOxOx)TS7 MS_Class=11
Mass test: TS0(OOOOOxOx)TS7 MS_Class=12
Mass test: TS0(OOOOOxOx)TS7 MS_Class=13
Mass test: TS0(OOOOOxOx)TS7 MS_Class=14
Mass test: TS0(OOOOOxOx)TS7 MS_Class=15
Mass test: TS0(OOOOOxOx)TS7 MS_Class=16
Mass test: TS0(OOOOOxOx)TS7 MS_Class=17
Mass test: TS0(OOOOOxOx)TS7 MS_Class=18
Mass test: TS0(OOOOOxOx)TS7 MS_Class=19
Mass test: TS0(OOOOOxOx)TS7 MS_Class=20
Mass test: TS0(OOOOOxOx)TS7 MS_Class=21
Mass test: TS0(OOOOOxOx)TS7 MS_Class=22
Mass test: TS0(OOOOOxOx)TS7 MS_Class=23
Mass test: TS0(OOOOOxOx)TS7 MS_Class=24
Mass test: TS0(OOOOOxOx)TS7 MS_Class=25
Mass test: TS0(OOOOOxOx)TS7 MS_Class=26
Mass test: TS0(OOOOOxOx)TS7 MS_Class=27
Mass test: TS0(OOOOOxOx)TS7 MS_Class=28
Mass test: TS0(OOOOOxOx)TS7 MS_Class=29
Mass test: TS0(OOOOOxOx)TS7 MS_Class=30
Mass test: TS0(OOOOOxOx)TS7 MS_Class=31
Mass test: TS0(OOOOOxOx)TS7 MS_Class=32
Mass test: TS0(OOOOOxOx)TS7 MS_Class=33
Mass test: TS0(OOOOOxOx)TS7 MS_Class=34
Mass test: TS0(OOOOOxOx)TS7 MS_Class=35
Mass test: TS0(OOOOOxOx)TS7 MS_Class=36
Mass test: TS0(OOOOOxOx)TS7 MS_Class=37
Mass test: TS0(OOOOOxOx)TS7 MS_Class=38
Mass test: TS0(OOOOOxOx)TS7 MS_Class=39
Mass test: TS0(OOOOOxOx)TS7 MS_Class=40
Mass test: TS0(OOOOOxOx)TS7 MS_Class=41
Mass test: TS0(OOOOOxOx)TS7 MS_Class=42
Mass test: TS0(OOOOOxOx)TS7 MS_Class=43
Mass test: TS0(OOOOOxOx)TS7 MS_Class=44
Mass test: TS0(OOOOOxOx)TS7 MS_Class=45
Mass test: TS0(OOOOOxOO)TS7 MS_Class=0
Mass test: TS0(OOOOOxOO)TS7 MS_Class=1
Mass test: TS0(OOOOOxOO)TS7 MS_Class=2
Mass test: TS0(OOOOOxOO)TS7 MS_Class=3
Mass test: TS0(OOOOOxOO)TS7 MS_Class=4
Mass test: TS0(OOOOOxOO)TS7 MS_Class=5
Mass test: TS0(OOOOOxOO)TS7 MS_Class=6
Mass test: TS0(OOOOOxOO)TS7 MS_Class=7
Mass test: TS0(OOOOOxOO)TS7 MS_Class=8
Mass test: TS0(OOOOOxOO)TS7 MS_Class=9
Mass test: TS0(OOOOOxOO)TS7 MS_Class=10
Mass test: TS0(OOOOOxOO)TS7 MS_Class=11
Mass test: TS0(OOOOOxOO)TS7 MS_Class=12
Mass test: TS0(OOOOOxOO)TS7 MS_Class=13
Mass test: TS0(OOOOOxOO)TS7 MS_Class=14
Mass test: TS0(OOOOOxOO)TS7 MS_Class=15
Mass test: TS0(OOOOOxOO)TS7 MS_Class=16
Mass test: TS0(OOOOOxOO)TS7 MS_Class=17
Mass test: TS0(OOOOOxOO)TS7 MS_Class=18
Mass test: TS0(OOOOOxOO)TS7 MS_Class=19
Mass test: TS0(OOOOOxOO)TS7 MS_Class=20
Mass test: TS0(OOOOOxOO)TS7 MS_Class=21
Mass test: TS0(OOOOOxOO)TS7 MS_Class=22
Mass test: TS0(OOOOOxOO)TS7 MS_Class=23
Mass test: TS0(OOOOOxOO)TS7 MS_Class=24
Mass test: TS0(OOOOOxOO)TS7 MS_Class=25
Mass test: TS0(OOOOOxOO)TS7 MS_Class=26
Mass test: TS0(OOOOOxOO)TS7 MS_Class=27
Mass test: TS0(OOOOOxOO)TS7 MS_Class=28
Mass test: TS0(OOOOOxOO)TS7 MS_Class=29
Mass test: TS0(OOOOOxOO)TS7 MS_Class=30
Mass test: TS0(OOOOOxOO)TS7 MS_Class=31
Mass test: TS0(OOOOOxOO)TS7 MS_Class=32
Mass test: TS0(OOOOOxOO)TS7 MS_Class=33
Mass test: TS0(OOOOOxOO)TS7 MS_Class=34
Mass test: TS0(OOOOOxOO)TS7 MS_Class=35
Mass test: TS0(OOOOOxOO)TS7 MS_Class=36
Mass test: TS0(OOOOOxOO)TS7 MS_Class=37
Mass test: TS0(OOOOOxOO)TS7 MS_Class=38
Mass test: TS0(OOOOOxOO)TS7 MS_Class=39
Mass test: TS0(OOOOOxOO)TS7 MS_Class=40
Mass test: TS0(OOOOOxOO)TS7 MS_Class=41
Mass test: TS0(OOOOOxOO)TS7 MS_Class=42
Mass test: TS0(OOOOOxOO)TS7 MS_Class=43
Mass test: TS0(OOOOOxOO)TS7 MS_Class=44
Mass test: TS0(OOOOOxOO)TS7 MS_Class=45
Mass test: TS0(OOOOOOxx)TS7 MS_Class=0
Mass test: TS0(OOOOOOxx)TS7 MS_Class=1
Mass test: TS0(OOOOOOxx)TS7 MS_Class=2
Mass test: TS0(OOOOOOxx)TS7 MS_Class=3
Mass test: TS0(OOOOOOxx)TS7 MS_Class=4
Mass test: TS0(OOOOOOxx)TS7 MS_Class=5
Mass test: TS0(OOOOOOxx)TS7 MS_Class=6
Mass test: TS0(OOOOOOxx)TS7 MS_Class=7
Mass test: TS0(OOOOOOxx)TS7 MS_Class=8
Mass test: TS0(OOOOOOxx)TS7 MS_Class=9
Mass test: TS0(OOOOOOxx)TS7 MS_Class=10
Mass test: TS0(OOOOOOxx)TS7 MS_Class=11
Mass test: TS0(OOOOOOxx)TS7 MS_Class=12
Mass test: TS0(OOOOOOxx)TS7 MS_Class=13
Mass test: TS0(OOOOOOxx)TS7 MS_Class=14
Mass test: TS0(OOOOOOxx)TS7 MS_Class=15
Mass test: TS0(OOOOOOxx)TS7 MS_Class=16
Mass test: TS0(OOOOOOxx)TS7 MS_Class=17
Mass test: TS0(OOOOOOxx)TS7 MS_Class=18
Mass test: TS0(OOOOOOxx)TS7 MS_Class=19
Mass test: TS0(OOOOOOxx)TS7 MS_Class=20
Mass test: TS0(OOOOOOxx)TS7 MS_Class=21
Mass test: TS0(OOOOOOxx)TS7 MS_Class=22
Mass test: TS0(OOOOOOxx)TS7 MS_Class=23
Mass test: TS0(OOOOOOxx)TS7 MS_Class=24
Mass test: TS0(OOOOOOxx)TS7 MS_Class=25
Mass test: TS0(OOOOOOxx)TS7 MS_Class=26
Mass test: TS0(OOOOOOxx)TS7 MS_Class=27
Mass test: TS0(OOOOOOxx)TS7 MS_Class=28
Mass test: TS0(OOOOOOxx)TS7 MS_Class=29
Mass test: TS0(OOOOOOxx)TS7 MS_Class=30
Mass test: TS0(OOOOOOxx)TS7 MS_Class=31
Mass test: TS0(OOOOOOxx)TS7 MS_Class=32
Mass test: TS0(OOOOOOxx)TS7 MS_Class=33
Mass test: TS0(OOOOOOxx)TS7 MS_Class=34
Mass test: TS0(OOOOOOxx)TS7 MS_Class=35
Mass test: TS0(OOOOOOxx)TS7 MS_Class=36
Mass test: TS0(OOOOOOxx)TS7 MS_Class=37
Mass test: TS0(OOOOOOxx)TS7 MS_Class=38
Mass test: TS0(OOOOOOxx)TS7 MS_Class=39
Mass test: TS0(OOOOOOxx)TS7 MS_Class=40
Mass test: TS0(OOOOOOxx)TS7 MS_Class=41
Mass test: TS0(OOOOOOxx)TS7 MS_Class=42
Mass test: TS0(OOOOOOxx)TS7 MS_Class=43
Mass test: TS0(OOOOOOxx)TS7 MS_Class=44
Mass test: TS0(OOOOOOxx)TS7 MS_Class=45
Mass test: TS0(OOOOOOxO)TS7 MS_Class=0
Mass test: TS0(OOOOOOxO)TS7 MS_Class=1
Mass test: TS0(OOOOOOxO)TS7 MS_Class=2
Mass test: TS0(OOOOOOxO)TS7 MS_Class=3
Mass test: TS0(OOOOOOxO)TS7 MS_Class=4
Mass test: TS0(OOOOOOxO)TS7 MS_Class=5
Mass test: TS0(OOOOOOxO)TS7 MS_Class=6
Mass test: TS0(OOOOOOxO)TS7 MS_Class=7
Mass test: TS0(OOOOOOxO)TS7 MS_Class=8
Mass test: TS0(OOOOOOxO)TS7 MS_Class=9
Mass test: TS0(OOOOOOxO)TS7 MS_Class=10
Mass test: TS0(OOOOOOxO)TS7 MS_Class=11
Mass test: TS0(OOOOOOxO)TS7 MS_Class=12
Mass test: TS0(OOOOOOxO)TS7 MS_Class=13
Mass test: TS0(OOOOOOxO)TS7 MS_Class=14
Mass test: TS0(OOOOOOxO)TS7 MS_Class=15
Mass test: TS0(OOOOOOxO)TS7 MS_Class=16
Mass test: TS0(OOOOOOxO)TS7 MS_Class=17
Mass test: TS0(OOOOOOxO)TS7 MS_Class=18
Mass test: TS0(OOOOOOxO)TS7 MS_Class=19
Mass test: TS0(OOOOOOxO)TS7 MS_Class=20
Mass test: TS0(OOOOOOxO)TS7 MS_Class=21
Mass test: TS0(OOOOOOxO)TS7 MS_Class=22
Mass test: TS0(OOOOOOxO)TS7 MS_Class=23
Mass test: TS0(OOOOOOxO)TS7 MS_Class=24
Mass test: TS0(OOOOOOxO)TS7 MS_Class=25
Mass test: TS0(OOOOOOxO)TS7 MS_Class=26
Mass test: TS0(OOOOOOxO)TS7 MS_Class=27
Mass test: TS0(OOOOOOxO)TS7 MS_Class=28
Mass test: TS0(OOOOOOxO)TS7 MS_Class=29
Mass test: TS0(OOOOOOxO)TS7 MS_Class=30
Mass test: TS0(OOOOOOxO)TS7 MS_Class=31
Mass test: TS0(OOOOOOxO)TS7 MS_Class=32
Mass test: TS0(OOOOOOxO)TS7 MS_Class=33
Mass test: TS0(OOOOOOxO)TS7 MS_Class=34
Mass test: TS0(OOOOOOxO)TS7 MS_Class=35
Mass test: TS0(OOOOOOxO)TS7 MS_Class=36
Mass test: TS0(OOOOOOxO)TS7 MS_Class=37
Mass test: TS0(OOOOOOxO)TS7 MS_Class=38
Mass test: TS0(OOOOOOxO)TS7 MS_Class=39
Mass test: TS0(OOOOOOxO)TS7 MS_Class=40
Mass test: TS0(OOOOOOxO)TS7 MS_Class=41
Mass test: TS0(OOOOOOxO)TS7 MS_Class=42
Mass test: TS0(OOOOOOxO)TS7 MS_Class=43
Mass test: TS0(OOOOOOxO)TS7 MS_Class=44
Mass test: TS0(OOOOOOxO)TS7 MS_Class=45
Mass test: TS0(OOOOOOOx)TS7 MS_Class=0
Mass test: TS0(OOOOOOOx)TS7 MS_Class=1
Mass test: TS0(OOOOOOOx)TS7 MS_Class=2
Mass test: TS0(OOOOOOOx)TS7 MS_Class=3
Mass test: TS0(OOOOOOOx)TS7 MS_Class=4
Mass test: TS0(OOOOOOOx)TS7 MS_Class=5
Mass test: TS0(OOOOOOOx)TS7 MS_Class=6
Mass test: TS0(OOOOOOOx)TS7 MS_Class=7
Mass test: TS0(OOOOOOOx)TS7 MS_Class=8
Mass test: TS0(OOOOOOOx)TS7 MS_Class=9
Mass test: TS0(OOOOOOOx)TS7 MS_Class=10
Mass test: TS0(OOOOOOOx)TS7 MS_Class=11
Mass test: TS0(OOOOOOOx)TS7 MS_Class=12
Mass test: TS0(OOOOOOOx)TS7 MS_Class=13
Mass test: TS0(OOOOOOOx)TS7 MS_Class=14
Mass test: TS0(OOOOOOOx)TS7 MS_Class=15
Mass test: TS0(OOOOOOOx)TS7 MS_Class=16
Mass test: TS0(OOOOOOOx)TS7 MS_Class=17
Mass test: TS0(OOOOOOOx)TS7 MS_Class=18
Mass test: TS0(OOOOOOOx)TS7 MS_Class=19
Mass test: TS0(OOOOOOOx)TS7 MS_Class=20
Mass test: TS0(OOOOOOOx)TS7 MS_Class=21
Mass test: TS0(OOOOOOOx)TS7 MS_Class=22
Mass test: TS0(OOOOOOOx)TS7 MS_Class=23
Mass test: TS0(OOOOOOOx)TS7 MS_Class=24
Mass test: TS0(OOOOOOOx)TS7 MS_Class=25
Mass test: TS0(OOOOOOOx)TS7 MS_Class=26
Mass test: TS0(OOOOOOOx)TS7 MS_Class=27
Mass test: TS0(OOOOOOOx)TS7 MS_Class=28
Mass test: TS0(OOOOOOOx)TS7 MS_Class=29
Mass test: TS0(OOOOOOOx)TS7 MS_Class=30
Mass test: TS0(OOOOOOOx)TS7 MS_Class=31
Mass test: TS0(OOOOOOOx)TS7 MS_Class=32
Mass test: TS0(OOOOOOOx)TS7 MS_Class=33
Mass test: TS0(OOOOOOOx)TS7 MS_Class=34
Mass test: TS0(OOOOOOOx)TS7 MS_Class=35
Mass test: TS0(OOOOOOOx)TS7 MS_Class=36
Mass test: TS0(OOOOOOOx)TS7 MS_Class=37
Mass test: TS0(OOOOOOOx)TS7 MS_Class=38
Mass test: TS0(OOOOOOOx)TS7 MS_Class=39
Mass test: TS0(OOOOOOOx)TS7 MS_Class=40
Mass test: TS0(OOOOOOOx)TS7 MS_Class=41
Mass test: TS0(OOOOOOOx)TS7 MS_Class=42
Mass test: TS0(OOOOOOOx)TS7 MS_Class=43
Mass test: TS0(OOOOOOOx)TS7 MS_Class=44
Mass test: TS0(OOOOOOOx)TS7 MS_Class=45
Mass test: TS0(OOOOOOOO)TS7 MS_Class=0
Mass test: TS0(OOOOOOOO)TS7 MS_Class=1
Mass test: TS0(OOOOOOOO)TS7 MS_Class=2
Mass test: TS0(OOOOOOOO)TS7 MS_Class=3
Mass test: TS0(OOOOOOOO)TS7 MS_Class=4
Mass test: TS0(OOOOOOOO)TS7 MS_Class=5
Mass test: TS0(OOOOOOOO)TS7 MS_Class=6
Mass test: TS0(OOOOOOOO)TS7 MS_Class=7
Mass test: TS0(OOOOOOOO)TS7 MS_Class=8
Mass test: TS0(OOOOOOOO)TS7 MS_Class=9
Mass test: TS0(OOOOOOOO)TS7 MS_Class=10
Mass test: TS0(OOOOOOOO)TS7 MS_Class=11
Mass test: TS0(OOOOOOOO)TS7 MS_Class=12
Mass test: TS0(OOOOOOOO)TS7 MS_Class=13
Mass test: TS0(OOOOOOOO)TS7 MS_Class=14
Mass test: TS0(OOOOOOOO)TS7 MS_Class=15
Mass test: TS0(OOOOOOOO)TS7 MS_Class=16
Mass test: TS0(OOOOOOOO)TS7 MS_Class=17
Mass test: TS0(OOOOOOOO)TS7 MS_Class=18
Mass test: TS0(OOOOOOOO)TS7 MS_Class=19
Mass test: TS0(OOOOOOOO)TS7 MS_Class=20
Mass test: TS0(OOOOOOOO)TS7 MS_Class=21
Mass test: TS0(OOOOOOOO)TS7 MS_Class=22
Mass test: TS0(OOOOOOOO)TS7 MS_Class=23
Mass test: TS0(OOOOOOOO)TS7 MS_Class=24
Mass test: TS0(OOOOOOOO)TS7 MS_Class=25
Mass test: TS0(OOOOOOOO)TS7 MS_Class=26
Mass test: TS0(OOOOOOOO)TS7 MS_Class=27
Mass test: TS0(OOOOOOOO)TS7 MS_Class=28
Mass test: TS0(OOOOOOOO)TS7 MS_Class=29
Mass test: TS0(OOOOOOOO)TS7 MS_Class=30
Mass test: TS0(OOOOOOOO)TS7 MS_Class=31
Mass test: TS0(OOOOOOOO)TS7 MS_Class=32
Mass test: TS0(OOOOOOOO)TS7 MS_Class=33
Mass test: TS0(OOOOOOOO)TS7 MS_Class=34
Mass test: TS0(OOOOOOOO)TS7 MS_Class=35
Mass test: TS0(OOOOOOOO)TS7 MS_Class=36
Mass test: TS0(OOOOOOOO)TS7 MS_Class=37
Mass test: TS0(OOOOOOOO)TS7 MS_Class=38
Mass test: TS0(OOOOOOOO)TS7 MS_Class=39
Mass test: TS0(OOOOOOOO)TS7 MS_Class=40
Mass test: TS0(OOOOOOOO)TS7 MS_Class=41
Mass test: TS0(OOOOOOOO)TS7 MS_Class=42
Mass test: TS0(OOOOOOOO)TS7 MS_Class=43
Mass test: TS0(OOOOOOOO)TS7 MS_Class=44
Mass test: TS0(OOOOOOOO)TS7 MS_Class=45
Going to test assignment with many TBF, algorithm A class 1..1 (UL and DL)
TBF[0] class 1 reserves ...C....
TBF[0] class 1 reserves ....C...
TBF[0] class 1 reserves .....C..
TBF[0] class 1 reserves ......C.
TBF[0] class 1 reserves .......C
TBF[1] class 1 reserves ...C....
TBF[1] class 1 reserves ....C...
TBF[1] class 1 reserves .....C..
TBF[1] class 1 reserves ......C.
TBF[1] class 1 reserves .......C
TBF[2] class 1 reserves ...C....
TBF[2] class 1 reserves ....C...
TBF[2] class 1 reserves .....C..
TBF[2] class 1 reserves ......C.
TBF[2] class 1 reserves .......C
TBF[3] class 1 reserves ...C....
TBF[3] class 1 reserves ....C...
TBF[3] class 1 reserves .....C..
TBF[3] class 1 reserves ......C.
TBF[3] class 1 reserves .......C
TBF[4] class 1 reserves ...C....
TBF[4] class 1 reserves ....C...
TBF[4] class 1 reserves .....C..
TBF[4] class 1 reserves ......C.
TBF[4] class 1 reserves .......C
TBF[5] class 1 reserves ...C....
TBF[5] class 1 reserves ....C...
TBF[5] class 1 reserves .....C..
TBF[5] class 1 reserves ......C.
TBF[5] class 1 reserves .......C
TBF[6] class 1 reserves ...C....
TBF[6] class 1 reserves ....C...
TBF[6] class 1 reserves .....C..
TBF[6] class 1 reserves ......C.
TBF[6] class 1 reserves .......C
Successfully allocated 35 UL TBFs, algorithm A class 1..1 (UL and DL)
Going to test assignment with many TBF, algorithm B class 10..10 (UL and DL)
TBF[0] class 10 reserves ...DDCD.
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[1] class 10 reserves .....DCC
TBF[2] class 10 reserves ...DCC..
TBF[3] class 10 reserves .....DCC
TBF[4] class 10 reserves ...DCC..
TBF[5] class 10 reserves .....DCC
TBF[6] class 10 reserves ...DCC..
TBF[7] class 10 reserves .....DCC
TBF[8] class 10 reserves ...DCC..
TBF[9] class 10 reserves .....DCC
TBF[10] class 10 reserves ...DCC..
TBF[11] class 10 reserves .....DCC
TBF[12] class 10 reserves ...DCC..
TBF[13] class 10 reserves .....DCC
TBF[14] class 10 reserves ...CC...
Successfully allocated 15 UL TBFs, algorithm B class 10..10 (UL and DL)
Going to test assignment with many TBF, algorithm B class 12..12 (UL and DL)
TBF[0] class 12 reserves ...DDCD.
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[1] class 12 reserves .....DCC
TBF[2] class 12 reserves ...DCC..
TBF[3] class 12 reserves .....DCC
TBF[4] class 12 reserves ...DCC..
TBF[5] class 12 reserves .....DCC
TBF[6] class 12 reserves ...DCC..
TBF[7] class 12 reserves .....DCC
TBF[8] class 12 reserves ...DCC..
TBF[9] class 12 reserves .....DCC
TBF[10] class 12 reserves ...DCC..
TBF[11] class 12 reserves .....DCC
TBF[12] class 12 reserves ...DCC..
TBF[13] class 12 reserves .....DCC
TBF[14] class 12 reserves ...CC...
Successfully allocated 15 UL TBFs, algorithm B class 12..12 (UL and DL)
Going to test assignment with many TBF, algorithm B class 1..12 (UL and DL)
TBF[0] class 1 reserves ...C....
TBF[1] class 2 reserves ....DC..
TBF[2] class 3 reserves ......DC
TBF[3] class 4 reserves ...DCD..
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[4] class 5 reserves ......CC
TBF[5] class 6 reserves ...CC...
TBF[6] class 7 reserves .....CC.
TBF[7] class 8 reserves ....DDCD
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[8] class 9 reserves ...DCC..
TBF[9] class 10 reserves .....DCC
TBF[10] class 11 reserves ...DCC..
TBF[11] class 12 reserves .....DCC
TBF[12] class 1 reserves ...C....
TBF[13] class 2 reserves ......DC
TBF[14] class 3 reserves ...DC...
TBF[15] class 4 reserves ....DCD.
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[16] class 5 reserves ...CC...
TBF[17] class 6 reserves ......CC
TBF[18] class 7 reserves ...CC...
TBF[19] class 8 reserves ....DDCD
TBF[20] class 9 reserves .....DDC
TBF[21] class 10 reserves ...DDCD.
TBF[22] class 11 reserves ...DDCD.
Successfully allocated 23 UL TBFs, algorithm B class 1..12 (UL and DL)
Going to test assignment with many TBF, algorithm B class 1..46 (UL and DL)
TBF[0] class 1 reserves ...C....
TBF[1] class 2 reserves ....DC..
TBF[2] class 3 reserves ......DC
TBF[3] class 4 reserves ...DCD..
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[4] class 5 reserves ......CC
TBF[5] class 6 reserves ...CC...
TBF[6] class 7 reserves .....CC.
TBF[7] class 8 reserves ....DDCD
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[8] class 9 reserves ...DCC..
TBF[9] class 10 reserves .....DCC
TBF[10] class 11 reserves ...DCC..
TBF[11] class 12 reserves .....DCC
TBF[12] class 13 reserves ...CCC..
TBF[13] class 14 reserves ...CCCC.
TBF[14] class 15 reserves ...CCCCC
TBF[15] class 16 reserves ...CDDDC
TBF[16] class 17 reserves ...CDDDC
Successfully allocated 17 UL TBFs, algorithm B class 1..46 (UL and DL)
Going to test assignment with many TBF, algorithm dynamic class 1..46 (UL and DL)
TBF[0] class 1 reserves ...C....
TBF[1] class 2 reserves ....DC..
TBF[2] class 3 reserves ......DC
TBF[3] class 4 reserves ...DCD..
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[4] class 5 reserves ......CC
TBF[5] class 6 reserves ...CC...
TBF[6] class 7 reserves .....CC.
TBF[7] class 8 reserves ....DDCD
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[8] class 9 reserves ...DCC..
TBF[9] class 10 reserves .....DCC
TBF[10] class 11 reserves ...DCC..
TBF[11] class 12 reserves .....DCC
TBF[12] class 13 reserves ...CCC..
TBF[13] class 14 reserves ...CCCC.
TBF[14] class 15 reserves ...CCCCC
TBF[15] class 16 reserves ...CDDDC
TBF[16] class 17 reserves ...CDDDC
Successfully allocated 17 UL TBFs, algorithm dynamic class 1..46 (UL and DL)
Going to test assignment with many TBF, algorithm A class 1..1 (DL and UL)
TBF[0] class 1 reserves ...C....
TBF[0] class 1 reserves ....C...
TBF[0] class 1 reserves .....C..
TBF[0] class 1 reserves ......C.
TBF[0] class 1 reserves .......C
TBF[1] class 1 reserves ...C....
TBF[1] class 1 reserves ....C...
TBF[1] class 1 reserves .....C..
TBF[1] class 1 reserves ......C.
TBF[1] class 1 reserves .......C
TBF[2] class 1 reserves ...C....
TBF[2] class 1 reserves ....C...
TBF[2] class 1 reserves .....C..
TBF[2] class 1 reserves ......C.
TBF[2] class 1 reserves .......C
TBF[3] class 1 reserves ...C....
TBF[3] class 1 reserves ....C...
TBF[3] class 1 reserves .....C..
TBF[3] class 1 reserves ......C.
TBF[3] class 1 reserves .......C
TBF[4] class 1 reserves ...C....
TBF[4] class 1 reserves ....C...
TBF[4] class 1 reserves .....C..
TBF[4] class 1 reserves ......C.
TBF[4] class 1 reserves .......C
TBF[5] class 1 reserves ...C....
TBF[5] class 1 reserves ....C...
TBF[5] class 1 reserves .....C..
TBF[5] class 1 reserves ......C.
TBF[5] class 1 reserves .......C
TBF[6] class 1 reserves ...C....
TBF[6] class 1 reserves ....C...
TBF[6] class 1 reserves .....C..
TBF[6] class 1 reserves ......C.
TBF[6] class 1 reserves .......C
Successfully allocated 35 UL TBFs, algorithm A class 1..1 (DL and UL)
Going to test assignment with many TBF, algorithm B class 10..10 (DL and UL)
TBF[0] class 10 reserves ...DDCD.
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[1] class 10 reserves .....DCC
TBF[2] class 10 reserves ...DCC..
TBF[3] class 10 reserves .....DCC
TBF[4] class 10 reserves ...DCC..
TBF[5] class 10 reserves .....DCC
TBF[6] class 10 reserves ...DCC..
TBF[7] class 10 reserves .....DCC
TBF[8] class 10 reserves ...DCC..
TBF[9] class 10 reserves .....DCC
TBF[10] class 10 reserves ...DCC..
TBF[11] class 10 reserves .....DCC
TBF[12] class 10 reserves ...DCC..
TBF[13] class 10 reserves .....DCC
TBF[14] class 10 reserves ...CC...
Successfully allocated 15 UL TBFs, algorithm B class 10..10 (DL and UL)
Going to test assignment with many TBF, algorithm dynamic class 10..10 (DL and UL)
TBF[0] class 10 reserves ...DDCD.
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[1] class 10 reserves .....DCC
TBF[2] class 10 reserves ...DCC..
TBF[3] class 10 reserves .....DCC
TBF[4] class 10 reserves ...DCC..
TBF[5] class 10 reserves .....DCC
TBF[6] class 10 reserves ...DCC..
TBF[7] class 10 reserves .....DCC
TBF[8] class 10 reserves ...DCC..
TBF[9] class 10 reserves .....DCC
TBF[10] class 10 reserves ...DCC..
TBF[11] class 10 reserves .....DCC
TBF[12] class 10 reserves ...DCC..
TBF[13] class 10 reserves .....DCC
TBF[14] class 10 reserves ...CC...
Successfully allocated 15 UL TBFs, algorithm dynamic class 10..10 (DL and UL)
Going to test assignment with many TBF, algorithm A class 1..1 (DL after UL)
TBF[0] class 1 reserves ...C....
TBF[0] class 1 reserves ....C...
TBF[0] class 1 reserves .....C..
TBF[0] class 1 reserves ......C.
TBF[0] class 1 reserves .......C
TBF[1] class 1 reserves ...C....
TBF[1] class 1 reserves ....C...
TBF[1] class 1 reserves .....C..
TBF[1] class 1 reserves ......C.
TBF[1] class 1 reserves .......C
TBF[2] class 1 reserves ...C....
TBF[2] class 1 reserves ....C...
TBF[2] class 1 reserves .....C..
TBF[2] class 1 reserves ......C.
TBF[2] class 1 reserves .......C
TBF[3] class 1 reserves ...C....
TBF[3] class 1 reserves ....C...
TBF[3] class 1 reserves .....C..
TBF[3] class 1 reserves ......C.
TBF[3] class 1 reserves .......C
TBF[4] class 1 reserves ...C....
TBF[4] class 1 reserves ....C...
TBF[4] class 1 reserves .....C..
TBF[4] class 1 reserves ......C.
TBF[4] class 1 reserves .......C
TBF[5] class 1 reserves ...C....
TBF[5] class 1 reserves ....C...
TBF[5] class 1 reserves .....C..
TBF[5] class 1 reserves ......C.
TBF[5] class 1 reserves .......C
TBF[6] class 1 reserves ...C....
TBF[6] class 1 reserves ....C...
TBF[6] class 1 reserves .....C..
TBF[6] class 1 reserves ......C.
TBF[6] class 1 reserves .......C
TBF[7] class 1 reserves ...C....
TBF[7] class 1 reserves ....C...
TBF[7] class 1 reserves .....C..
TBF[7] class 1 reserves ......C.
TBF[7] class 1 reserves .......C
TBF[8] class 1 reserves ...C....
TBF[8] class 1 reserves ....C...
TBF[8] class 1 reserves .....C..
TBF[8] class 1 reserves ......C.
TBF[8] class 1 reserves .......C
TBF[9] class 1 reserves ...C....
TBF[9] class 1 reserves ....C...
TBF[9] class 1 reserves .....C..
TBF[9] class 1 reserves ......C.
TBF[9] class 1 reserves .......C
TBF[10] class 1 reserves ...C....
TBF[10] class 1 reserves ....C...
TBF[10] class 1 reserves .....C..
TBF[10] class 1 reserves ......C.
TBF[10] class 1 reserves .......C
TBF[11] class 1 reserves ...C....
TBF[11] class 1 reserves ....C...
TBF[11] class 1 reserves .....C..
TBF[11] class 1 reserves ......C.
TBF[11] class 1 reserves .......C
TBF[12] class 1 reserves ...C....
TBF[12] class 1 reserves ....C...
TBF[12] class 1 reserves .....C..
TBF[12] class 1 reserves ......C.
TBF[12] class 1 reserves .......C
TBF[13] class 1 reserves ...C....
TBF[13] class 1 reserves ....C...
TBF[13] class 1 reserves .....C..
TBF[13] class 1 reserves ......C.
TBF[13] class 1 reserves .......C
TBF[14] class 1 reserves ...C....
TBF[14] class 1 reserves ....C...
TBF[14] class 1 reserves .....C..
TBF[14] class 1 reserves ......C.
TBF[14] class 1 reserves .......C
TBF[15] class 1 reserves ...C....
TBF[15] class 1 reserves ....C...
TBF[15] class 1 reserves .....C..
TBF[15] class 1 reserves ......C.
TBF[15] class 1 reserves .......C
TBF[16] class 1 reserves ...C....
TBF[16] class 1 reserves ....C...
TBF[16] class 1 reserves .....C..
TBF[16] class 1 reserves ......C.
TBF[16] class 1 reserves .......C
TBF[17] class 1 reserves ...C....
TBF[17] class 1 reserves ....C...
TBF[17] class 1 reserves .....C..
TBF[17] class 1 reserves ......C.
TBF[17] class 1 reserves .......C
TBF[18] class 1 reserves ...C....
TBF[18] class 1 reserves ....C...
TBF[18] class 1 reserves .....C..
TBF[18] class 1 reserves ......C.
TBF[18] class 1 reserves .......C
TBF[19] class 1 reserves ...C....
TBF[19] class 1 reserves ....C...
TBF[19] class 1 reserves .....C..
TBF[19] class 1 reserves ......C.
TBF[19] class 1 reserves .......C
TBF[20] class 1 reserves ...C....
TBF[20] class 1 reserves ....C...
TBF[20] class 1 reserves .....C..
TBF[20] class 1 reserves ......C.
TBF[20] class 1 reserves .......C
TBF[21] class 1 reserves ...C....
TBF[21] class 1 reserves ....C...
TBF[21] class 1 reserves .....C..
TBF[21] class 1 reserves ......C.
TBF[21] class 1 reserves .......C
TBF[22] class 1 reserves ...C....
TBF[22] class 1 reserves ....C...
TBF[22] class 1 reserves .....C..
TBF[22] class 1 reserves ......C.
TBF[22] class 1 reserves .......C
TBF[23] class 1 reserves ...C....
TBF[23] class 1 reserves ....C...
TBF[23] class 1 reserves .....C..
TBF[23] class 1 reserves ......C.
TBF[23] class 1 reserves .......C
TBF[24] class 1 reserves ...C....
TBF[24] class 1 reserves ....C...
TBF[24] class 1 reserves .....C..
TBF[24] class 1 reserves ......C.
TBF[24] class 1 reserves .......C
TBF[25] class 1 reserves ...C....
TBF[25] class 1 reserves ....C...
TBF[25] class 1 reserves .....C..
TBF[25] class 1 reserves ......C.
TBF[25] class 1 reserves .......C
TBF[26] class 1 reserves ...C....
TBF[26] class 1 reserves ....C...
TBF[26] class 1 reserves .....C..
TBF[26] class 1 reserves ......C.
TBF[26] class 1 reserves .......C
TBF[27] class 1 reserves ...C....
TBF[27] class 1 reserves ....C...
TBF[27] class 1 reserves .....C..
TBF[27] class 1 reserves ......C.
TBF[27] class 1 reserves .......C
TBF[28] class 1 reserves ...C....
TBF[28] class 1 reserves ....C...
TBF[28] class 1 reserves .....C..
TBF[28] class 1 reserves ......C.
TBF[28] class 1 reserves .......C
TBF[29] class 1 reserves ...C....
TBF[29] class 1 reserves ....C...
TBF[29] class 1 reserves .....C..
TBF[29] class 1 reserves ......C.
TBF[29] class 1 reserves .......C
TBF[30] class 1 reserves ...C....
TBF[30] class 1 reserves ....C...
TBF[30] class 1 reserves .....C..
TBF[30] class 1 reserves ......C.
TBF[30] class 1 reserves .......C
TBF[31] class 1 reserves ...C....
TBF[31] class 1 reserves ....C...
TBF[31] class 1 reserves .....C..
TBF[31] class 1 reserves ......C.
TBF[31] class 1 reserves .......C
Successfully allocated 160 UL TBFs, algorithm A class 1..1 (DL after UL)
Going to test assignment with many TBF, algorithm B class 10..10 (DL after UL)
TBF[0] class 10 reserves ...DDCD.
TBF[1] class 10 reserves .....DCD
TBF[2] class 10 reserves ...DCD..
TBF[3] class 10 reserves .....DCD
TBF[4] class 10 reserves ...DCD..
TBF[5] class 10 reserves .....DCD
TBF[6] class 10 reserves ...DCD..
TBF[7] class 10 reserves .....DCD
TBF[8] class 10 reserves ...DCD..
TBF[9] class 10 reserves .....DCD
TBF[10] class 10 reserves ...DCD..
TBF[11] class 10 reserves .....DCD
TBF[12] class 10 reserves ...DCD..
TBF[13] class 10 reserves .....DCD
TBF[14] class 10 reserves ...DCD..
TBF[15] class 10 reserves .....DCD
TBF[16] class 10 reserves ...DCD..
TBF[17] class 10 reserves .....DCD
TBF[18] class 10 reserves ...DCD..
TBF[19] class 10 reserves .....DCD
TBF[20] class 10 reserves ...DCD..
TBF[21] class 10 reserves .....DCD
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[22] class 10 reserves ...CD...
TBF[23] class 10 reserves .....DCD
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[24] class 10 reserves ...CD...
TBF[25] class 10 reserves ...CD...
TBF[26] class 10 reserves .....DCD
TBF[27] class 10 reserves ...CD...
TBF[28] class 10 reserves ....DCD.
TBF[29] class 10 reserves .....DCD
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[30] class 10 reserves ...CD...
TBF[31] class 10 reserves ...CD...
Successfully allocated 32 UL TBFs, algorithm B class 10..10 (DL after UL)
Going to test assignment with many TBF, algorithm dynamic class 10..10 (DL after UL)
TBF[0] class 10 reserves ...DDCD.
TBF[1] class 10 reserves .....DCD
TBF[2] class 10 reserves ...DCD..
TBF[3] class 10 reserves .....DCD
TBF[4] class 10 reserves ...DCD..
TBF[5] class 10 reserves .....DCD
TBF[6] class 10 reserves ...DCD..
TBF[7] class 10 reserves .....DCD
TBF[8] class 10 reserves ...DCD..
TBF[9] class 10 reserves .....DCD
TBF[10] class 10 reserves ...DCD..
TBF[11] class 10 reserves .....DCD
TBF[12] class 10 reserves ...DCD..
TBF[13] class 10 reserves .....DCD
TBF[14] class 10 reserves ...DCD..
TBF[15] class 10 reserves .....DCD
TBF[16] class 10 reserves ...DCD..
TBF[17] class 10 reserves .....DCD
TBF[18] class 10 reserves ...DCD..
TBF[19] class 10 reserves .....DCD
TBF[20] class 10 reserves ...DCD..
TBF[21] class 10 reserves .....DCD
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[22] class 10 reserves ...CD...
TBF[23] class 10 reserves .....DCD
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[24] class 10 reserves ...CD...
TBF[25] class 10 reserves ...CD...
TBF[26] class 10 reserves .....DCD
TBF[27] class 10 reserves ...CD...
TBF[28] class 10 reserves ....DCD.
TBF[29] class 10 reserves .....DCD
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[30] class 10 reserves ...CD...
TBF[31] class 10 reserves ...CD...
TBF[2] class 10 reserves ......C.
TBF[1] class 10 reserves ...C....
TBF[0] class 10 reserves .......C
TBF[3] class 10 reserves ...C....
TBF[2] class 10 reserves .......C
TBF[5] class 10 reserves ...C....
TBF[4] class 10 reserves .......C
TBF[7] class 10 reserves ...C....
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[4] class 10 reserves ......C.
TBF[6] class 10 reserves .......C
TBF[9] class 10 reserves ...C....
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[1] class 10 reserves ....C...
TBF[6] class 10 reserves ......C.
TBF[8] class 10 reserves .......C
TBF[11] class 10 reserves ...C....
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[3] class 10 reserves ....C...
TBF[8] class 10 reserves ......C.
TBF[10] class 10 reserves .......C
TBF[13] class 10 reserves ...C....
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[5] class 10 reserves ....C...
TBF[10] class 10 reserves ......C.
TBF[12] class 10 reserves .......C
TBF[15] class 10 reserves ...C....
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[7] class 10 reserves ....C...
TBF[12] class 10 reserves ......C.
TBF[14] class 10 reserves .......C
TBF[17] class 10 reserves ...C....
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[9] class 10 reserves ....C...
TBF[22] class 10 reserves .....C..
TBF[14] class 10 reserves ......C.
TBF[16] class 10 reserves .......C
TBF[19] class 10 reserves ...C....
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[11] class 10 reserves ....C...
TBF[24] class 10 reserves .....C..
TBF[16] class 10 reserves ......C.
TBF[18] class 10 reserves .......C
TBF[21] class 10 reserves ...C....
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[13] class 10 reserves ....C...
TBF[25] class 10 reserves .....C..
TBF[18] class 10 reserves ......C.
TBF[20] class 10 reserves .......C
TBF[23] class 10 reserves ...C....
TBF[15] class 10 reserves ....C...
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[27] class 10 reserves .....C..
TBF[20] class 10 reserves ......C.
TBF[22] class 10 reserves .......C
TBF[26] class 10 reserves ...C....
TBF[17] class 10 reserves ....C...
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[30] class 10 reserves .....C..
TBF[22] class 10 reserves ......C.
TBF[24] class 10 reserves .......C
TBF[28] class 10 reserves ...C....
TBF[19] class 10 reserves ....C...
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[31] class 10 reserves .....C..
TBF[24] class 10 reserves ......C.
TBF[25] class 10 reserves .......C
TBF[29] class 10 reserves ...C....
TBF[21] class 10 reserves ....C...
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[25] class 10 reserves ......C.
TBF[27] class 10 reserves .......C
TBF[23] class 10 reserves ....C...
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[27] class 10 reserves ......C.
TBF[28] class 10 reserves .......C
TBF[26] class 10 reserves ....C...
TBF[30] class 10 reserves ......C.
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[30] class 10 reserves .......C
TBF[29] class 10 reserves ....C...
TBF[31] class 10 reserves ......C.
TBF[31] class 10 reserves .......C
Successfully allocated 101 UL TBFs, algorithm dynamic class 10..10 (DL after UL)
Going to test assignment with many TBF, algorithm A class 1..1 (UL after DL)
TBF[0] class 1 reserves ...U....
TBF[0] class 1 reserves ....U...
TBF[0] class 1 reserves .....U..
TBF[0] class 1 reserves ......U.
TBF[0] class 1 reserves .......U
TBF[1] class 1 reserves ...U....
TBF[1] class 1 reserves ....U...
TBF[1] class 1 reserves .....U..
TBF[1] class 1 reserves ......U.
TBF[1] class 1 reserves .......U
TBF[2] class 1 reserves ...U....
TBF[2] class 1 reserves ....U...
TBF[2] class 1 reserves .....U..
TBF[2] class 1 reserves ......U.
TBF[2] class 1 reserves .......U
TBF[3] class 1 reserves ...U....
TBF[3] class 1 reserves ....U...
TBF[3] class 1 reserves .....U..
TBF[3] class 1 reserves ......U.
TBF[3] class 1 reserves .......U
TBF[4] class 1 reserves ...U....
TBF[4] class 1 reserves ....U...
TBF[4] class 1 reserves .....U..
TBF[4] class 1 reserves ......U.
TBF[4] class 1 reserves .......U
TBF[5] class 1 reserves ...U....
TBF[5] class 1 reserves ....U...
TBF[5] class 1 reserves .....U..
TBF[5] class 1 reserves ......U.
TBF[5] class 1 reserves .......U
TBF[6] class 1 reserves ...U....
TBF[6] class 1 reserves ....U...
TBF[6] class 1 reserves .....U..
TBF[6] class 1 reserves ......U.
TBF[6] class 1 reserves .......U
Successfully allocated 35 UL TBFs, algorithm A class 1..1 (UL after DL)
Going to test assignment with many TBF, algorithm B class 10..10 (UL after DL)
TBF[0] class 10 reserves .....U..
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[1] class 10 reserves ......UU
TBF[2] class 10 reserves ....UU..
TBF[3] class 10 reserves ......UU
TBF[4] class 10 reserves ....UU..
TBF[5] class 10 reserves ......UU
TBF[6] class 10 reserves ....UU..
TBF[7] class 10 reserves ......UU
TBF[8] class 10 reserves ....UU..
TBF[9] class 10 reserves ......UU
TBF[10] class 10 reserves ....UU..
TBF[11] class 10 reserves ......UU
TBF[12] class 10 reserves ....UU..
TBF[13] class 10 reserves ......UU
TBF[14] class 10 reserves ...UU...
Successfully allocated 15 UL TBFs, algorithm B class 10..10 (UL after DL)
Going to test assignment with many TBF, algorithm dynamic class 10..10 (UL after DL)
TBF[0] class 10 reserves .....U..
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[1] class 10 reserves ......UU
TBF[2] class 10 reserves ....UU..
TBF[3] class 10 reserves ......UU
TBF[4] class 10 reserves ....UU..
TBF[5] class 10 reserves ......UU
TBF[6] class 10 reserves ....UU..
TBF[7] class 10 reserves ......UU
TBF[8] class 10 reserves ....UU..
TBF[9] class 10 reserves ......UU
TBF[10] class 10 reserves ....UU..
TBF[11] class 10 reserves ......UU
TBF[12] class 10 reserves ....UU..
TBF[13] class 10 reserves ......UU
TBF[14] class 10 reserves ...UU...
Successfully allocated 15 UL TBFs, algorithm dynamic class 10..10 (UL after DL)
Going to test assignment with many TBF, algorithm A class 1..1 (UL only)
TBF[0] class 1 reserves ...U....
TBF[0] class 1 reserves ....U...
TBF[0] class 1 reserves .....U..
TBF[0] class 1 reserves ......U.
TBF[0] class 1 reserves .......U
TBF[1] class 1 reserves ...U....
TBF[1] class 1 reserves ....U...
TBF[1] class 1 reserves .....U..
TBF[1] class 1 reserves ......U.
TBF[1] class 1 reserves .......U
TBF[2] class 1 reserves ...U....
TBF[2] class 1 reserves ....U...
TBF[2] class 1 reserves .....U..
TBF[2] class 1 reserves ......U.
TBF[2] class 1 reserves .......U
TBF[3] class 1 reserves ...U....
TBF[3] class 1 reserves ....U...
TBF[3] class 1 reserves .....U..
TBF[3] class 1 reserves ......U.
TBF[3] class 1 reserves .......U
TBF[4] class 1 reserves ...U....
TBF[4] class 1 reserves ....U...
TBF[4] class 1 reserves .....U..
TBF[4] class 1 reserves ......U.
TBF[4] class 1 reserves .......U
TBF[5] class 1 reserves ...U....
TBF[5] class 1 reserves ....U...
TBF[5] class 1 reserves .....U..
TBF[5] class 1 reserves ......U.
TBF[5] class 1 reserves .......U
TBF[6] class 1 reserves ...U....
TBF[6] class 1 reserves ....U...
TBF[6] class 1 reserves .....U..
TBF[6] class 1 reserves ......U.
TBF[6] class 1 reserves .......U
Successfully allocated 35 UL TBFs, algorithm A class 1..1 (UL only)
Going to test assignment with many TBF, algorithm B class 10..10 (UL only)
TBF[0] class 10 reserves .....U..
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[1] class 10 reserves ......UU
TBF[2] class 10 reserves ....UU..
TBF[3] class 10 reserves ......UU
TBF[4] class 10 reserves ....UU..
TBF[5] class 10 reserves ......UU
TBF[6] class 10 reserves ....UU..
TBF[7] class 10 reserves ......UU
TBF[8] class 10 reserves ....UU..
TBF[9] class 10 reserves ......UU
TBF[10] class 10 reserves ....UU..
TBF[11] class 10 reserves ......UU
TBF[12] class 10 reserves ....UU..
TBF[13] class 10 reserves ......UU
TBF[14] class 10 reserves ...UU...
Successfully allocated 15 UL TBFs, algorithm B class 10..10 (UL only)
Going to test assignment with many TBF, algorithm dynamic class 10..10 (UL only)
TBF[0] class 10 reserves .....U..
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[1] class 10 reserves ......UU
TBF[2] class 10 reserves ....UU..
TBF[3] class 10 reserves ......UU
TBF[4] class 10 reserves ....UU..
TBF[5] class 10 reserves ......UU
TBF[6] class 10 reserves ....UU..
TBF[7] class 10 reserves ......UU
TBF[8] class 10 reserves ....UU..
TBF[9] class 10 reserves ......UU
TBF[10] class 10 reserves ....UU..
TBF[11] class 10 reserves ......UU
TBF[12] class 10 reserves ....UU..
TBF[13] class 10 reserves ......UU
TBF[14] class 10 reserves ...UU...
TBF[0] class 10 reserves ...U....
TBF[1] class 10 reserves ...U....
TBF[2] class 10 reserves ...U....
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[3] class 10 reserves ...U....
TBF[4] class 10 reserves ...U....
TBF[5] class 10 reserves ...U....
Successfully allocated 21 UL TBFs, algorithm dynamic class 10..10 (UL only)
Going to test assignment with many TBF, algorithm A class 1..1 (DL only)
TBF[0] class 1 reserves ...C....
TBF[0] class 1 reserves ....C...
TBF[0] class 1 reserves .....C..
TBF[0] class 1 reserves ......C.
TBF[0] class 1 reserves .......C
TBF[1] class 1 reserves ...C....
TBF[1] class 1 reserves ....C...
TBF[1] class 1 reserves .....C..
TBF[1] class 1 reserves ......C.
TBF[1] class 1 reserves .......C
TBF[2] class 1 reserves ...C....
TBF[2] class 1 reserves ....C...
TBF[2] class 1 reserves .....C..
TBF[2] class 1 reserves ......C.
TBF[2] class 1 reserves .......C
TBF[3] class 1 reserves ...C....
TBF[3] class 1 reserves ....C...
TBF[3] class 1 reserves .....C..
TBF[3] class 1 reserves ......C.
TBF[3] class 1 reserves .......C
TBF[4] class 1 reserves ...C....
TBF[4] class 1 reserves ....C...
TBF[4] class 1 reserves .....C..
TBF[4] class 1 reserves ......C.
TBF[4] class 1 reserves .......C
TBF[5] class 1 reserves ...C....
TBF[5] class 1 reserves ....C...
TBF[5] class 1 reserves .....C..
TBF[5] class 1 reserves ......C.
TBF[5] class 1 reserves .......C
TBF[6] class 1 reserves ...C....
TBF[6] class 1 reserves ....C...
TBF[6] class 1 reserves .....C..
TBF[6] class 1 reserves ......C.
TBF[6] class 1 reserves .......C
TBF[7] class 1 reserves ...C....
TBF[7] class 1 reserves ....C...
TBF[7] class 1 reserves .....C..
TBF[7] class 1 reserves ......C.
TBF[7] class 1 reserves .......C
TBF[8] class 1 reserves ...C....
TBF[8] class 1 reserves ....C...
TBF[8] class 1 reserves .....C..
TBF[8] class 1 reserves ......C.
TBF[8] class 1 reserves .......C
TBF[9] class 1 reserves ...C....
TBF[9] class 1 reserves ....C...
TBF[9] class 1 reserves .....C..
TBF[9] class 1 reserves ......C.
TBF[9] class 1 reserves .......C
TBF[10] class 1 reserves ...C....
TBF[10] class 1 reserves ....C...
TBF[10] class 1 reserves .....C..
TBF[10] class 1 reserves ......C.
TBF[10] class 1 reserves .......C
TBF[11] class 1 reserves ...C....
TBF[11] class 1 reserves ....C...
TBF[11] class 1 reserves .....C..
TBF[11] class 1 reserves ......C.
TBF[11] class 1 reserves .......C
TBF[12] class 1 reserves ...C....
TBF[12] class 1 reserves ....C...
TBF[12] class 1 reserves .....C..
TBF[12] class 1 reserves ......C.
TBF[12] class 1 reserves .......C
TBF[13] class 1 reserves ...C....
TBF[13] class 1 reserves ....C...
TBF[13] class 1 reserves .....C..
TBF[13] class 1 reserves ......C.
TBF[13] class 1 reserves .......C
TBF[14] class 1 reserves ...C....
TBF[14] class 1 reserves ....C...
TBF[14] class 1 reserves .....C..
TBF[14] class 1 reserves ......C.
TBF[14] class 1 reserves .......C
TBF[15] class 1 reserves ...C....
TBF[15] class 1 reserves ....C...
TBF[15] class 1 reserves .....C..
TBF[15] class 1 reserves ......C.
TBF[15] class 1 reserves .......C
TBF[16] class 1 reserves ...C....
TBF[16] class 1 reserves ....C...
TBF[16] class 1 reserves .....C..
TBF[16] class 1 reserves ......C.
TBF[16] class 1 reserves .......C
TBF[17] class 1 reserves ...C....
TBF[17] class 1 reserves ....C...
TBF[17] class 1 reserves .....C..
TBF[17] class 1 reserves ......C.
TBF[17] class 1 reserves .......C
TBF[18] class 1 reserves ...C....
TBF[18] class 1 reserves ....C...
TBF[18] class 1 reserves .....C..
TBF[18] class 1 reserves ......C.
TBF[18] class 1 reserves .......C
TBF[19] class 1 reserves ...C....
TBF[19] class 1 reserves ....C...
TBF[19] class 1 reserves .....C..
TBF[19] class 1 reserves ......C.
TBF[19] class 1 reserves .......C
TBF[20] class 1 reserves ...C....
TBF[20] class 1 reserves ....C...
TBF[20] class 1 reserves .....C..
TBF[20] class 1 reserves ......C.
TBF[20] class 1 reserves .......C
TBF[21] class 1 reserves ...C....
TBF[21] class 1 reserves ....C...
TBF[21] class 1 reserves .....C..
TBF[21] class 1 reserves ......C.
TBF[21] class 1 reserves .......C
TBF[22] class 1 reserves ...C....
TBF[22] class 1 reserves ....C...
TBF[22] class 1 reserves .....C..
TBF[22] class 1 reserves ......C.
TBF[22] class 1 reserves .......C
TBF[23] class 1 reserves ...C....
TBF[23] class 1 reserves ....C...
TBF[23] class 1 reserves .....C..
TBF[23] class 1 reserves ......C.
TBF[23] class 1 reserves .......C
TBF[24] class 1 reserves ...C....
TBF[24] class 1 reserves ....C...
TBF[24] class 1 reserves .....C..
TBF[24] class 1 reserves ......C.
TBF[24] class 1 reserves .......C
TBF[25] class 1 reserves ...C....
TBF[25] class 1 reserves ....C...
TBF[25] class 1 reserves .....C..
TBF[25] class 1 reserves ......C.
TBF[25] class 1 reserves .......C
TBF[26] class 1 reserves ...C....
TBF[26] class 1 reserves ....C...
TBF[26] class 1 reserves .....C..
TBF[26] class 1 reserves ......C.
TBF[26] class 1 reserves .......C
TBF[27] class 1 reserves ...C....
TBF[27] class 1 reserves ....C...
TBF[27] class 1 reserves .....C..
TBF[27] class 1 reserves ......C.
TBF[27] class 1 reserves .......C
TBF[28] class 1 reserves ...C....
TBF[28] class 1 reserves ....C...
TBF[28] class 1 reserves .....C..
TBF[28] class 1 reserves ......C.
TBF[28] class 1 reserves .......C
TBF[29] class 1 reserves ...C....
TBF[29] class 1 reserves ....C...
TBF[29] class 1 reserves .....C..
TBF[29] class 1 reserves ......C.
TBF[29] class 1 reserves .......C
TBF[30] class 1 reserves ...C....
TBF[30] class 1 reserves ....C...
TBF[30] class 1 reserves .....C..
TBF[30] class 1 reserves ......C.
TBF[30] class 1 reserves .......C
TBF[31] class 1 reserves ...C....
TBF[31] class 1 reserves ....C...
TBF[31] class 1 reserves .....C..
TBF[31] class 1 reserves ......C.
TBF[31] class 1 reserves .......C
Successfully allocated 160 UL TBFs, algorithm A class 1..1 (DL only)
Going to test assignment with many TBF, algorithm B class 10..10 (DL only)
TBF[0] class 10 reserves ...DDCD.
TBF[1] class 10 reserves .....DCD
TBF[2] class 10 reserves ...DCD..
TBF[3] class 10 reserves .....DCD
TBF[4] class 10 reserves ...DCD..
TBF[5] class 10 reserves .....DCD
TBF[6] class 10 reserves ...DCD..
TBF[7] class 10 reserves .....DCD
TBF[8] class 10 reserves ...DCD..
TBF[9] class 10 reserves .....DCD
TBF[10] class 10 reserves ...DCD..
TBF[11] class 10 reserves .....DCD
TBF[12] class 10 reserves ...DCD..
TBF[13] class 10 reserves .....DCD
TBF[14] class 10 reserves ...DCD..
TBF[15] class 10 reserves .....DCD
TBF[16] class 10 reserves ...DCD..
TBF[17] class 10 reserves .....DCD
TBF[18] class 10 reserves ...DCD..
TBF[19] class 10 reserves .....DCD
TBF[20] class 10 reserves ...DCD..
TBF[21] class 10 reserves .....DCD
TBF[22] class 10 reserves ...CD...
TBF[23] class 10 reserves .....DCD
TBF[24] class 10 reserves ...CD...
TBF[25] class 10 reserves ...CD...
TBF[26] class 10 reserves .....DCD
TBF[27] class 10 reserves ...CD...
TBF[28] class 10 reserves ....DCD.
TBF[29] class 10 reserves .....DCD
TBF[30] class 10 reserves ...CD...
TBF[31] class 10 reserves ...CD...
Successfully allocated 32 UL TBFs, algorithm B class 10..10 (DL only)
Going to test assignment with many TBF, algorithm dynamic class 10..10 (DL only)
TBF[0] class 10 reserves ...DDCD.
TBF[1] class 10 reserves .....DCD
TBF[2] class 10 reserves ...DCD..
TBF[3] class 10 reserves .....DCD
TBF[4] class 10 reserves ...DCD..
TBF[5] class 10 reserves .....DCD
TBF[6] class 10 reserves ...DCD..
TBF[7] class 10 reserves .....DCD
TBF[8] class 10 reserves ...DCD..
TBF[9] class 10 reserves .....DCD
TBF[10] class 10 reserves ...DCD..
TBF[11] class 10 reserves .....DCD
TBF[12] class 10 reserves ...DCD..
TBF[13] class 10 reserves .....DCD
TBF[14] class 10 reserves ...DCD..
TBF[15] class 10 reserves .....DCD
TBF[16] class 10 reserves ...DCD..
TBF[17] class 10 reserves .....DCD
TBF[18] class 10 reserves ...DCD..
TBF[19] class 10 reserves .....DCD
TBF[20] class 10 reserves ...DCD..
TBF[21] class 10 reserves .....DCD
TBF[22] class 10 reserves ...CD...
TBF[23] class 10 reserves .....DCD
TBF[24] class 10 reserves ...CD...
TBF[25] class 10 reserves ...CD...
TBF[26] class 10 reserves .....DCD
TBF[27] class 10 reserves ...CD...
TBF[28] class 10 reserves ....DCD.
TBF[29] class 10 reserves .....DCD
TBF[30] class 10 reserves ...CD...
TBF[31] class 10 reserves ...CD...
TBF[1] class 10 reserves ...C....
TBF[0] class 10 reserves .......C
TBF[3] class 10 reserves ...C....
TBF[2] class 10 reserves .......C
TBF[5] class 10 reserves ...C....
TBF[2] class 10 reserves ......C.
TBF[4] class 10 reserves .......C
TBF[7] class 10 reserves ...C....
TBF[4] class 10 reserves ......C.
TBF[6] class 10 reserves .......C
TBF[9] class 10 reserves ...C....
TBF[1] class 10 reserves ....C...
TBF[6] class 10 reserves ......C.
TBF[8] class 10 reserves .......C
TBF[11] class 10 reserves ...C....
TBF[3] class 10 reserves ....C...
TBF[8] class 10 reserves ......C.
TBF[10] class 10 reserves .......C
TBF[13] class 10 reserves ...C....
TBF[5] class 10 reserves ....C...
TBF[10] class 10 reserves ......C.
TBF[12] class 10 reserves .......C
TBF[15] class 10 reserves ...C....
TBF[7] class 10 reserves ....C...
TBF[12] class 10 reserves ......C.
TBF[14] class 10 reserves .......C
TBF[17] class 10 reserves ...C....
TBF[9] class 10 reserves ....C...
TBF[22] class 10 reserves .....C..
TBF[14] class 10 reserves ......C.
TBF[16] class 10 reserves .......C
TBF[19] class 10 reserves ...C....
TBF[11] class 10 reserves ....C...
TBF[24] class 10 reserves .....C..
TBF[16] class 10 reserves ......C.
TBF[18] class 10 reserves .......C
TBF[21] class 10 reserves ...C....
TBF[13] class 10 reserves ....C...
TBF[25] class 10 reserves .....C..
TBF[18] class 10 reserves ......C.
TBF[20] class 10 reserves .......C
TBF[23] class 10 reserves ...C....
TBF[15] class 10 reserves ....C...
TBF[27] class 10 reserves .....C..
TBF[20] class 10 reserves ......C.
TBF[22] class 10 reserves .......C
TBF[26] class 10 reserves ...C....
TBF[17] class 10 reserves ....C...
TBF[30] class 10 reserves .....C..
TBF[22] class 10 reserves ......C.
TBF[24] class 10 reserves .......C
TBF[28] class 10 reserves ...C....
TBF[19] class 10 reserves ....C...
TBF[31] class 10 reserves .....C..
TBF[24] class 10 reserves ......C.
TBF[25] class 10 reserves .......C
TBF[29] class 10 reserves ...C....
TBF[21] class 10 reserves ....C...
TBF[25] class 10 reserves ......C.
TBF[27] class 10 reserves .......C
TBF[23] class 10 reserves ....C...
TBF[27] class 10 reserves ......C.
TBF[28] class 10 reserves .......C
TBF[26] class 10 reserves ....C...
TBF[30] class 10 reserves ......C.
TBF[30] class 10 reserves .......C
TBF[29] class 10 reserves ....C...
TBF[31] class 10 reserves ......C.
TBF[31] class 10 reserves .......C
Successfully allocated 101 UL TBFs, algorithm dynamic class 10..10 (DL only)
Going to test assignment with many connections, algorithm A
TBF[0] class 1 reserves ...C....
TBF[0] class 2 reserves ....C...
TBF[0] class 3 reserves .....C..
TBF[0] class 4 reserves ......C.
TBF[0] class 5 reserves .......C
TBF[1] class 6 reserves ...C....
TBF[1] class 7 reserves ....C...
TBF[1] class 8 reserves .....C..
TBF[1] class 9 reserves ......C.
TBF[1] class 10 reserves .......C
TBF[2] class 11 reserves ...C....
TBF[2] class 12 reserves ....C...
TBF[2] class 13 reserves .....C..
TBF[2] class 14 reserves ......C.
TBF[2] class 15 reserves .......C
TBF[3] class 16 reserves ...C....
TBF[3] class 17 reserves ....C...
TBF[3] class 18 reserves .....C..
TBF[3] class 19 reserves ......C.
TBF[3] class 20 reserves .......C
TBF[4] class 21 reserves ...C....
TBF[4] class 22 reserves ....C...
TBF[4] class 23 reserves .....C..
TBF[4] class 24 reserves ......C.
TBF[4] class 25 reserves .......C
TBF[5] class 26 reserves ...C....
TBF[5] class 27 reserves ....C...
TBF[5] class 28 reserves .....C..
TBF[5] class 29 reserves ......C.
TBF[5] class 30 reserves .......C
TBF[6] class 31 reserves ...C....
TBF[6] class 32 reserves ....C...
TBF[6] class 33 reserves .....C..
TBF[6] class 34 reserves ......C.
TBF[6] class 35 reserves .......C
TBF[7] class 36 reserves ...C....
TBF[7] class 37 reserves ....C...
TBF[7] class 38 reserves .....C..
TBF[7] class 39 reserves ......C.
TBF[7] class 40 reserves .......C
TBF[8] class 41 reserves ...C....
TBF[8] class 42 reserves ....C...
TBF[8] class 43 reserves .....C..
TBF[8] class 44 reserves ......C.
TBF[8] class 45 reserves .......C
TBF[9] class 46 reserves ...C....
TBF[9] class 1 reserves ....C...
TBF[9] class 2 reserves .....C..
TBF[9] class 3 reserves ......C.
TBF[9] class 4 reserves .......C
TBF[10] class 5 reserves ...C....
TBF[10] class 6 reserves ....C...
TBF[10] class 7 reserves .....C..
TBF[10] class 8 reserves ......C.
TBF[10] class 9 reserves .......C
TBF[11] class 10 reserves ...C....
TBF[11] class 11 reserves ....C...
TBF[11] class 12 reserves .....C..
TBF[11] class 13 reserves ......C.
TBF[11] class 14 reserves .......C
TBF[12] class 15 reserves ...C....
TBF[12] class 16 reserves ....C...
TBF[12] class 17 reserves .....C..
TBF[12] class 18 reserves ......C.
TBF[12] class 19 reserves .......C
TBF[13] class 20 reserves ...C....
TBF[13] class 21 reserves ....C...
TBF[13] class 22 reserves .....C..
TBF[13] class 23 reserves ......C.
TBF[13] class 24 reserves .......C
TBF[14] class 25 reserves ...C....
TBF[14] class 26 reserves ....C...
TBF[14] class 27 reserves .....C..
TBF[14] class 28 reserves ......C.
TBF[14] class 29 reserves .......C
TBF[15] class 30 reserves ...C....
TBF[15] class 31 reserves ....C...
TBF[15] class 32 reserves .....C..
TBF[15] class 33 reserves ......C.
TBF[15] class 34 reserves .......C
TBF[16] class 35 reserves ...C....
TBF[16] class 36 reserves ....C...
TBF[16] class 37 reserves .....C..
TBF[16] class 38 reserves ......C.
TBF[16] class 39 reserves .......C
TBF[17] class 40 reserves ...C....
TBF[17] class 41 reserves ....C...
TBF[17] class 42 reserves .....C..
TBF[17] class 43 reserves ......C.
TBF[17] class 44 reserves .......C
TBF[18] class 45 reserves ...C....
TBF[18] class 46 reserves ....C...
TBF[18] class 1 reserves .....C..
TBF[18] class 2 reserves ......C.
TBF[18] class 3 reserves .......C
TBF[19] class 4 reserves ...C....
TBF[19] class 5 reserves ....C...
TBF[19] class 6 reserves .....C..
TBF[19] class 7 reserves ......C.
TBF[19] class 8 reserves .......C
TBF[20] class 9 reserves ...C....
TBF[20] class 10 reserves ....C...
TBF[20] class 11 reserves .....C..
TBF[20] class 12 reserves ......C.
TBF[20] class 13 reserves .......C
TBF[21] class 14 reserves ...C....
TBF[21] class 15 reserves ....C...
TBF[21] class 16 reserves .....C..
TBF[21] class 17 reserves ......C.
TBF[21] class 18 reserves .......C
TBF[22] class 19 reserves ...C....
TBF[22] class 20 reserves ....C...
TBF[22] class 21 reserves .....C..
TBF[22] class 22 reserves ......C.
TBF[22] class 23 reserves .......C
TBF[23] class 24 reserves ...C....
TBF[23] class 25 reserves ....C...
TBF[23] class 26 reserves .....C..
TBF[23] class 27 reserves ......C.
TBF[23] class 28 reserves .......C
TBF[24] class 29 reserves ...C....
TBF[24] class 30 reserves ....C...
TBF[24] class 31 reserves .....C..
TBF[24] class 32 reserves ......C.
TBF[24] class 33 reserves .......C
TBF[25] class 34 reserves ...C....
TBF[25] class 35 reserves ....C...
TBF[25] class 36 reserves .....C..
TBF[25] class 37 reserves ......C.
TBF[25] class 38 reserves .......C
TBF[26] class 39 reserves ...C....
TBF[26] class 40 reserves ....C...
TBF[26] class 41 reserves .....C..
TBF[26] class 42 reserves ......C.
TBF[26] class 43 reserves .......C
TBF[27] class 44 reserves ...C....
TBF[27] class 45 reserves ....C...
TBF[27] class 46 reserves .....C..
TBF[27] class 1 reserves ......C.
TBF[27] class 2 reserves .......C
TBF[28] class 3 reserves ...C....
TBF[28] class 4 reserves ....C...
TBF[28] class 5 reserves .....C..
TBF[28] class 6 reserves ......C.
TBF[28] class 7 reserves .......C
TBF[29] class 8 reserves ...C....
TBF[29] class 9 reserves ....C...
TBF[29] class 10 reserves .....C..
TBF[29] class 11 reserves ......C.
TBF[29] class 12 reserves .......C
TBF[30] class 13 reserves ...C....
TBF[30] class 14 reserves ....C...
TBF[30] class 15 reserves .....C..
TBF[30] class 16 reserves ......C.
TBF[30] class 17 reserves .......C
TBF[31] class 18 reserves ...C....
TBF[31] class 19 reserves ....C...
TBF[31] class 20 reserves .....C..
TBF[31] class 21 reserves ......C.
TBF[31] class 22 reserves .......C
TBF[0] class 1 reserves ...C....
TBF[0] class 2 reserves ....C...
TBF[0] class 3 reserves .....C..
TBF[0] class 4 reserves ......C.
TBF[0] class 5 reserves .......C
TBF[1] class 6 reserves ...C....
TBF[1] class 7 reserves ....C...
TBF[1] class 8 reserves .....C..
TBF[1] class 9 reserves ......C.
TBF[1] class 10 reserves .......C
TBF[2] class 11 reserves ...C....
TBF[2] class 12 reserves ....C...
TBF[2] class 13 reserves .....C..
TBF[2] class 14 reserves ......C.
TBF[2] class 15 reserves .......C
TBF[3] class 16 reserves ...C....
TBF[3] class 17 reserves ....C...
TBF[3] class 18 reserves .....C..
TBF[3] class 19 reserves ......C.
TBF[3] class 20 reserves .......C
TBF[4] class 21 reserves ...C....
TBF[4] class 22 reserves ....C...
TBF[4] class 23 reserves .....C..
TBF[4] class 24 reserves ......C.
TBF[4] class 25 reserves .......C
TBF[5] class 26 reserves ...C....
TBF[5] class 27 reserves ....C...
TBF[5] class 28 reserves .....C..
TBF[5] class 29 reserves ......C.
TBF[5] class 30 reserves .......C
TBF[6] class 31 reserves ...C....
TBF[6] class 32 reserves ....C...
TBF[6] class 33 reserves .....C..
TBF[6] class 34 reserves ......C.
TBF[6] class 35 reserves .......C
TBF[0] class 1 reserves ...C....
TBF[0] class 2 reserves ....C...
TBF[0] class 3 reserves .....C..
TBF[0] class 4 reserves ......C.
TBF[0] class 5 reserves .......C
TBF[1] class 6 reserves ...C....
TBF[1] class 7 reserves ....C...
TBF[1] class 8 reserves .....C..
TBF[1] class 9 reserves ......C.
TBF[1] class 10 reserves .......C
TBF[2] class 11 reserves ...C....
TBF[2] class 12 reserves ....C...
TBF[2] class 13 reserves .....C..
TBF[2] class 14 reserves ......C.
TBF[2] class 15 reserves .......C
TBF[3] class 16 reserves ...C....
TBF[3] class 17 reserves ....C...
TBF[3] class 18 reserves .....C..
TBF[3] class 19 reserves ......C.
TBF[3] class 20 reserves .......C
TBF[4] class 21 reserves ...C....
TBF[4] class 22 reserves ....C...
TBF[4] class 23 reserves .....C..
TBF[4] class 24 reserves ......C.
TBF[4] class 25 reserves .......C
TBF[5] class 26 reserves ...C....
TBF[5] class 27 reserves ....C...
TBF[5] class 28 reserves .....C..
TBF[5] class 29 reserves ......C.
TBF[5] class 30 reserves .......C
TBF[6] class 31 reserves ...C....
TBF[6] class 32 reserves ....C...
TBF[6] class 33 reserves .....C..
TBF[6] class 34 reserves ......C.
TBF[6] class 35 reserves .......C
TBF[7] class 36 reserves ...C....
TBF[7] class 37 reserves ....C...
TBF[7] class 38 reserves .....C..
TBF[7] class 39 reserves ......C.
TBF[7] class 40 reserves .......C
TBF[8] class 41 reserves ...C....
TBF[8] class 42 reserves ....C...
TBF[8] class 43 reserves .....C..
TBF[8] class 44 reserves ......C.
TBF[8] class 45 reserves .......C
TBF[9] class 46 reserves ...C....
TBF[9] class 1 reserves ....C...
TBF[9] class 2 reserves .....C..
TBF[9] class 3 reserves ......C.
TBF[9] class 4 reserves .......C
TBF[10] class 5 reserves ...C....
TBF[10] class 6 reserves ....C...
TBF[10] class 7 reserves .....C..
TBF[10] class 8 reserves ......C.
TBF[10] class 9 reserves .......C
TBF[11] class 10 reserves ...C....
TBF[11] class 11 reserves ....C...
TBF[11] class 12 reserves .....C..
TBF[11] class 13 reserves ......C.
TBF[11] class 14 reserves .......C
TBF[12] class 15 reserves ...C....
TBF[12] class 16 reserves ....C...
TBF[12] class 17 reserves .....C..
TBF[12] class 18 reserves ......C.
TBF[12] class 19 reserves .......C
TBF[13] class 20 reserves ...C....
TBF[13] class 21 reserves ....C...
TBF[13] class 22 reserves .....C..
TBF[13] class 23 reserves ......C.
TBF[13] class 24 reserves .......C
TBF[14] class 25 reserves ...C....
TBF[14] class 26 reserves ....C...
TBF[14] class 27 reserves .....C..
TBF[14] class 28 reserves ......C.
TBF[14] class 29 reserves .......C
TBF[15] class 30 reserves ...C....
TBF[15] class 31 reserves ....C...
TBF[15] class 32 reserves .....C..
TBF[15] class 33 reserves ......C.
TBF[15] class 34 reserves .......C
TBF[16] class 35 reserves ...C....
TBF[16] class 36 reserves ....C...
TBF[16] class 37 reserves .....C..
TBF[16] class 38 reserves ......C.
TBF[16] class 39 reserves .......C
TBF[17] class 40 reserves ...C....
TBF[17] class 41 reserves ....C...
TBF[17] class 42 reserves .....C..
TBF[17] class 43 reserves ......C.
TBF[17] class 44 reserves .......C
TBF[18] class 45 reserves ...C....
TBF[18] class 46 reserves ....C...
TBF[18] class 1 reserves .....C..
TBF[18] class 2 reserves ......C.
TBF[18] class 3 reserves .......C
TBF[19] class 4 reserves ...C....
TBF[19] class 5 reserves ....C...
TBF[19] class 6 reserves .....C..
TBF[19] class 7 reserves ......C.
TBF[19] class 8 reserves .......C
TBF[20] class 9 reserves ...C....
TBF[20] class 10 reserves ....C...
TBF[20] class 11 reserves .....C..
TBF[20] class 12 reserves ......C.
TBF[20] class 13 reserves .......C
TBF[21] class 14 reserves ...C....
TBF[21] class 15 reserves ....C...
TBF[21] class 16 reserves .....C..
TBF[21] class 17 reserves ......C.
TBF[21] class 18 reserves .......C
TBF[22] class 19 reserves ...C....
TBF[22] class 20 reserves ....C...
TBF[22] class 21 reserves .....C..
TBF[22] class 22 reserves ......C.
TBF[22] class 23 reserves .......C
TBF[23] class 24 reserves ...C....
TBF[23] class 25 reserves ....C...
TBF[23] class 26 reserves .....C..
TBF[23] class 27 reserves ......C.
TBF[23] class 28 reserves .......C
TBF[24] class 29 reserves ...C....
TBF[24] class 30 reserves ....C...
TBF[24] class 31 reserves .....C..
TBF[24] class 32 reserves ......C.
TBF[24] class 33 reserves .......C
TBF[25] class 34 reserves ...C....
TBF[25] class 35 reserves ....C...
TBF[25] class 36 reserves .....C..
TBF[25] class 37 reserves ......C.
TBF[25] class 38 reserves .......C
TBF[26] class 39 reserves ...C....
TBF[26] class 40 reserves ....C...
TBF[26] class 41 reserves .....C..
TBF[26] class 42 reserves ......C.
TBF[26] class 43 reserves .......C
TBF[27] class 44 reserves ...C....
TBF[27] class 45 reserves ....C...
TBF[27] class 46 reserves .....C..
TBF[27] class 1 reserves ......C.
TBF[27] class 2 reserves .......C
TBF[28] class 3 reserves ...C....
TBF[28] class 4 reserves ....C...
TBF[28] class 5 reserves .....C..
TBF[28] class 6 reserves ......C.
TBF[28] class 7 reserves .......C
TBF[29] class 8 reserves ...C....
TBF[29] class 9 reserves ....C...
TBF[29] class 10 reserves .....C..
TBF[29] class 11 reserves ......C.
TBF[29] class 12 reserves .......C
TBF[30] class 13 reserves ...C....
TBF[30] class 14 reserves ....C...
TBF[30] class 15 reserves .....C..
TBF[30] class 16 reserves ......C.
TBF[30] class 17 reserves .......C
TBF[31] class 18 reserves ...C....
TBF[31] class 19 reserves ....C...
TBF[31] class 20 reserves .....C..
TBF[31] class 21 reserves ......C.
TBF[31] class 22 reserves .......C
TBF[0] class 1 reserves ...C....
TBF[0] class 2 reserves ....C...
TBF[0] class 3 reserves .....C..
TBF[0] class 4 reserves ......C.
TBF[0] class 5 reserves .......C
TBF[1] class 6 reserves ...C....
TBF[1] class 7 reserves ....C...
TBF[1] class 8 reserves .....C..
TBF[1] class 9 reserves ......C.
TBF[1] class 10 reserves .......C
TBF[2] class 11 reserves ...C....
TBF[2] class 12 reserves ....C...
TBF[2] class 13 reserves .....C..
TBF[2] class 14 reserves ......C.
TBF[2] class 15 reserves .......C
TBF[3] class 16 reserves ...C....
TBF[3] class 17 reserves ....C...
TBF[3] class 18 reserves .....C..
TBF[3] class 19 reserves ......C.
TBF[3] class 20 reserves .......C
TBF[4] class 21 reserves ...C....
TBF[4] class 22 reserves ....C...
TBF[4] class 23 reserves .....C..
TBF[4] class 24 reserves ......C.
TBF[4] class 25 reserves .......C
TBF[5] class 26 reserves ...C....
TBF[5] class 27 reserves ....C...
TBF[5] class 28 reserves .....C..
TBF[5] class 29 reserves ......C.
TBF[5] class 30 reserves .......C
TBF[6] class 31 reserves ...C....
TBF[6] class 32 reserves ....C...
TBF[6] class 33 reserves .....C..
TBF[6] class 34 reserves ......C.
TBF[6] class 35 reserves .......C
TBF[7] class 36 reserves ...C....
TBF[7] class 37 reserves ....C...
TBF[7] class 38 reserves .....C..
TBF[7] class 39 reserves ......C.
TBF[7] class 40 reserves .......C
TBF[8] class 41 reserves ...C....
TBF[8] class 42 reserves ....C...
TBF[8] class 43 reserves .....C..
TBF[8] class 44 reserves ......C.
TBF[8] class 45 reserves .......C
TBF[9] class 46 reserves ...C....
TBF[9] class 1 reserves ....C...
TBF[9] class 2 reserves .....C..
TBF[9] class 3 reserves ......C.
TBF[9] class 4 reserves .......C
TBF[10] class 5 reserves ...C....
TBF[10] class 6 reserves ....C...
TBF[10] class 7 reserves .....C..
TBF[10] class 8 reserves ......C.
TBF[10] class 9 reserves .......C
TBF[11] class 10 reserves ...C....
TBF[11] class 11 reserves ....C...
TBF[11] class 12 reserves .....C..
TBF[11] class 13 reserves ......C.
TBF[11] class 14 reserves .......C
TBF[12] class 15 reserves ...C....
TBF[12] class 16 reserves ....C...
TBF[12] class 17 reserves .....C..
TBF[12] class 18 reserves ......C.
TBF[12] class 19 reserves .......C
TBF[13] class 20 reserves ...C....
TBF[13] class 21 reserves ....C...
TBF[13] class 22 reserves .....C..
TBF[13] class 23 reserves ......C.
TBF[13] class 24 reserves .......C
TBF[14] class 25 reserves ...C....
TBF[14] class 26 reserves ....C...
TBF[14] class 27 reserves .....C..
TBF[14] class 28 reserves ......C.
TBF[14] class 29 reserves .......C
TBF[15] class 30 reserves ...C....
TBF[15] class 31 reserves ....C...
TBF[15] class 32 reserves .....C..
TBF[15] class 33 reserves ......C.
TBF[15] class 34 reserves .......C
TBF[16] class 35 reserves ...C....
TBF[16] class 36 reserves ....C...
TBF[16] class 37 reserves .....C..
TBF[16] class 38 reserves ......C.
TBF[16] class 39 reserves .......C
TBF[17] class 40 reserves ...C....
TBF[17] class 41 reserves ....C...
TBF[17] class 42 reserves .....C..
TBF[17] class 43 reserves ......C.
TBF[17] class 44 reserves .......C
TBF[18] class 45 reserves ...C....
TBF[18] class 46 reserves ....C...
TBF[18] class 1 reserves .....C..
TBF[18] class 2 reserves ......C.
TBF[18] class 3 reserves .......C
TBF[19] class 4 reserves ...C....
TBF[19] class 5 reserves ....C...
TBF[19] class 6 reserves .....C..
TBF[19] class 7 reserves ......C.
TBF[19] class 8 reserves .......C
TBF[20] class 9 reserves ...C....
TBF[20] class 10 reserves ....C...
TBF[20] class 11 reserves .....C..
TBF[20] class 12 reserves ......C.
TBF[20] class 13 reserves .......C
TBF[21] class 14 reserves ...C....
TBF[21] class 15 reserves ....C...
TBF[21] class 16 reserves .....C..
TBF[21] class 17 reserves ......C.
TBF[21] class 18 reserves .......C
TBF[22] class 19 reserves ...C....
TBF[22] class 20 reserves ....C...
TBF[22] class 21 reserves .....C..
TBF[22] class 22 reserves ......C.
TBF[22] class 23 reserves .......C
TBF[23] class 24 reserves ...C....
TBF[23] class 25 reserves ....C...
TBF[23] class 26 reserves .....C..
TBF[23] class 27 reserves ......C.
TBF[23] class 28 reserves .......C
TBF[24] class 29 reserves ...C....
TBF[24] class 30 reserves ....C...
TBF[24] class 31 reserves .....C..
TBF[24] class 32 reserves ......C.
TBF[24] class 33 reserves .......C
TBF[25] class 34 reserves ...C....
TBF[25] class 35 reserves ....C...
TBF[25] class 36 reserves .....C..
TBF[25] class 37 reserves ......C.
TBF[25] class 38 reserves .......C
TBF[26] class 39 reserves ...C....
TBF[26] class 40 reserves ....C...
TBF[26] class 41 reserves .....C..
TBF[26] class 42 reserves ......C.
TBF[26] class 43 reserves .......C
TBF[27] class 44 reserves ...C....
TBF[27] class 45 reserves ....C...
TBF[27] class 46 reserves .....C..
TBF[27] class 1 reserves ......C.
TBF[27] class 2 reserves .......C
TBF[28] class 3 reserves ...C....
TBF[28] class 4 reserves ....C...
TBF[28] class 5 reserves .....C..
TBF[28] class 6 reserves ......C.
TBF[28] class 7 reserves .......C
TBF[29] class 8 reserves ...C....
TBF[29] class 9 reserves ....C...
TBF[29] class 10 reserves .....C..
TBF[29] class 11 reserves ......C.
TBF[29] class 12 reserves .......C
TBF[30] class 13 reserves ...C....
TBF[30] class 14 reserves ....C...
TBF[30] class 15 reserves .....C..
TBF[30] class 16 reserves ......C.
TBF[30] class 17 reserves .......C
TBF[31] class 18 reserves ...C....
TBF[31] class 19 reserves ....C...
TBF[31] class 20 reserves .....C..
TBF[31] class 21 reserves ......C.
TBF[31] class 22 reserves .......C
Successfully allocated 160 TBFs
Going to test assignment with many connections, algorithm B
TBF[0] class 1 reserves ...C....
TBF[1] class 2 reserves ....DC..
TBF[2] class 3 reserves ......DC
TBF[3] class 4 reserves ...DCD..
TBF[4] class 5 reserves ......CD
TBF[5] class 6 reserves ...CD...
TBF[6] class 7 reserves .....CD.
TBF[7] class 8 reserves ....DDCD
TBF[8] class 9 reserves ...DCD..
TBF[9] class 10 reserves .....DCD
TBF[10] class 11 reserves ...DCD..
TBF[11] class 12 reserves .....DCD
TBF[12] class 13 reserves ...CDD..
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[13] class 14 reserves ...CDDD.
TBF[14] class 15 reserves ...CDDDD
TBF[15] class 16 reserves ...CDDDD
TBF[16] class 17 reserves ...CDDDD
TBF[17] class 18 reserves ...CDDDD
TBF[18] class 19 reserves .....DCD
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[19] class 20 reserves .....DCD
TBF[20] class 21 reserves ...DCD..
TBF[21] class 22 reserves .....DCD
TBF[22] class 23 reserves ...DCD..
TBF[23] class 24 reserves .....DCD
TBF[24] class 25 reserves ...DCD..
TBF[25] class 26 reserves .....DCD
TBF[26] class 27 reserves ...DCD..
TBF[27] class 28 reserves .....DCD
TBF[28] class 29 reserves ...DCD..
TBF[29] class 30 reserves ...DDDCD
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[30] class 31 reserves ....DDCD
TBF[31] class 32 reserves ...DDCD.
TBF[0] class 1 reserves ...C....
TBF[1] class 2 reserves ....DC..
TBF[2] class 3 reserves ......DC
TBF[3] class 4 reserves ...DCD..
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[4] class 5 reserves ......CC
TBF[5] class 6 reserves ...CC...
TBF[6] class 7 reserves .....CC.
TBF[7] class 8 reserves ....DDCD
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[8] class 9 reserves ...DCC..
TBF[9] class 10 reserves .....DCC
TBF[10] class 11 reserves ...DCC..
TBF[11] class 12 reserves .....DCC
TBF[12] class 13 reserves ...CCC..
TBF[13] class 14 reserves ...CCCC.
TBF[14] class 15 reserves ...CCCCC
TBF[15] class 16 reserves ...CDDDC
TBF[16] class 17 reserves ...CDDDC
TBF[0] class 1 reserves ...C....
TBF[1] class 2 reserves ....DC..
TBF[2] class 3 reserves ......DC
TBF[3] class 4 reserves ...DCD..
TBF[4] class 5 reserves ......CD
TBF[5] class 6 reserves ...CD...
TBF[6] class 7 reserves .....CD.
TBF[7] class 8 reserves ....DDCD
TBF[8] class 9 reserves ...DCD..
TBF[9] class 10 reserves .....DCD
TBF[10] class 11 reserves ...DCD..
TBF[11] class 12 reserves .....DCD
TBF[12] class 13 reserves ...CDD..
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[13] class 14 reserves ...CDDD.
TBF[14] class 15 reserves ...CDDDD
TBF[15] class 16 reserves ...CDDDD
TBF[16] class 17 reserves ...CDDDD
TBF[17] class 18 reserves ...CDDDD
TBF[18] class 19 reserves .....DCD
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[19] class 20 reserves .....DCD
TBF[20] class 21 reserves ...DCD..
TBF[21] class 22 reserves .....DCD
TBF[22] class 23 reserves ...DCD..
TBF[23] class 24 reserves .....DCD
TBF[24] class 25 reserves ...DCD..
TBF[25] class 26 reserves .....DCD
TBF[26] class 27 reserves ...DCD..
TBF[27] class 28 reserves .....DCD
TBF[28] class 29 reserves ...DCD..
TBF[29] class 30 reserves ...DDDCD
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[30] class 31 reserves ....DDCD
TBF[31] class 32 reserves ...DDCD.
TBF[0] class 1 reserves ...C....
TBF[1] class 2 reserves ...DC...
TBF[2] class 3 reserves ......DC
TBF[3] class 4 reserves ...DCD..
TBF[4] class 5 reserves ...CD...
TBF[5] class 6 reserves ...CD...
TBF[6] class 7 reserves ......CD
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[7] class 8 reserves ....DDCD
TBF[8] class 9 reserves ...DCD..
TBF[9] class 10 reserves .....DCD
TBF[10] class 11 reserves ...DCD..
TBF[11] class 12 reserves .....DCD
TBF[12] class 13 reserves ...CDD..
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[13] class 14 reserves ...CDDD.
TBF[14] class 15 reserves ...CDDDD
TBF[15] class 16 reserves ...CDDDD
TBF[16] class 17 reserves ...CDDDD
TBF[17] class 18 reserves ...CDDDD
TBF[18] class 19 reserves .....DCD
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[19] class 20 reserves .....DCD
TBF[20] class 21 reserves ...DCD..
TBF[21] class 22 reserves .....DCD
TBF[22] class 23 reserves ...DCD..
TBF[23] class 24 reserves .....DCD
TBF[24] class 25 reserves ...DCD..
TBF[25] class 26 reserves .....DCD
TBF[26] class 27 reserves ...DCD..
TBF[27] class 28 reserves .....DCD
TBF[28] class 29 reserves ...DCD..
TBF[29] class 30 reserves ...DDDCD
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[30] class 31 reserves ....DDCD
TBF[31] class 32 reserves ...DDCD.
Successfully allocated 32 TBFs
Going to test assignment with many connections, algorithm dynamic
TBF[0] class 1 reserves ...C....
TBF[1] class 2 reserves ....DC..
TBF[2] class 3 reserves ......DC
TBF[3] class 4 reserves ...DCD..
TBF[4] class 5 reserves ......CD
TBF[5] class 6 reserves ...CD...
TBF[6] class 7 reserves .....CD.
TBF[7] class 8 reserves ....DDCD
TBF[8] class 9 reserves ...DCD..
TBF[9] class 10 reserves .....DCD
TBF[10] class 11 reserves ...DCD..
TBF[11] class 12 reserves .....DCD
TBF[12] class 13 reserves ...CDD..
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[13] class 14 reserves ...CDDD.
TBF[14] class 15 reserves ...CDDDD
TBF[15] class 16 reserves ...CDDDD
TBF[16] class 17 reserves ...CDDDD
TBF[17] class 18 reserves ...CDDDD
TBF[18] class 19 reserves .....DCD
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[19] class 20 reserves .....DCD
TBF[20] class 21 reserves ...DCD..
TBF[21] class 22 reserves .....DCD
TBF[22] class 23 reserves ...DCD..
TBF[23] class 24 reserves .....DCD
TBF[24] class 25 reserves ...DCD..
TBF[25] class 26 reserves .....DCD
TBF[26] class 27 reserves ...DCD..
TBF[27] class 28 reserves .....DCD
TBF[28] class 29 reserves ...DCD..
TBF[29] class 30 reserves ...DDDCD
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[30] class 31 reserves ....DDCD
TBF[31] class 32 reserves ...DDCD.
TBF[0] class 33 reserves ......C.
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[1] class 34 reserves ...C....
TBF[2] class 35 reserves ...C....
TBF[0] class 36 reserves .......C
TBF[4] class 37 reserves ...C....
TBF[1] class 38 reserves .......C
TBF[6] class 39 reserves ...C....
TBF[0] class 40 reserves ....C...
TBF[3] class 41 reserves .......C
TBF[7] class 42 reserves ...C....
TBF[2] class 43 reserves ....C...
TBF[5] class 44 reserves .......C
TBF[9] class 45 reserves ...C....
TBF[4] class 46 reserves ....C...
TBF[6] class 1 reserves .......C
TBF[11] class 2 reserves ...C....
TBF[1] class 3 reserves ......C.
TBF[6] class 4 reserves ....C...
TBF[8] class 5 reserves .......C
TBF[18] class 6 reserves ...C....
TBF[3] class 7 reserves ......C.
TBF[9] class 8 reserves ....C...
TBF[10] class 9 reserves .......C
TBF[19] class 10 reserves ...C....
TBF[5] class 11 reserves ......C.
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[11] class 12 reserves ....C...
TBF[12] class 13 reserves .......C
TBF[21] class 14 reserves ...C....
TBF[8] class 15 reserves ......C.
TBF[0] class 16 reserves .....C..
TBF[18] class 17 reserves ....C...
TBF[13] class 18 reserves .......C
TBF[23] class 19 reserves ...C....
TBF[10] class 20 reserves ......C.
TBF[2] class 21 reserves .....C..
TBF[19] class 22 reserves ....C...
TBF[20] class 23 reserves .......C
TBF[25] class 24 reserves ...C....
TBF[12] class 25 reserves ......C.
TBF[4] class 26 reserves .....C..
TBF[21] class 27 reserves ....C...
TBF[22] class 28 reserves .......C
TBF[27] class 29 reserves ...C....
TBF[20] class 30 reserves ......C.
TBF[5] class 31 reserves .....C..
TBF[23] class 32 reserves ....C...
TBF[24] class 33 reserves .......C
TBF[30] class 34 reserves ...C....
TBF[22] class 35 reserves ......C.
TBF[25] class 36 reserves ....C...
TBF[26] class 37 reserves .......C
TBF[24] class 38 reserves ......C.
TBF[27] class 39 reserves ....C...
TBF[28] class 40 reserves .......C
TBF[26] class 41 reserves ......C.
TBF[31] class 42 reserves .......C
TBF[28] class 43 reserves ......C.
TBF[0] class 1 reserves ...C....
TBF[0] class 2 reserves ....DC..
TBF[0] class 3 reserves ......DC
TBF[0] class 4 reserves ...DCD..
TBF[0] class 5 reserves ......CD
TBF[1] class 6 reserves ...CD...
TBF[1] class 7 reserves .....CD.
TBF[1] class 8 reserves ....DDCD
TBF[1] class 9 reserves ...DCD..
TBF[2] class 10 reserves .....DCD
TBF[2] class 11 reserves ...DCD..
TBF[3] class 12 reserves .....DCD
TBF[2] class 13 reserves ...CDD..
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[3] class 14 reserves ...CDDD.
TBF[4] class 15 reserves ...CDDDD
TBF[5] class 16 reserves ...CDDDD
TBF[6] class 17 reserves ...CDDDD
TBF[0] class 1 reserves ...C....
TBF[1] class 2 reserves .....C..
TBF[2] class 3 reserves .......C
TBF[1] class 4 reserves ....C...
TBF[2] class 5 reserves ......C.
TBF[3] class 6 reserves ...C....
TBF[3] class 7 reserves .....C..
TBF[4] class 8 reserves ......C.
TBF[3] class 9 reserves ....C...
TBF[6] class 10 reserves ......C.
TBF[5] class 11 reserves ....C...
TBF[7] class 12 reserves ......C.
TBF[5] class 13 reserves ...C....
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[8] class 14 reserves ...C....
TBF[10] class 15 reserves ...C....
TBF[12] class 16 reserves ...C....
TBF[13] class 17 reserves ...C....
TBF[14] class 18 reserves ...C....
TBF[9] class 19 reserves ......C.
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[11] class 20 reserves ......C.
TBF[7] class 21 reserves ....C...
TBF[13] class 22 reserves ......C.
TBF[8] class 23 reserves ....C...
TBF[14] class 24 reserves ......C.
TBF[10] class 25 reserves ....C...
TBF[15] class 26 reserves ......C.
TBF[12] class 27 reserves ....C...
TBF[16] class 28 reserves ......C.
TBF[13] class 29 reserves ....C...
TBF[17] class 30 reserves ......C.
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[18] class 31 reserves ......C.
TBF[6] class 32 reserves .....C..
TBF[0] class 33 reserves ......C.
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[1] class 34 reserves ...C....
TBF[2] class 35 reserves ...C....
TBF[0] class 36 reserves .......C
TBF[4] class 37 reserves ...C....
TBF[1] class 38 reserves .......C
TBF[6] class 39 reserves ...C....
TBF[0] class 40 reserves ....C...
TBF[3] class 41 reserves .......C
TBF[7] class 42 reserves ...C....
TBF[2] class 43 reserves ....C...
TBF[4] class 44 reserves .......C
TBF[9] class 45 reserves ...C....
TBF[4] class 46 reserves ....C...
TBF[5] class 1 reserves .......C
TBF[11] class 2 reserves ...C....
TBF[1] class 3 reserves ......C.
TBF[6] class 4 reserves ....C...
TBF[6] class 5 reserves .......C
TBF[15] class 6 reserves ...C....
TBF[3] class 7 reserves ......C.
TBF[9] class 8 reserves ....C...
TBF[7] class 9 reserves .......C
TBF[16] class 10 reserves ...C....
TBF[5] class 11 reserves ......C.
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[11] class 12 reserves ....C...
TBF[8] class 13 reserves .......C
TBF[17] class 14 reserves ...C....
TBF[8] class 15 reserves ......C.
TBF[0] class 16 reserves .....C..
TBF[14] class 17 reserves ....C...
TBF[9] class 18 reserves .......C
TBF[18] class 19 reserves ...C....
TBF[10] class 20 reserves ......C.
TBF[2] class 21 reserves .....C..
TBF[15] class 22 reserves ....C...
TBF[10] class 23 reserves .......C
TBF[19] class 24 reserves ...C....
TBF[12] class 25 reserves ......C.
TBF[4] class 26 reserves .....C..
TBF[16] class 27 reserves ....C...
TBF[11] class 28 reserves .......C
TBF[20] class 29 reserves ...C....
TBF[19] class 30 reserves ......C.
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[5] class 31 reserves .....C..
TBF[17] class 32 reserves ....C...
TBF[12] class 33 reserves .......C
TBF[21] class 34 reserves ...C....
TBF[20] class 35 reserves ......C.
TBF[18] class 36 reserves ....C...
TBF[13] class 37 reserves .......C
TBF[21] class 38 reserves ......C.
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[19] class 39 reserves ....C...
TBF[14] class 40 reserves .......C
TBF[22] class 41 reserves ......C.
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[15] class 42 reserves .......C
TBF[23] class 43 reserves ......C.
TBF[7] class 44 reserves .....C..
TBF[8] class 45 reserves .....C..
TBF[9] class 46 reserves .....C..
TBF[10] class 1 reserves .....C..
TBF[11] class 2 reserves .....C..
TBF[12] class 3 reserves .....C..
TBF[13] class 4 reserves .....C..
TBF[14] class 5 reserves .....C..
TBF[15] class 6 reserves .....C..
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[16] class 7 reserves .....C..
TBF[16] class 8 reserves .......C
TBF[17] class 9 reserves .....C..
TBF[17] class 10 reserves .......C
TBF[18] class 11 reserves .....C..
TBF[18] class 12 reserves .......C
TBF[19] class 13 reserves .....C..
TBF[19] class 14 reserves .......C
TBF[20] class 15 reserves ....C...
TBF[20] class 16 reserves .....C..
TBF[20] class 17 reserves .......C
TBF[21] class 18 reserves ....C...
TBF[21] class 19 reserves .....C..
TBF[21] class 20 reserves .......C
TBF[22] class 21 reserves ...C....
TBF[22] class 22 reserves ....C...
TBF[22] class 23 reserves .....C..
TBF[22] class 24 reserves .......C
TBF[23] class 25 reserves ...C....
TBF[23] class 26 reserves ....C...
TBF[23] class 27 reserves .....C..
TBF[23] class 28 reserves .......C
TBF[24] class 29 reserves ...C....
TBF[24] class 30 reserves ....C...
TBF[24] class 31 reserves .....C..
TBF[24] class 32 reserves ......C.
TBF[24] class 33 reserves .......C
TBF[25] class 34 reserves ...C....
TBF[25] class 35 reserves ....C...
TBF[25] class 36 reserves .....C..
TBF[25] class 37 reserves ......C.
TBF[25] class 38 reserves .......C
TBF[26] class 39 reserves ...C....
TBF[26] class 40 reserves ....C...
TBF[26] class 41 reserves .....C..
TBF[26] class 42 reserves ......C.
TBF[26] class 43 reserves .......C
TBF[27] class 44 reserves ...C....
TBF[27] class 45 reserves ....C...
TBF[27] class 46 reserves .....C..
TBF[27] class 1 reserves ......C.
TBF[27] class 2 reserves .......C
TBF[28] class 3 reserves ...C....
TBF[28] class 4 reserves ....C...
TBF[28] class 5 reserves .....C..
TBF[28] class 6 reserves ......C.
TBF[28] class 7 reserves .......C
TBF[29] class 8 reserves ...C....
TBF[29] class 9 reserves ....C...
TBF[29] class 10 reserves .....C..
TBF[29] class 11 reserves ......C.
TBF[29] class 12 reserves .......C
TBF[30] class 13 reserves ...C....
TBF[30] class 14 reserves ....C...
TBF[30] class 15 reserves .....C..
TBF[30] class 16 reserves ......C.
TBF[30] class 17 reserves .......C
TBF[31] class 18 reserves ...C....
TBF[31] class 19 reserves ....C...
TBF[31] class 20 reserves .....C..
TBF[31] class 21 reserves ......C.
TBF[31] class 22 reserves .......C
TBF[0] class 1 reserves ...C....
TBF[1] class 2 reserves .....C..
TBF[2] class 3 reserves .......C
TBF[1] class 4 reserves ....C...
TBF[2] class 5 reserves ......C.
TBF[3] class 6 reserves ...C....
TBF[3] class 7 reserves .....C..
TBF[4] class 8 reserves ......C.
TBF[3] class 9 reserves ....C...
TBF[6] class 10 reserves ......C.
TBF[5] class 11 reserves ....C...
TBF[7] class 12 reserves ......C.
TBF[5] class 13 reserves ...C....
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[8] class 14 reserves ...C....
TBF[10] class 15 reserves ...C....
TBF[12] class 16 reserves ...C....
TBF[13] class 17 reserves ...C....
TBF[14] class 18 reserves ...C....
TBF[9] class 19 reserves ......C.
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[11] class 20 reserves ......C.
TBF[7] class 21 reserves ....C...
TBF[13] class 22 reserves ......C.
TBF[8] class 23 reserves ....C...
TBF[14] class 24 reserves ......C.
TBF[10] class 25 reserves ....C...
TBF[15] class 26 reserves ......C.
TBF[12] class 27 reserves ....C...
TBF[16] class 28 reserves ......C.
TBF[13] class 29 reserves ....C...
TBF[17] class 30 reserves ......C.
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[18] class 31 reserves ......C.
TBF[6] class 32 reserves .....C..
TBF[0] class 33 reserves ......C.
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[1] class 34 reserves ...C....
TBF[2] class 35 reserves ...C....
TBF[0] class 36 reserves .......C
TBF[4] class 37 reserves ...C....
TBF[1] class 38 reserves .......C
TBF[6] class 39 reserves ...C....
TBF[0] class 40 reserves ....C...
TBF[3] class 41 reserves .......C
TBF[7] class 42 reserves ...C....
TBF[2] class 43 reserves ....C...
TBF[4] class 44 reserves .......C
TBF[9] class 45 reserves ...C....
TBF[4] class 46 reserves ....C...
TBF[5] class 1 reserves .......C
TBF[11] class 2 reserves ...C....
TBF[1] class 3 reserves ......C.
TBF[6] class 4 reserves ....C...
TBF[6] class 5 reserves .......C
TBF[15] class 6 reserves ...C....
TBF[3] class 7 reserves ......C.
TBF[9] class 8 reserves ....C...
TBF[7] class 9 reserves .......C
TBF[16] class 10 reserves ...C....
TBF[5] class 11 reserves ......C.
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[11] class 12 reserves ....C...
TBF[8] class 13 reserves .......C
TBF[17] class 14 reserves ...C....
TBF[8] class 15 reserves ......C.
TBF[0] class 16 reserves .....C..
TBF[14] class 17 reserves ....C...
TBF[9] class 18 reserves .......C
TBF[18] class 19 reserves ...C....
TBF[10] class 20 reserves ......C.
TBF[2] class 21 reserves .....C..
TBF[15] class 22 reserves ....C...
TBF[10] class 23 reserves .......C
TBF[19] class 24 reserves ...C....
TBF[12] class 25 reserves ......C.
TBF[4] class 26 reserves .....C..
TBF[16] class 27 reserves ....C...
TBF[11] class 28 reserves .......C
TBF[20] class 29 reserves ...C....
TBF[19] class 30 reserves ......C.
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[5] class 31 reserves .....C..
TBF[17] class 32 reserves ....C...
TBF[12] class 33 reserves .......C
TBF[21] class 34 reserves ...C....
TBF[20] class 35 reserves ......C.
TBF[18] class 36 reserves ....C...
TBF[13] class 37 reserves .......C
TBF[21] class 38 reserves ......C.
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[19] class 39 reserves ....C...
TBF[14] class 40 reserves .......C
TBF[22] class 41 reserves ......C.
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[15] class 42 reserves .......C
TBF[23] class 43 reserves ......C.
TBF[7] class 44 reserves .....C..
TBF[8] class 45 reserves .....C..
TBF[9] class 46 reserves .....C..
TBF[10] class 1 reserves .....C..
TBF[11] class 2 reserves .....C..
TBF[12] class 3 reserves .....C..
TBF[13] class 4 reserves .....C..
TBF[14] class 5 reserves .....C..
TBF[15] class 6 reserves .....C..
Support uplink multi-slot allocations Before this patch, allocate_usf() was implemented to only allocate 1 USF per TBF, regardless of the available ul_slot mask. As a result, only 1 slot at max was allocated to any TBF. That's a pity because usual multislot classes like 12 support up to 2 UL slots per TBF (in common TS with DL). This patch reworks allocate_usf() to allocate as many UL multislots as possible (given mslot class, current USF availability, TFI availability, related DL TBF slots for the same MS, etc.). As a result, it can be seen that AllocTest results change substantially and maximum concurrent TBF allocation drops under some conditions. That happens due to more USFs being reserved (because each TBF has now more UL slots reserved). Hence now USF exhaustion becomes the usual limitation factor as per the number of concurrent TBFs than can be handled per TRX (as opposed to TFIs previously). Some of the biggest limitations in test appear though because really high end multislot classes are used, which can consume high volumes of UL slots (USFs), and which are probably not the most extended devices in the field. Moreover, in general the curren timeslot allocator for a given multislot class will in general try to optimize the DL side gathering most of the possible timeslots there. That means, for instance on ms class 12 (4 Tx, 4Rx, 5 Sum), 4 DL slots and 1 UL slot will still be selected. But in the case where only 3 PDCHs are available, then with this new multi-slot UL support a TBF will reserve 3 DL slots and 2 UL slots, while before this patch it would only taken 1 UL slot instead of 2. This USF exhaustion situation can be improved in the future by parametrizing (VTY command?) the maximum amount of UL slots that a TBF can reserve, making for instance a default value of 2, meaning usual classes can gather up 2 UL timelosts at a time while forbidding high-end hungry classes to gather up to 8 UL timeslots. Another approach would be to dynamically limit the amount of allowed reservable UL timeslots based on current USF reservation load. Related: OS#2282 Change-Id: Id97cc6e3b769511b591b1694549e0dac55227c43
2021-02-22 16:20:15 +00:00
TBF[16] class 7 reserves .....C..
TBF[16] class 8 reserves .......C
TBF[17] class 9 reserves .....C..
TBF[17] class 10 reserves .......C
TBF[18] class 11 reserves .....C..
TBF[18] class 12 reserves .......C
TBF[19] class 13 reserves .....C..
TBF[19] class 14 reserves .......C
TBF[20] class 15 reserves ....C...
TBF[20] class 16 reserves .....C..
TBF[20] class 17 reserves .......C
TBF[21] class 18 reserves ....C...
TBF[21] class 19 reserves .....C..
TBF[21] class 20 reserves .......C
TBF[22] class 21 reserves ...C....
TBF[22] class 22 reserves ....C...
TBF[22] class 23 reserves .....C..
TBF[22] class 24 reserves .......C
TBF[23] class 25 reserves ...C....
TBF[23] class 26 reserves ....C...
TBF[23] class 27 reserves .....C..
TBF[23] class 28 reserves .......C
TBF[24] class 29 reserves ...C....
TBF[24] class 30 reserves ....C...
TBF[24] class 31 reserves .....C..
TBF[24] class 32 reserves ......C.
TBF[24] class 33 reserves .......C
TBF[25] class 34 reserves ...C....
TBF[25] class 35 reserves ....C...
TBF[25] class 36 reserves .....C..
TBF[25] class 37 reserves ......C.
TBF[25] class 38 reserves .......C
TBF[26] class 39 reserves ...C....
TBF[26] class 40 reserves ....C...
TBF[26] class 41 reserves .....C..
TBF[26] class 42 reserves ......C.
TBF[26] class 43 reserves .......C
TBF[27] class 44 reserves ...C....
TBF[27] class 45 reserves ....C...
TBF[27] class 46 reserves .....C..
TBF[27] class 1 reserves ......C.
TBF[27] class 2 reserves .......C
TBF[28] class 3 reserves ...C....
TBF[28] class 4 reserves ....C...
TBF[28] class 5 reserves .....C..
TBF[28] class 6 reserves ......C.
TBF[28] class 7 reserves .......C
TBF[29] class 8 reserves ...C....
TBF[29] class 9 reserves ....C...
TBF[29] class 10 reserves .....C..
TBF[29] class 11 reserves ......C.
TBF[29] class 12 reserves .......C
TBF[30] class 13 reserves ...C....
TBF[30] class 14 reserves ....C...
TBF[30] class 15 reserves .....C..
TBF[30] class 16 reserves ......C.
TBF[30] class 17 reserves .......C
TBF[31] class 18 reserves ...C....
TBF[31] class 19 reserves ....C...
TBF[31] class 20 reserves .....C..
TBF[31] class 21 reserves ......C.
TBF[31] class 22 reserves .......C
Successfully allocated 160 TBFs
Testing DL TS allocation for Multi UEs
TBF1: numTs(4)
TBF2: numTs(3)