61 lines
1.1 KiB
Verilog
61 lines
1.1 KiB
Verilog
/*
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* soc_usb_buf_bridge.v
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*
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* vim: ts=4 sw=4
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*
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* Copyright (C) 2023 Sylvain Munaut <tnt@246tNt.com>
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* SPDX-License-Identifier: CERN-OHL-P-2.0
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*/
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`default_nettype none
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module soc_usb_buf_bridge (
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// Wishbone (from SoC)
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input wire [15:0] wb_addr,
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output reg [31:0] wb_rdata,
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input wire [31:0] wb_wdata,
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input wire [ 3:0] wb_wmsk,
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input wire wb_we,
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input wire wb_cyc,
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output reg wb_ack,
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// USB EP buffer
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output wire [ 8:0] ep_tx_addr_0,
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output wire [31:0] ep_tx_data_0,
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output wire ep_tx_we_0,
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output wire [ 8:0] ep_rx_addr_0,
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input wire [31:0] ep_rx_data_1,
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output wire ep_rx_re_0,
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// Clock / Reset
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input wire clk,
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input wire rst
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);
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// Ack
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always @(posedge clk)
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wb_ack <= wb_cyc & ~wb_ack;
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// Address
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assign ep_tx_addr_0 = wb_addr[8:0];
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assign ep_rx_addr_0 = wb_addr[8:0];
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// Read Enable
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assign ep_rx_re_0 = wb_cyc;
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// Read
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always @(*)
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if (~wb_ack)
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wb_rdata = 32'h00000000;
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else
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wb_rdata = ep_rx_data_1;
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// Write data
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assign ep_tx_data_0 = wb_wdata;
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// Write enable
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assign ep_tx_we_0 = wb_ack & wb_we;
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endmodule // soc_usb_buf_bridge
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