Kevin Redon 31f31e24eb schematic: mark JP1 and JP2 as dot no place ... the protruding through hole pins of the header for the jumper might get shorted when the board lies on a conductive surface, leading to unwanted flash erase (JP2) or false TST signal (JP1) Change-Id: I7fc6176d8c63ab8274b641e7bcd990093af3c4ca		2019-09-03 17:47:55 +02:00
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datasheet	add datasheet of SPI flash component mounted on recent boards	2013-11-16 10:41:48 +01:00
kicad	schematic: mark JP1 and JP2 as dot no place	2019-09-03 17:47:55 +02:00
pcb	schematic: mark JP1 and JP2 as dot no place	2019-09-03 17:47:55 +02:00