schematic: mark JP1 and JP2 as dot no place
the protruding through hole pins of the header for the jumper might get shorted when the board lies on a conductive surface, leading to unwanted flash erase (JP2) or false TST signal (JP1) Change-Id: I7fc6176d8c63ab8274b641e7bcd990093af3c4ca
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@ -827,6 +827,8 @@ F 0 "JP2" H 4500 1000 50 0000 C CNN
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F 1 "ERASE" H 3800 1000 40 0000 C CNN
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F 2 "PIN_ARRAY_2X1" H 4150 950 60 0001 C CNN
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F 3 "" H 4150 950 60 0001 C CNN
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F 4 "NP" H 4150 1000 50 0000 C CNN "Place"
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F 5 "the pertruding through pins might get shorted when the board lies on a conductive surface, leading to unwanted flash erase" H 4150 950 50 0001 C CNN "Note"
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1 4150 950
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-1 0 0 -1
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$EndComp
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@ -838,6 +840,8 @@ F 0 "JP1" H 3800 1100 50 0000 C CNN
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F 1 "TEST" H 4500 1100 40 0000 C CNN
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F 2 "PIN_ARRAY_2X1" H 4150 1050 60 0001 C CNN
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F 3 "" H 4150 1050 60 0001 C CNN
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F 4 "NP" H 4150 1100 50 0000 C CNN "Place"
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F 5 "the pertruding through pins might get shorted when the board lies on a conductive surface, leading to false signal" H 4150 1050 50 0001 C CNN "Note"
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1 4150 1050
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1 0 0 -1
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$EndComp
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