![Stefan Weil](/assets/img/avatar_default.png)
Those blanks violate the coding conventions, see scripts/checkpatch.pl. Blanks missing after colons in the changed lines were added. This patch does not try to fix tabs, long lines and other problems in the changed lines, therefore checkpatch.pl reports many violations. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
256 lines
5.7 KiB
C
256 lines
5.7 KiB
C
/*
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* PXA270-based Intel Mainstone platforms.
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* FPGA driver
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*
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* Copyright (c) 2007 by Armin Kuster <akuster@kama-aina.net> or
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* <akuster@mvista.com>
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*
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* This code is licensed under the GNU GPL v2.
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*/
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#include "hw.h"
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#include "sysbus.h"
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/* Mainstone FPGA for extern irqs */
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#define FPGA_GPIO_PIN 0
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#define MST_NUM_IRQS 16
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#define MST_LEDDAT1 0x10
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#define MST_LEDDAT2 0x14
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#define MST_LEDCTRL 0x40
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#define MST_GPSWR 0x60
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#define MST_MSCWR1 0x80
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#define MST_MSCWR2 0x84
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#define MST_MSCWR3 0x88
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#define MST_MSCRD 0x90
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#define MST_INTMSKENA 0xc0
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#define MST_INTSETCLR 0xd0
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#define MST_PCMCIA0 0xe0
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#define MST_PCMCIA1 0xe4
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#define MST_PCMCIAx_READY (1 << 10)
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#define MST_PCMCIAx_nCD (1 << 5)
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#define MST_PCMCIA_CD0_IRQ 9
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#define MST_PCMCIA_CD1_IRQ 13
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typedef struct mst_irq_state{
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SysBusDevice busdev;
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qemu_irq parent;
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uint32_t prev_level;
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uint32_t leddat1;
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uint32_t leddat2;
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uint32_t ledctrl;
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uint32_t gpswr;
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uint32_t mscwr1;
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uint32_t mscwr2;
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uint32_t mscwr3;
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uint32_t mscrd;
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uint32_t intmskena;
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uint32_t intsetclr;
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uint32_t pcmcia0;
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uint32_t pcmcia1;
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}mst_irq_state;
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static void
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mst_fpga_set_irq(void *opaque, int irq, int level)
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{
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mst_irq_state *s = (mst_irq_state *)opaque;
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uint32_t oldint = s->intsetclr & s->intmskena;
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if (level)
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s->prev_level |= 1u << irq;
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else
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s->prev_level &= ~(1u << irq);
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switch(irq) {
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case MST_PCMCIA_CD0_IRQ:
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if (level)
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s->pcmcia0 &= ~MST_PCMCIAx_nCD;
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else
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s->pcmcia0 |= MST_PCMCIAx_nCD;
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break;
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case MST_PCMCIA_CD1_IRQ:
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if (level)
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s->pcmcia1 &= ~MST_PCMCIAx_nCD;
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else
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s->pcmcia1 |= MST_PCMCIAx_nCD;
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break;
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}
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if ((s->intmskena & (1u << irq)) && level)
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s->intsetclr |= 1u << irq;
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if (oldint != (s->intsetclr & s->intmskena))
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qemu_set_irq(s->parent, s->intsetclr & s->intmskena);
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}
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static uint32_t
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mst_fpga_readb(void *opaque, target_phys_addr_t addr)
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{
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mst_irq_state *s = (mst_irq_state *) opaque;
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switch (addr) {
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case MST_LEDDAT1:
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return s->leddat1;
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case MST_LEDDAT2:
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return s->leddat2;
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case MST_LEDCTRL:
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return s->ledctrl;
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case MST_GPSWR:
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return s->gpswr;
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case MST_MSCWR1:
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return s->mscwr1;
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case MST_MSCWR2:
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return s->mscwr2;
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case MST_MSCWR3:
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return s->mscwr3;
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case MST_MSCRD:
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return s->mscrd;
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case MST_INTMSKENA:
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return s->intmskena;
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case MST_INTSETCLR:
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return s->intsetclr;
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case MST_PCMCIA0:
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return s->pcmcia0;
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case MST_PCMCIA1:
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return s->pcmcia1;
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default:
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printf("Mainstone - mst_fpga_readb: Bad register offset "
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"0x" TARGET_FMT_plx "\n", addr);
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}
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return 0;
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}
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static void
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mst_fpga_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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mst_irq_state *s = (mst_irq_state *) opaque;
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value &= 0xffffffff;
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switch (addr) {
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case MST_LEDDAT1:
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s->leddat1 = value;
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break;
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case MST_LEDDAT2:
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s->leddat2 = value;
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break;
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case MST_LEDCTRL:
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s->ledctrl = value;
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break;
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case MST_GPSWR:
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s->gpswr = value;
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break;
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case MST_MSCWR1:
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s->mscwr1 = value;
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break;
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case MST_MSCWR2:
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s->mscwr2 = value;
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break;
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case MST_MSCWR3:
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s->mscwr3 = value;
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break;
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case MST_MSCRD:
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s->mscrd = value;
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break;
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case MST_INTMSKENA: /* Mask interrupt */
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s->intmskena = (value & 0xFEEFF);
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qemu_set_irq(s->parent, s->intsetclr & s->intmskena);
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break;
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case MST_INTSETCLR: /* clear or set interrupt */
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s->intsetclr = (value & 0xFEEFF);
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qemu_set_irq(s->parent, s->intsetclr & s->intmskena);
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break;
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/* For PCMCIAx allow the to change only power and reset */
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case MST_PCMCIA0:
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s->pcmcia0 = (value & 0x1f) | (s->pcmcia0 & ~0x1f);
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break;
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case MST_PCMCIA1:
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s->pcmcia1 = (value & 0x1f) | (s->pcmcia1 & ~0x1f);
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break;
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default:
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printf("Mainstone - mst_fpga_writeb: Bad register offset "
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"0x" TARGET_FMT_plx "\n", addr);
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}
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}
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static CPUReadMemoryFunc * const mst_fpga_readfn[] = {
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mst_fpga_readb,
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mst_fpga_readb,
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mst_fpga_readb,
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};
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static CPUWriteMemoryFunc * const mst_fpga_writefn[] = {
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mst_fpga_writeb,
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mst_fpga_writeb,
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mst_fpga_writeb,
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};
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static int mst_fpga_post_load(void *opaque, int version_id)
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{
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mst_irq_state *s = (mst_irq_state *) opaque;
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qemu_set_irq(s->parent, s->intsetclr & s->intmskena);
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return 0;
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}
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static int mst_fpga_init(SysBusDevice *dev)
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{
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mst_irq_state *s;
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int iomemtype;
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s = FROM_SYSBUS(mst_irq_state, dev);
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s->pcmcia0 = MST_PCMCIAx_READY | MST_PCMCIAx_nCD;
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s->pcmcia1 = MST_PCMCIAx_READY | MST_PCMCIAx_nCD;
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sysbus_init_irq(dev, &s->parent);
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/* alloc the external 16 irqs */
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qdev_init_gpio_in(&dev->qdev, mst_fpga_set_irq, MST_NUM_IRQS);
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iomemtype = cpu_register_io_memory(mst_fpga_readfn,
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mst_fpga_writefn, s, DEVICE_NATIVE_ENDIAN);
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sysbus_init_mmio(dev, 0x00100000, iomemtype);
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return 0;
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}
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static VMStateDescription vmstate_mst_fpga_regs = {
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.name = "mainstone_fpga",
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.version_id = 0,
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.minimum_version_id = 0,
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.minimum_version_id_old = 0,
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.post_load = mst_fpga_post_load,
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.fields = (VMStateField []) {
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VMSTATE_UINT32(prev_level, mst_irq_state),
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VMSTATE_UINT32(leddat1, mst_irq_state),
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VMSTATE_UINT32(leddat2, mst_irq_state),
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VMSTATE_UINT32(ledctrl, mst_irq_state),
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VMSTATE_UINT32(gpswr, mst_irq_state),
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VMSTATE_UINT32(mscwr1, mst_irq_state),
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VMSTATE_UINT32(mscwr2, mst_irq_state),
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VMSTATE_UINT32(mscwr3, mst_irq_state),
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VMSTATE_UINT32(mscrd, mst_irq_state),
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VMSTATE_UINT32(intmskena, mst_irq_state),
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VMSTATE_UINT32(intsetclr, mst_irq_state),
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VMSTATE_UINT32(pcmcia0, mst_irq_state),
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VMSTATE_UINT32(pcmcia1, mst_irq_state),
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VMSTATE_END_OF_LIST(),
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},
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};
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static SysBusDeviceInfo mst_fpga_info = {
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.init = mst_fpga_init,
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.qdev.name = "mainstone-fpga",
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.qdev.desc = "Mainstone II FPGA",
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.qdev.size = sizeof(mst_irq_state),
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.qdev.vmsd = &vmstate_mst_fpga_regs,
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};
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static void mst_fpga_register(void)
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{
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sysbus_register_withprop(&mst_fpga_info);
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}
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device_init(mst_fpga_register);
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