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Remove blanks before \n in output strings 

Those blanks violate the coding conventions, see
scripts/checkpatch.pl.

Blanks missing after colons in the changed lines were added.

This patch does not try to fix tabs, long lines and other
problems in the changed lines, therefore checkpatch.pl reports
many violations.

Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Stefan Weil 2011-09-12 22:33:01 +02:00 committed by Anthony Liguori
parent 937b1258b7
commit b2bedb2144
16 changed files with 41 additions and 41 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
block/vvfat.c
View File

@ -1789,7 +1789,7 @@ DLOG(fprintf(stderr, "read cluster %d (sector %d)\n", (int)cluster_num, (int)clu
for (i = 0; i < 0x10 * s->sectors_per_cluster; i++) {
int cluster_count = 0;
DLOG(fprintf(stderr, "check direntry %d: \n", i); print_direntry(direntries + i));
DLOG(fprintf(stderr, "check direntry %d:\n", i); print_direntry(direntries + i));
if (is_volume_label(direntries + i) || is_dot(direntries + i) ||
is_free(direntries + i))
continue;

4
darwin-user/machload.c
View File

@ -865,11 +865,11 @@ unsigned long setup_arg_pages(void * mh, char ** argv, char ** env)
page_set_flags((int)argv[i], (int)(argv[i]+strlen(argv[i])), PROT_READ | PAGE_VALID);
}
DPRINTF("pushing argc %d \n", argc);
DPRINTF("pushing argc %d\n", argc);
stl(stack, argc);
stack--;
DPRINTF("pushing mh 0x%x \n", (int)mh);
DPRINTF("pushing mh 0x%x\n", (int)mh);
stl(stack, (int) mh);
/* Stack points on the mh */

24
hw/bonito.c
View File

@ -241,7 +241,7 @@ static void bonito_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
saddr = (addr - BONITO_REGBASE) >> 2;
DPRINTF("bonito_writel "TARGET_FMT_plx" val %x saddr %x \n", addr, val, saddr);
DPRINTF("bonito_writel "TARGET_FMT_plx" val %x saddr %x\n", addr, val, saddr);
switch (saddr) {
case BONITO_BONPONCFG:
case BONITO_IODEVCFG:
@ -287,10 +287,10 @@ static void bonito_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
break;
case BONITO_INTEN:
case BONITO_INTISR:
DPRINTF("write to readonly bonito register %x \n", saddr);
DPRINTF("write to readonly bonito register %x\n", saddr);
break;
default:
DPRINTF("write to unknown bonito register %x \n", saddr);
DPRINTF("write to unknown bonito register %x\n", saddr);
break;
}
}
@ -302,7 +302,7 @@ static uint32_t bonito_readl(void *opaque, target_phys_addr_t addr)
saddr = (addr - BONITO_REGBASE) >> 2;
DPRINTF("bonito_readl "TARGET_FMT_plx" \n", addr);
DPRINTF("bonito_readl "TARGET_FMT_plx"\n", addr);
switch (saddr) {
case BONITO_INTISR:
return s->regs[saddr];
@ -328,7 +328,7 @@ static void bonito_pciconf_writel(void *opaque, target_phys_addr_t addr,
{
PCIBonitoState *s = opaque;
DPRINTF("bonito_pciconf_writel "TARGET_FMT_plx" val %x \n", addr, val);
DPRINTF("bonito_pciconf_writel "TARGET_FMT_plx" val %x\n", addr, val);
s->dev.config_write(&s->dev, addr, val, 4);
}
@ -443,7 +443,7 @@ static uint32_t bonito_sbridge_pciaddr(void *opaque, target_phys_addr_t addr)
exit(1);
}
pciaddr = PCI_ADDR(pci_bus_num(s->pcihost->bus), devno, funno, regno);
DPRINTF("cfgaddr %x pciaddr %x busno %x devno %d funno %d regno %d \n",
DPRINTF("cfgaddr %x pciaddr %x busno %x devno %d funno %d regno %d\n",
cfgaddr, pciaddr, pci_bus_num(s->pcihost->bus), devno, funno, regno);
return pciaddr;
@ -456,7 +456,7 @@ static void bonito_spciconf_writeb(void *opaque, target_phys_addr_t addr,
uint32_t pciaddr;
uint16_t status;
DPRINTF("bonito_spciconf_writeb "TARGET_FMT_plx" val %x \n", addr, val);
DPRINTF("bonito_spciconf_writeb "TARGET_FMT_plx" val %x\n", addr, val);
pciaddr = bonito_sbridge_pciaddr(s, addr);
if (pciaddr == 0xffffffff) {
@ -480,7 +480,7 @@ static void bonito_spciconf_writew(void *opaque, target_phys_addr_t addr,
uint32_t pciaddr;
uint16_t status;
DPRINTF("bonito_spciconf_writew "TARGET_FMT_plx" val %x \n", addr, val);
DPRINTF("bonito_spciconf_writew "TARGET_FMT_plx" val %x\n", addr, val);
assert((addr&0x1)==0);
pciaddr = bonito_sbridge_pciaddr(s, addr);
@ -506,7 +506,7 @@ static void bonito_spciconf_writel(void *opaque, target_phys_addr_t addr,
uint32_t pciaddr;
uint16_t status;
DPRINTF("bonito_spciconf_writel "TARGET_FMT_plx" val %x \n", addr, val);
DPRINTF("bonito_spciconf_writel "TARGET_FMT_plx" val %x\n", addr, val);
assert((addr&0x3)==0);
pciaddr = bonito_sbridge_pciaddr(s, addr);
@ -531,7 +531,7 @@ static uint32_t bonito_spciconf_readb(void *opaque, target_phys_addr_t addr)
uint32_t pciaddr;
uint16_t status;
DPRINTF("bonito_spciconf_readb "TARGET_FMT_plx" \n", addr);
DPRINTF("bonito_spciconf_readb "TARGET_FMT_plx"\n", addr);
pciaddr = bonito_sbridge_pciaddr(s, addr);
if (pciaddr == 0xffffffff) {
@ -555,7 +555,7 @@ static uint32_t bonito_spciconf_readw(void *opaque, target_phys_addr_t addr)
uint32_t pciaddr;
uint16_t status;
DPRINTF("bonito_spciconf_readw "TARGET_FMT_plx" \n", addr);
DPRINTF("bonito_spciconf_readw "TARGET_FMT_plx"\n", addr);
assert((addr&0x1)==0);
pciaddr = bonito_sbridge_pciaddr(s, addr);
@ -581,7 +581,7 @@ static uint32_t bonito_spciconf_readl(void *opaque, target_phys_addr_t addr)
uint32_t pciaddr;
uint16_t status;
DPRINTF("bonito_spciconf_readl "TARGET_FMT_plx" \n", addr);
DPRINTF("bonito_spciconf_readl "TARGET_FMT_plx"\n", addr);
assert((addr&0x3) == 0);
pciaddr = bonito_sbridge_pciaddr(s, addr);

2
hw/fmopl.c
View File

@ -606,7 +606,7 @@ static void init_timetables( FM_OPL *OPL , int ARRATE , int DRRATE )
}
#if 0
for (i = 0;i < 64 ;i++){ /* make for overflow area */
LOG(LOG_WAR,("rate %2d , ar %f ms , dr %f ms \n",i,
LOG(LOG_WAR, ("rate %2d , ar %f ms , dr %f ms\n", i,
((double)(EG_ENT<<ENV_BITS) / OPL->AR_TABLE[i]) * (1000.0 / OPL->rate),
((double)(EG_ENT<<ENV_BITS) / OPL->DR_TABLE[i]) * (1000.0 / OPL->rate) ));
}

8
hw/hpet.c
View File

@ -397,7 +397,7 @@ static uint32_t hpet_ram_readl(void *opaque, target_phys_addr_t addr)
case HPET_CFG:
return s->config;
case HPET_CFG + 4:
DPRINTF("qemu: invalid HPET_CFG + 4 hpet_ram_readl \n");
DPRINTF("qemu: invalid HPET_CFG + 4 hpet_ram_readl\n");
return 0;
case HPET_COUNTER:
if (hpet_enabled(s)) {
@ -458,7 +458,7 @@ static void hpet_ram_writel(void *opaque, target_phys_addr_t addr,
uint8_t timer_id = (addr - 0x100) / 0x20;
HPETTimer *timer = &s->timer[timer_id];
DPRINTF("qemu: hpet_ram_writel timer_id = %#x \n", timer_id);
DPRINTF("qemu: hpet_ram_writel timer_id = %#x\n", timer_id);
if (timer_id > s->num_timers) {
DPRINTF("qemu: timer id out of range\n");
return;
@ -485,7 +485,7 @@ static void hpet_ram_writel(void *opaque, target_phys_addr_t addr,
DPRINTF("qemu: invalid HPET_TN_CFG+4 write\n");
break;
case HPET_TN_CMP: // comparator register
DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP \n");
DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP\n");
if (timer->config & HPET_TN_32BIT) {
new_val = (uint32_t)new_val;
}
@ -570,7 +570,7 @@ static void hpet_ram_writel(void *opaque, target_phys_addr_t addr,
}
break;
case HPET_CFG + 4:
DPRINTF("qemu: invalid HPET_CFG+4 write \n");
DPRINTF("qemu: invalid HPET_CFG+4 write\n");
break;
case HPET_STATUS:
val = new_val & s->isr;

4
hw/loader.c
View File

@ -779,13 +779,13 @@ void do_info_roms(Monitor *mon)
QTAILQ_FOREACH(rom, &roms, next) {
if (!rom->fw_file) {
monitor_printf(mon, "addr=" TARGET_FMT_plx
" size=0x%06zx mem=%s name=\"%s\" \n",
" size=0x%06zx mem=%s name=\"%s\"\n",
rom->addr, rom->romsize,
rom->isrom ? "rom" : "ram",
rom->name);
} else {
monitor_printf(mon, "fw=%s/%s"
" size=0x%06zx name=\"%s\" \n",
" size=0x%06zx name=\"%s\"\n",
rom->fw_dir,
rom->fw_file,
rom->romsize,

2
hw/mips_fulong2e.c
View File

@ -343,7 +343,7 @@ static void mips_fulong2e_init(ram_addr_t ram_size, const char *boot_device,
via_devfn = vt82c686b_init(pci_bus, PCI_DEVFN(FULONG2E_VIA_SLOT, 0));
if (via_devfn < 0) {
fprintf(stderr, "vt82c686b_init error \n");
fprintf(stderr, "vt82c686b_init error\n");
exit(1);
}

4
hw/mst_fpga.c
View File

@ -118,7 +118,7 @@ mst_fpga_readb(void *opaque, target_phys_addr_t addr)
return s->pcmcia1;
default:
printf("Mainstone - mst_fpga_readb: Bad register offset "
"0x" TARGET_FMT_plx " \n", addr);
"0x" TARGET_FMT_plx "\n", addr);
}
return 0;
}
@ -171,7 +171,7 @@ mst_fpga_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
break;
default:
printf("Mainstone - mst_fpga_writeb: Bad register offset "
"0x" TARGET_FMT_plx " \n", addr);
"0x" TARGET_FMT_plx "\n", addr);
}
}

12
hw/vt82c686.c
View File

@ -49,7 +49,7 @@ static void superio_ioport_writeb(void *opaque, uint32_t addr, uint32_t data)
int can_write;
SuperIOConfig *superio_conf = opaque;
DPRINTF("superio_ioport_writeb address 0x%x val 0x%x \n", addr, data);
DPRINTF("superio_ioport_writeb address 0x%x val 0x%x\n", addr, data);
if (addr == 0x3f0) {
superio_conf->index = data & 0xff;
} else {
@ -73,12 +73,12 @@ static void superio_ioport_writeb(void *opaque, uint32_t addr, uint32_t data)
switch (superio_conf->index) {
case 0xe7:
if ((data & 0xff) != 0xfe) {
DPRINTF("chage uart 1 base. unsupported yet \n");
DPRINTF("chage uart 1 base. unsupported yet\n");
}
break;
case 0xe8:
if ((data & 0xff) != 0xbe) {
DPRINTF("chage uart 2 base. unsupported yet \n");
DPRINTF("chage uart 2 base. unsupported yet\n");
}
break;
@ -95,7 +95,7 @@ static uint32_t superio_ioport_readb(void *opaque, uint32_t addr)
{
SuperIOConfig *superio_conf = opaque;
DPRINTF("superio_ioport_readb address 0x%x \n", addr);
DPRINTF("superio_ioport_readb address 0x%x\n", addr);
return (superio_conf->config[superio_conf->index]);
}
@ -133,7 +133,7 @@ static void vt82c686b_write_config(PCIDevice * d, uint32_t address,
{
VT82C686BState *vt686 = DO_UPCAST(VT82C686BState, dev, d);
DPRINTF("vt82c686b_write_config address 0x%x val 0x%x len 0x%x \n",
DPRINTF("vt82c686b_write_config address 0x%x val 0x%x len 0x%x\n",
address, val, len);
pci_default_write_config(d, address, val, len);
@ -285,7 +285,7 @@ static void pm_io_space_update(VT686PMState *s)
static void pm_write_config(PCIDevice *d,
uint32_t address, uint32_t val, int len)
{
DPRINTF("pm_write_config address 0x%x val 0x%x len 0x%x \n",
DPRINTF("pm_write_config address 0x%x val 0x%x len 0x%x\n",
address, val, len);
pci_default_write_config(d, address, val, len);
}

2
linux-user/syscall.c
View File

@ -1504,7 +1504,7 @@ static abi_long do_setsockopt(int sockfd, int level, int optname,
break;
default:
unimplemented:
gemu_log("Unsupported setsockopt level=%d optname=%d \n", level, optname);
gemu_log("Unsupported setsockopt level=%d optname=%d\n", level, optname);
ret = -TARGET_ENOPROTOOPT;
}
return ret;

2
mips-dis.c
View File

@ -4841,7 +4841,7 @@ with the -M switch (multiple options should be separated by commas):\n"));
Default: based on binary being disassembled.\n"));
fprintf (stream, _("\n\
hwr-names=ARCH Print HWR names according to specified \n\
hwr-names=ARCH Print HWR names according to specified\n\
architecture.\n\
Default: based on binary being disassembled.\n"));

2
qemu-io.c
View File

@ -880,7 +880,7 @@ static void multiwrite_help(void)
" in a batch of requests that may be merged by qemu\n"
"\n"
" Example:\n"
" 'multiwrite 512 1k 1k ; 4k 1k' \n"
" 'multiwrite 512 1k 1k ; 4k 1k'\n"
" writes 2 kB at 512 bytes and 1 kB at 4 kB into the open file\n"
"\n"
" Writes into a segment of the currently open file, using a buffer\n"

8
slirp/tcp_input.c
View File

@ -231,7 +231,7 @@ tcp_input(struct mbuf *m, int iphlen, struct socket *inso)
Slirp *slirp;
DEBUG_CALL("tcp_input");
DEBUG_ARGS((dfd," m = %8lx iphlen = %2d inso = %lx\n",
DEBUG_ARGS((dfd, " m = %8lx iphlen = %2d inso = %lx\n",
(long )m, iphlen, (long )inso ));
/*
@ -580,7 +580,7 @@ findso:
if((tcp_fconnect(so) == -1) && (errno != EINPROGRESS) && (errno != EWOULDBLOCK)) {
u_char code=ICMP_UNREACH_NET;
DEBUG_MISC((dfd," tcp fconnect errno = %d-%s\n",
DEBUG_MISC((dfd, " tcp fconnect errno = %d-%s\n",
errno,strerror(errno)));
if(errno == ECONNREFUSED) {
/* ACK the SYN, send RST to refuse the connection */
@ -910,7 +910,7 @@ trimthenstep6:
if (SEQ_LEQ(ti->ti_ack, tp->snd_una)) {
if (ti->ti_len == 0 && tiwin == tp->snd_wnd) {
DEBUG_MISC((dfd," dup ack m = %lx so = %lx \n",
DEBUG_MISC((dfd, " dup ack m = %lx so = %lx\n",
(long )m, (long )so));
/*
* If we have outstanding data (other than
@ -1293,7 +1293,7 @@ tcp_dooptions(struct tcpcb *tp, u_char *cp, int cnt, struct tcpiphdr *ti)
int opt, optlen;
DEBUG_CALL("tcp_dooptions");
DEBUG_ARGS((dfd," tp = %lx cnt=%i \n", (long )tp, cnt));
DEBUG_ARGS((dfd, " tp = %lx cnt=%i\n", (long)tp, cnt));
for (; cnt > 0; cnt -= optlen, cp += optlen) {
opt = cp[0];

2
slirp/tcp_subr.c
View File

@ -902,7 +902,7 @@ int tcp_ctl(struct socket *so)
return 1;
}
do_pty = ex_ptr->ex_pty;
DEBUG_MISC((dfd, " executing %s \n",ex_ptr->ex_exec));
DEBUG_MISC((dfd, " executing %s\n", ex_ptr->ex_exec));
return fork_exec(so, ex_ptr->ex_exec, do_pty);
}
}

2
target-ppc/helper.c
View File

@ -553,7 +553,7 @@ static inline int get_bat(CPUState *env, mmu_ctx_t *ctx, target_ulong virtual,
BEPIl = *BATu & 0x0FFE0000;
bl = (*BATu & 0x00001FFC) << 15;
LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx
" BATl " TARGET_FMT_lx " \n\t" TARGET_FMT_lx " "
" BATl " TARGET_FMT_lx "\n\t" TARGET_FMT_lx " "
TARGET_FMT_lx " " TARGET_FMT_lx "\n",
__func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
*BATu, *BATl, BEPIu, BEPIl, bl);

2
tests/test-i386.c
View File

@ -802,7 +802,7 @@ void test_fcmp(double a, double b)
"fstsw %%ax\n"
: "=a" (fpus)
: "t" (a), "u" (b));
printf("fcom(%f %f)=%04lx \n",
printf("fcom(%f %f)=%04lx\n",
a, b, fpus & (0x4500 | FPUS_EMASK));
fpu_clear_exceptions();
asm("fucom %2\n"