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Author SHA1 Message Date
Blue Swirl 8c0d577eb5 kvm: avoid collision with dprintf macro in stdio.h, spotted by clang
Fixes clang errors:
  CC    i386-softmmu/kvm.o
/src/qemu/target-i386/kvm.c:40:9: error: 'dprintf' macro redefined
In file included from /src/qemu/target-i386/kvm.c:21:
In file included from /src/qemu/qemu-common.h:27:
In file included from /usr/include/stdio.h:910:
/usr/include/bits/stdio2.h:189:12: note: previous definition is here
  CC    i386-softmmu/kvm-all.o
/src/qemu/kvm-all.c:39:9: error: 'dprintf' macro redefined
In file included from /src/qemu/kvm-all.c:23:
In file included from /src/qemu/qemu-common.h:27:
In file included from /usr/include/stdio.h:910:
/usr/include/bits/stdio2.h:189:12: note: previous definition is here

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-04-18 14:22:14 +00:00
Adam Lackorzynski 9bd5494e57 target-i386: Fix variable in (disabled) debugging code
Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-08 21:44:40 +02:00
Stefan Weil e5c15efff6 target-i386: Fix compiler warning
With argument checking for cpu_fprintf, gcc throws this warning:

  CC    i386-softmmu/helper.o
cc1: warnings being treated as errors
/qemu/ar7/target-i386/helper.c: In function ‘cpu_x86_dump_seg_cache’:
/qemu/ar7/target-i386/helper.c:220: error: format not a string literal and no format arguments

The code is correct, but current gcc versions don't detect this.
Therefore the patch rewrites the statement to satisfy the compiler.

Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-08 21:42:26 +02:00
Paolo Bonzini 1a7ff92218 remove TARGET_* defines from translate-all.c
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-08 21:34:12 +02:00
Paul Brook d4c430a80f Large page TLB flush
QEMU uses a fixed page size for the CPU TLB.  If the guest uses large
pages then we effectively split these into multiple smaller pages, and
populate the corresponding TLB entries on demand.

When the guest invalidates the TLB by virtual address we must invalidate
all entries covered by the large page.  However the address used to
invalidate the entry may not be present in the QEMU TLB, so we do not
know which regions to clear.

Implementing a full vaiable size TLB is hard and slow, so just keep a
simple address/mask pair to record which addresses may have been mapped by
large pages.  If the guest invalidates this region then flush the
whole TLB.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-03-17 02:44:41 +00:00
Aurelien Jarno 2f7a21c4a5 x86/cpuid: fix indentation
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13 16:50:54 +01:00
Aurelien Jarno 8560efed6a x86/cpuid: Enable all features of real CPU
Enable all features of real CPU, unsupported features will be
trimmed depending on TCG or KVM capabilities.

Move the list of unsupported TCG features near the TCG capabilities
masks.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13 16:50:54 +01:00
Andre Przywara 58012d66dc x86/cpuid: fix CPUID levels
Bump up the xlevel number for qemu32 to allow parsing of the processor
name string for this model.
Similiarly the 486 processor should have at least the feature bit
leaf enabled.

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13 16:50:54 +01:00
Andre Przywara d3bf59157c x86/cpuid: Always expose 32 and 64-bit CPUs
Since 64-bit capability is just another CPUID bit we now properly
mask, there is no reason anymore to hide the 64-bit capable CPU
models from a 32-bit only QEMU. All 64-bit CPUs can be used
perfectly in 32-bit legacy mode anyway, so these models also make
sense for 32-bit.

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13 16:50:54 +01:00
Andre Przywara 551a2dec8f x86/cpuid: add TCG feature bit trimming
In KVM we trim the user provided CPUID bits to match the host CPU's
one. Introduce a similar feature to QEMU/TCG. Create a mask of TCG's
capabilities and apply it to the user bits.
This allows to let the CPU models reflect their native archetypes.

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13 16:50:54 +01:00
Andre Przywara 457dfed614 x86/cpuid: remove unnecessary kvm_trim function
Correct me if I am wrong, but kvm_trim looks like a really bloated
implementation of a bitwise AND. So remove this function and replace
it with the real stuff(TM).

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13 16:50:54 +01:00
Andre Przywara ed2c54d4cc x86/cpuid: add "host" to the list of supported CPU models
Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13 16:50:54 +01:00
Andre Przywara e117f7725a x86/cpuid: add missing CPUID feature flag names
Some CPUID feature flags had no string value, so they could not be
switched on or off from the command line.
Add names for the missing ones mentioned in the current public CPUID
specification from both Intel and AMD. Those only mentioned in the
Linux kernel source I put as comments.

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13 16:50:54 +01:00
Andre Przywara bdde476a9c x86/cpuid: moved host_cpuid function and remove prototype
the host_cpuid function was located at the end of the file and had
a prototype before it's first use. Move it up and remove the
prototype.

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13 16:50:54 +01:00
Andre Przywara 4d067ed7a7 x86/cpuid: fix missing feature set bits
This one was accidently removed with commit
bb0300dc57

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13 16:50:54 +01:00
Andre Przywara 42673936d1 x86/cpuid: replace magic number with named constant
CPUID leaf Fn8000_0001.EDX contains a copy of many Fn0000_0001.EDX bits.
Define a name for this mask to improve readability and avoid typos.

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13 16:50:54 +01:00
Andre Przywara c6dc6f63bf x86/cpuid: move CPUID functions into separate file
about half of target-i386/helper.c consist of CPUID related functions.
Only one of them is a real TCG helper function. So move the whole
CPUID stuff out of this into a separate file to get better
maintainable parts.
This is only code reordering and should not affect QEMU's
functionality.

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13 16:50:54 +01:00
TeLeMan 2e21e7491f target-i386: fix commit c22549204a
The commit c22549204a led movntps &
movntdq to be translated incorrectly.

Signed-off-by: TeLeMan <geleman@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13 11:35:55 +01:00
Paul Brook 4fcc562bff Remove cpu_get_phys_page_debug from userspace emulation
cpu_get_phys_page_debug makes no sense for userspace emulation, so remove it.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-03-12 18:34:25 +00:00
Richard Henderson 5270589032 Move TARGET_PHYS_ADDR_SPACE_BITS to target-*/cpu.h.
Removes a set of ifdefs from exec.c.

Introduce TARGET_VIRT_ADDR_SPACE_BITS for all targets other
than Alpha.  This will be used for page_find_alloc, which is
supposed to be using virtual addresses in the first place.

Signed-off-by: Richard Henderson <rth@twiddle.net>
2010-03-12 16:28:24 +00:00
Aurelien Jarno b16f827bdf target-i386: fix SIB decoding with index = 4
A SIB byte with an index of 4 means "no scaled index", even if the scale
value is not 0. In 64-bit mode, if REX.X is used, an index of 4 selects
%r12. This is correctly handled by the computation of the index variable,
which includes the index bits, and also the REX.X prefix:

    index = ((code >> 3) & 7) | REX_X(s);

Thanks to Avi Kivity, Jamie Lokier and Malc for the analysis of the
problem and the initial patch.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-10 08:43:43 +01:00
malc 41b1e61f51 target-i386: Fix long jumps/calls in long mode with REX.W set
Signed-off-by: malc <av1474@comtv.ru>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-06 19:20:04 +01:00
Aurelien Jarno c22549204a target-i386: fix lddqu SSE instruction
This instruction load data from memory to register and not the reverse.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-06 18:33:53 +01:00
Jan Kiszka ea64305139 KVM: x86: Restrict writeback of VCPU state
Do not write nmi_pending, sipi_vector, and mpstate unless we at least go
through a reset. And TSC as well as KVM wallclocks should only be
written on full sync, otherwise we risk to drop some time on state
read-modify-write.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
2010-03-04 00:29:30 -03:00
Jan Kiszka ea375f9ab8 KVM: Rework VCPU state writeback API
This grand cleanup drops all reset and vmsave/load related
synchronization points in favor of four(!) generic hooks:

- cpu_synchronize_all_states in qemu_savevm_state_complete
  (initial sync from kernel before vmsave)
- cpu_synchronize_all_post_init in qemu_loadvm_state
  (writeback after vmload)
- cpu_synchronize_all_post_init in main after machine init
- cpu_synchronize_all_post_reset in qemu_system_reset
  (writeback after system reset)

These writeback points + the existing one of VCPU exec after
cpu_synchronize_state map on three levels of writeback:

- KVM_PUT_RUNTIME_STATE (during runtime, other VCPUs continue to run)
- KVM_PUT_RESET_STATE   (on synchronous system reset, all VCPUs stopped)
- KVM_PUT_FULL_STATE    (on init or vmload, all VCPUs stopped as well)

This level is passed to the arch-specific VCPU state writing function
that will decide which concrete substates need to be written. That way,
no writer of load, save or reset functions that interact with in-kernel
KVM states will ever have to worry about synchronization again. That
also means that a lot of reasons for races, segfaults and deadlocks are
eliminated.

cpu_synchronize_state remains untouched, just as Anthony suggested. We
continue to need it before reading or writing of VCPU states that are
also tracked by in-kernel KVM subsystems.

Consequently, this patch removes many cpu_synchronize_state calls that
are now redundant, just like remaining explicit register syncs.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
2010-03-04 00:29:28 -03:00
Jan Kiszka b0b1d69079 KVM: Rework of guest debug state writing
So far we synchronized any dirty VCPU state back into the kernel before
updating the guest debug state. This was a tribute to a deficite in x86
kernels before 2.6.33. But as this is an arch-dependent issue, it is
better handle in the x86 part of KVM and remove the writeback point for
generic code. This also avoids overwriting the flushed state later on if
user space decides to change some more registers before resuming the
guest.

We furthermore need to reinject guest exceptions via the appropriate
mechanism. That is KVM_SET_GUEST_DEBUG for older kernels and
KVM_SET_VCPU_EVENTS for recent ones. Using both mechanisms at the same
time will cause state corruptions.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
2010-03-04 00:29:26 -03:00
Paul Brook 35bed8ee91 Move ioport.h out of cpu-all.h
Only include ioport.h where it is actually needed.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-03-01 03:29:21 +00:00
Jason Wessel 63a54736f3 target-i386: fix crash on x86 32bit linux host with hw breakpoint exceptions
If you make use of hw breakpoints on a 32bit x86 linux host, qemu
will segmentation fault when processing the exception.

The problem is that the value of env is stored in $ebp in the op_helper
raise_exception() function, and it can have the wrong value when
calling it from non generated code.

It is possible to work around the problem by restoring the value of
env before calling raise_exception() using a new helper function that
takes (CPUState *) as one of the arguments.

Signed-off-by: Jason Wessel <jason.wessel@windriver.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-28 19:20:02 +01:00
Blue Swirl d354899c82 Fix OpenBSD linker warning
helper.o(.text+0x11e0): In function `listflags':
/src/qemu/target-i386/helper.c:661: warning: sprintf() is often misused, please use snprintf()

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-23 22:01:36 +00:00
Blue Swirl 161717d2cb Fix i386-bsd-user build
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-23 21:46:32 +00:00
Anthony Liguori 724c689357 Merge remote branch 'qemu-kvm/uq/master' into staging 2010-02-22 16:16:22 -06:00
john cooper b5ec5ce0e3 Add cpu model configuration support..
This is a reimplementation of prior versions which adds
the ability to define cpu models for contemporary processors.
The added models are likewise selected via -cpu <name>,
and are intended to displace the existing convention
of "-cpu qemu64" augmented with a series of feature flags.

A primary motivation was determination of a least common
denominator within a given processor class to simplify guest
migration.  It is still possible to modify an arbitrary model
via additional feature flags however the goal here was to
make doing so unnecessary in typical usage.  The other
consideration was providing models names reflective of
current processors.  Both AMD and Intel have reviewed the
models in terms of balancing generality of migration vs.
excessive feature downgrade relative to released silicon.

This version of the patch replaces the prior hard wired
definitions with a configuration file approach for new
models.  Existing models are thus far left as-is but may
easily be transitioned to (or may be overridden by) the
configuration file representation.

Proposed new model definitions are provided here for current
AMD and Intel processors.  Each model consists of a name
used to select it on the command line (-cpu <name>), and a
model_id which corresponds to a least common denominator
commercial instance of the processor class.

A table of names/model_ids may be queried via "-cpu ?model":

        :
    x86       Opteron_G3  AMD Opteron 23xx (Gen 3 Class Opteron)
    x86       Opteron_G2  AMD Opteron 22xx (Gen 2 Class Opteron)
    x86       Opteron_G1  AMD Opteron 240 (Gen 1 Class Opteron)
    x86          Nehalem  Intel Core i7 9xx (Nehalem Class Core i7)
    x86           Penryn  Intel Core 2 Duo P9xxx (Penryn Class Core 2)
    x86           Conroe  Intel Celeron_4x0 (Conroe/Merom Class Core 2)
        :

Also added is "-cpu ?dump" which exhaustively outputs all config
data for all defined models, and "-cpu ?cpuid" which enumerates
all qemu recognized CPUID feature flags.

The pseudo cpuid flag 'check' when added to the feature flag list
will warn when feature flags (either implicit in a cpu model or
explicit on the command line) would have otherwise been quietly
unavailable to a guest:

    # qemu-system-x86_64 ... -cpu Nehalem,check
    warning: host cpuid 0000_0001 lacks requested flag 'sse4.2|sse4_2' [0x00100000]
    warning: host cpuid 0000_0001 lacks requested flag 'popcnt' [0x00800000]

A similar 'enforce' pseudo flag exists which in addition
to the above causes qemu to error exit if requested flags are
unavailable.

Configuration data for a cpu model resides in the target config
file which by default will be installed as:

    /usr/local/etc/qemu/target-<arch>.conf

The format of this file should be self explanatory given the
definitions for the above six models and essentially mimics
the structure of the static x86_def_t x86_defs.

Encoding of cpuid flags names now allows aliases for both the
configuration file and the command line which reconciles some
Intel/AMD/Linux/Qemu naming differences.

This patch was tested relative to qemu.git.

Signed-off-by: john cooper <john.cooper@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2010-02-22 16:16:17 -06:00
Jes Sorensen 62f734a0d5 kvm: Kill CR3_CACHE feature references
Remove all references to KVM_CR3_CACHE as it was never implemented.

Signed-off-by: Jes Sorensen <Jes.Sorensen@redhat.com>
Signed-off-by: Avi Kivity <avi@redhat.com>
2010-02-21 11:41:07 +02:00
Jes Sorensen 4c5b10b7b6 QEMU e820 reservation patch
Hi,

Kevin and I have agreed on the approach for this one now. So here is
the latest version of the patch for QEMU, submitting e820 reservation
entries via fw_cfg.

Cheers,
Jes

Use qemu-cfg to provide the BIOS with an optional table of e820 entries.

Notify the BIOS of the location of the TSS+EPT range to by reserving
it via the e820 table.

This matches a corresponding patch for Seabios, however older versions
of Seabios will default to the hardcoded address range and stay
compatible with current QEMU.

Signed-off-by: Jes Sorensen <Jes.Sorensen@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2010-02-19 15:53:54 -06:00
Anthony Liguori 8217d94586 Merge remote branch 'qemu-kvm/uq/master' into staging-tmp 2010-02-08 10:06:54 -06:00
Paolo Bonzini 5e398dd2f0 remove two dead assignments in target-i386/translate.c
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-05 18:13:14 +00:00
Jan Kiszka 19ccb8ea17 KVM: x86: Fix up misreported CPU features
From qemu-kvm: Kernels before 2.6.30 misreported some essential CPU
features via KVM_GET_SUPPORTED_CPUID. Fix them up.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2010-02-03 19:47:34 -02:00
Jan Kiszka aee028b95d KVM: Request setting of nmi_pending and sipi_vector
The final version of VCPU events in 2.6.33 will allow to skip
nmi_pending and sipi_vector on KVM_SET_VCPU_EVENTS. For now let's write
them unconditionally, which is unproblematic for upstream due to missing
SMP support. Future version which enable SMP will write them only on
reset.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
2010-02-03 19:47:33 -02:00
Paolo Bonzini 49a945a3c0 kill regs_to_env and env_to_regs
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2010-01-19 16:31:02 -06:00
Paolo Bonzini baee019f64 remove dead code from target-i386/exec.h
These are unused since edea5f0 (no need to define global registers in
cpu-exec.c, 2008-05-10).

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2010-01-19 16:31:02 -06:00
Gleb Natapov bb0300dc57 Add KVM paravirt cpuid leaf
Initialize KVM paravirt cpuid leaf and allow user to control guest
visible PV features through -cpu flag.

Signed-off-by: Gleb Natapov <gleb@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2010-01-13 17:14:16 -06:00
Amit Shah d7209371b1 x86: translate.c: remove dead assignment
clang-analyzer points out a redundant assignment.

Signed-off-by: Amit Shah <amit.shah@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2010-01-13 17:14:15 -06:00
Gleb Natapov e73223a584 remove pending exception on vcpu reset.
Without this qemu can even start on kvm modules with events support
since default value of exception_injected in zero and this is #DE
exception.

Signed-off-by: Gleb Natapov <gleb@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2010-01-11 09:56:30 -06:00
Huang Ying af364b418c MCE: Fix bug of IA32_MCG_STATUS after system reset
Now, if we inject a fatal MCE into guest OS, for example Linux, Linux
will go panic and then reboot. But if we inject another MCE now,
system will reset directly instead of go panic firstly, because
MCG_STATUS.MCIP is set to 1 and not cleared after reboot. This is does
not follow the behavior in real hardware.

This patch fixes this via set env->mcg_status to 0 during system reset.

Signed-off-by: Huang Ying <ying.huang@intel.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2010-01-11 09:56:30 -06:00
Aurelien Jarno 995963852c target-i386: Fix "call im" on x86_64 when executing 32-bit code
Similarly to what is done in 32938e127f
for "jmp im", trunc the immediate to 32-bit when not running in 64-bit
mode.

Reported-by: Kevin O'Connor <kevin@koconnor.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-01-03 03:14:41 +01:00
Gleb Natapov c84bd4f104 Intel CPUs starting from pentium have apic
Intel CPUs starting from pentium have apic. Lets advertise it.

Signed-off-by: Gleb Natapov <gleb@redhat.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-24 19:39:53 +01:00
Anthony Liguori acb6685fea Revert "kvm: x86: Save/restore exception_index"
This reverts commit ebbc8a3d8e76d0402f8a08c10c0f32e24715d41d.

As suggested by Jan Kiszka,

  "It was obsoleted by d1793b836f8f123b961c613de1bb1c0c185c84cc and now
   saves/restores a useless field."

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-12-18 11:26:33 -06:00
Jan Kiszka d46272c774 target-i386: Fix evaluation of DR7 register
hw_breakpoint_type and hw_breakpoint_len used the wrong index multiplier
to extract type and len.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-12-18 11:26:25 -06:00
Jan Kiszka 31827373f0 kvm: x86: Use separate exception_injected CPUState field
Marcelo correctly remarked that there are usage conflicts between QEMU
core code and KVM /wrt exception_index. So spend a separate field and
also save/restore it properly.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-12-18 11:26:25 -06:00
Andre Przywara f1e00a9cf3 target-i386: Update CPUID feature set for TCG
The CPUID features QEMU presented to the guest were not up-to-date
with QEMU's emulated feature set.
Add the missing bits of recent (and not so recent) additions to
QEMU's emulation engine.
For stability reasons only the user mode usable bits are exposed for
now, features like Monitor or CR8LEG are left out.

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13 20:48:20 +01:00
Glauber Costa 1a03675db1 v2: properly save kvm system time msr registers
Currently, the msrs involved in setting up pvclock are not saved over
migration and/or save/restore. This patch puts their value in special
fields in our CPUState, and deal with them using vmstate.

kvm also has to account for it, by including them in the msr list
for the ioctls.

This is a backport from qemu-kvm.git

[v2: sucessfully build without kerneldir ]

Signed-off-by: Glauber Costa <glommer@redhat.com>
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-12-12 07:59:49 -06:00
Jan Kiszka 4d6e3ac5d4 kvm: x86: Save/restore exception_index
As KVM now makes use of exception_index to keep pending exceptions, we
have to save&restore this field as well.

NOTE: We have to nail the arch-independent exception_index down to a
certain bit width for proper vmstate processing, namely to 32 bit.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-12-12 07:59:39 -06:00
Andre Przywara 6d9fef1a02 cpuid: Fix multicore setup on Intel
The multicore CPUID code detects whether the guest is an Intel or an
AMD CPU, because the Linux kernel is picky about the CmpLegacy bit.
KVM by default passes through the host's vendor, which was not
catched by the code. So fork out the vendor determining bits into a
separate function to be used from both places and always get the real
vendor.
This fixes KVM's multicore setup on Intel CPUs.

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Reported-by: Dietmar Maurer <dietmar@proxmox.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-12-07 11:13:42 -06:00
Jan Kiszka 6fb6d24554 kvm: x86: Fix initial kvm_has_msr_star
KVM_GET_MSR_INDEX_LIST returns -E2BIG when the provided space is too
small for all MSRs. But this is precisely the error we trigger with the
initial request in order to obtain that size. Do not fail in that case.

This caused a subtle corruption of the guest state as MSR_STAR was not
properly saved/restored. The corruption became visible with latest kvm
optimizing the MSR updates.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-12-07 08:45:47 -06:00
Jan Kiszka a0fb002c64 kvm: x86: Add support for VCPU event states
This patch extends the qemu-kvm state sync logic with support for
KVM_GET/SET_VCPU_EVENTS, giving access to yet missing exception,
interrupt and NMI states.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-12-03 15:25:57 -06:00
Jan Kiszka 5a2e3c2e11 kvm: x86: Fix merge artifact of f8d926e9 about mp_state
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-12-03 15:25:56 -06:00
Jan Kiszka 0e607a80d3 kvm: x86: Refactor use of interrupt_bitmap
Drop interrupt_bitmap from the cpustate and solely rely on the integer
interupt_injected. This prepares us for the new injected-interrupt
interface, which will deprecate the bitmap, while preserving
compatibility.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-11-17 08:49:37 -06:00
Jan Kiszka caa5af0ff3 kvm: Add arch reset handler
Will be required by succeeding changes.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-11-17 08:49:37 -06:00
Hollis Blanchard 9bdbe550f0 kvm: Move KVM mp_state accessors to i386-specific code
Unbreaks PowerPC and S390 KVM builds.

Signed-off-by: Hollis Blanchard <hollisb@us.ibm.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-11-12 11:23:55 -06:00
Blue Swirl b55a37c981 user: move CPU reset call to main.c for x86/PPC/Sparc
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-11-07 10:37:06 +00:00
Glauber Costa c169998802 v3: don't call reset functions on cpu initialization
There is absolutely no need to call reset functions when initializing
devices. Since we are already registering them, calling qemu_system_reset()
should suffice. Actually, it is what happens when we reboot the machine,
and using the same process instead of a special case semantics will even
allow us to find bugs easier.

Furthermore, the fact that we initialize things like the cpu quite early,
leads to the need to introduce synchronization stuff like qemu_system_cond.
This patch removes it entirely. All we need to do is call qemu_system_reset()
only when we're already sure the system is up and running

I tested it with qemu (with and without io-thread) and qemu-kvm, and it
seems to be doing okay - although qemu-kvm uses a slightly different patch.

[ v2: user mode still needs cpu_reset, so put it in ifdef. ]
[ v3: leave qemu_system_cond for now. ]

Signed-off-by: Glauber Costa <glommer@redhat.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-11-07 08:06:58 +00:00
Juan Quintela d4829d4992 vmstate: Add version arg to VMSTATE_SINGLE_TEST()
This allows to define VMSTATE_SINGLE with VMSTATE_SINGLE_TEST
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-27 12:28:51 -05:00
Andre Przywara 31501a714b target-i386: implement lzcnt emulation
lzcnt is a AMD Phenom/Barcelona added instruction returning the
number of leading zero bits in a word.
As this is similar to the "bsr" instruction, reuse the existing
code. There need to be some more changes, though, as lzcnt always
returns a valid value (in opposite to bsr, which has a special
case when the operand is 0).
lzcnt is guarded by the ABM CPUID bit (Fn8000_0001:ECX_5).

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-23 17:10:36 +02:00
Blue Swirl 976b2037e5 x86: add 'static' to please Sparse
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-10-18 14:51:10 +00:00
Laurent Desnogues 49d9fdcca6 target-i386: fix ARPL
The arpl implementation in target-i386/translate.c uses cpu_A0
temporary across a brcond op.  This patch fixes that issue.

Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-06 22:01:00 +02:00
Aurelien Jarno 5a2d0e57ad target-i386: move recently added vmstate fields at the end of the structure
This reduce the impact on hosts that have addressing modes with limited
offsets. Suggested by Laurent Desnogues.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-05 22:41:04 +02:00
Juan Quintela 1e7fbc6d3c x86: fix miss merge
There was a missmerge, and then we got a tail recursive call to cpu_post_load
without case base :)

Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 14:01:16 -05:00
Jan Kiszka 5f30fa18ad gdbstub: x86: Switch 64/32 bit registers dynamically
Commit 56aebc8916 changed gdbstub in way
that debugging 32 or 16-bit guest code is no longer possible with qemu
for x86_64 guest CPUs. Since that commit, qemu only provides registers
sets for 64-bit, forcing current and foreseeable gdb to also switch its
architecture to 64-bit. And this breaks if the inferior is 32 or 16 bit.

No question, this is a gdb issue. But, as it was confirmed in several
discusssions with gdb people, it is a non-trivial thing to fix. So until
qemu finds a gdb version attach with a rework x86 support, we have to
work around it by switching the register layout as the guest switches
its execution mode between 16/32 and 64 bit.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:45 -05:00
Juan Quintela 0cb892aa26 x86: port cpu to vmstate
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:43 -05:00
Juan Quintela 3c8ce630c5 x86: factor out cpu_get/put_fpreg()
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:43 -05:00
Juan Quintela 216c07c3a8 x86: factor out cpu_get/put_mttr_var()
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:42 -05:00
Juan Quintela fc3b0aa23e x86: factor out cpu_get/put_xmm_reg()
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:42 -05:00
Juan Quintela 468f65814e x86: factor out cpu_pre/post_load()
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:42 -05:00
Juan Quintela c4c38c8c72 x86: factor out cpu_pre_save()
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:42 -05:00
Juan Quintela 66e6d55b75 x86: port segments to vmstate
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:42 -05:00
Juan Quintela c1a54d573b x86: split MTRRVar union
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:42 -05:00
Juan Quintela acc6883679 x86: split FPReg union
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:42 -05:00
Juan Quintela e5cc6429de x86: mcg_cap is never 0
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:42 -05:00
Juan Quintela 496eb021d8 x86: send mce_banks as an array
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:41 -05:00
Juan Quintela ac74d0f1fc x86: mce_banks always have the same size
mce_banks is always MCE_BANKS_DEF * 4 in size, value never change

CC: Huang Ying <ying.huang@intel.com>
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:41 -05:00
Juan Quintela 60a902f1c3 x86: add fpregs_format_vmstate
Don't even ask, being able to load/save between 64<->80bit floats should be forbidden

Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:41 -05:00
Juan Quintela bfc179b60c x86: add pending_irq_vmstate to the state
It is needed to save the interrupt_bitmap

Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:40 -05:00
Juan Quintela cdc0c58fa9 x86: add fptag_vmstate to the state
It is needed to store fptags

Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:40 -05:00
Juan Quintela 67b8f41957 x86: fpus is uint16_t not unsigned int
We save more that fpus on that 16 bits (fpstt), we need an additional field

Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:40 -05:00
Juan Quintela eb83162311 x86: fpuc is uint16_t not unsigned int
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:40 -05:00
Juan Quintela 5ee0ffaa42 x86: make a20_mask int32_t
This makes the savevm code correct, and sign extensins gives us exactly
what we need (namely, sign extend to 64 bits when used with 64bit addresess.

Once there, change 0x100000 for 1 << 20, that maks all a20 use the same syntax.

Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:39 -05:00
Juan Quintela 1f76b9b9b3 x86: hflags is not modified at all, just save it directly
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-05 09:32:39 -05:00
Kevin Wolf 09d85fb843 target-i386: Fix exceptions for fxsave/fxrstor
This patch corrects the following aspects of exception generation in
fxsave/fxrstor:

* Generate #GP if the operand is not aligned to a 16 byte boundary
* Generate #UD if the LOCK prefix is used
* For CR0.EM = 1 #NM is generated, not #UD

Signed-off-by: Kevin Wolf <mail@kevin-wolf.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-04 23:10:22 +02:00
Andre Przywara 1b050077d2 target-i386: add RDTSCP support
RDTSCP reads the time stamp counter and atomically also the content
of a 32-bit MSR, which can be freely set by the OS. This allows CPU
local data to be queried by userspace.
Linux uses this to allow a fast implementation of the getcpu()
syscall, which uses the vsyscall page to avoid a context switch.
AMD CPUs since K8RevF and Intel CPUs since Nehalem support this
instruction.
RDTSCP is guarded by the RDTSCP CPUID bit (Fn8000_0001:EDX[27]).

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-04 14:46:34 +02:00
Andre Przywara d9f4bb27db target-i386: add SSE4a instruction support
This adds support for the AMD Phenom/Barcelona's SSE4a instructions.
Those include insertq and extrq, which are doing shift and mask on
XMM registers, in two versions (immediate shift/length values and
stored in another XMM register).
Additionally it implements movntss, movntsd, which are scalar
non-temporal stores (avoiding cache trashing). These are implemented
as normal stores, though.
SSE4a is guarded by the SSE4A CPUID bit (Fn8000_0001:ECX[6]).

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-04 14:09:41 +02:00
Andre Przywara ccd59d09a9 target-i386: add lock mov cr0 = cr8
AMD CPUs featuring a shortcut to access CR8 even from 32-bit mode.
If you use the LOCK prefix with "mov CR0", it accesses CR8 instead.
This behavior is guarded by the CR8_LEGACY CPUID bit
(Fn8000_0001:ECX[1]).

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-04 14:04:40 +02:00
Anthony Liguori c227f0995e Revert "Get rid of _t suffix"
In the very least, a change like this requires discussion on the list.

The naming convention is goofy and it causes a massive merge problem.  Something
like this _must_ be presented on the list first so people can provide input
and cope with it.

This reverts commit 99a0949b72.

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-01 16:12:16 -05:00
malc 99a0949b72 Get rid of _t suffix
Some not so obvious bits, slirp and Xen were left alone for the time
being.

Signed-off-by: malc <av1474@comtv.ru>
2009-10-01 22:45:02 +04:00
Laurent Desnogues cc739bb0c4 x86: use globals for CPU registers
Use globals for the 8 or 16 CPU registers on i386 and x86_64.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-30 22:53:05 +02:00
Aurelien Jarno bedda79c1e target-i386: kill a tmp register
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-27 00:57:41 +02:00
Aurelien Jarno 5b207c007c target-i386: use subfi instead of sub with a non-freed constant
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-27 00:57:28 +02:00
Juan Quintela 3897293825 gcc wants 1st static and then const
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-09-25 19:52:06 +00:00
Blue Swirl afcea8cbde ioports: remove unused env parameter and compile only once
The CPU state parameter is not used, remove it and adjust callers. Now we
can compile ioport.c once for all targets.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-09-20 16:05:47 +00:00
Jan Kiszka 2305411129 i386: Drop redundant kvm_enabled test
cpu_synchronize_state already does this.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-09-12 15:52:13 +00:00
Blue Swirl aba1d00a41 Work around OpenSolaris sys/regset.h namespace pollution
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-09-12 12:36:11 +00:00