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109 Commits

Author SHA1 Message Date
aurel32 fad6cb1a56 Update FSF address in GPL/LGPL boilerplate 
The attached patch updates the FSF address in the GPL/LGPL boilerplate
in most GPL/LGPLed files, and also in COPYING.LIB.

Signed-off-by: Stuart Brady <stuart.brady@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6162 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-01-04 22:05:52 +00:00
ths f9480ffc14 Fix remaining compiler warnings for mips targets. 
Signed-off-by: Stefan Weil <weil@mail.berlios.de>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6111 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-12-20 19:42:14 +00:00
aurel32 cd5158ea69 MIPS: remove a few warnings 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5944 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-12-07 23:26:24 +00:00
pbrook a7812ae412 TCG variable type checking. 
Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-17 14:43:54 +00:00
aurel32 49bcf33cc7 target-mips: convert bit shuffle ops to TCG 
Bit shuffle operations can be written with very few TCG instructions
(between 5 and 8), so it is worth converting them to TCG.

This code also move all bit shuffle generation code to a separate
function in order to have a cleaner exception code path, that is it
doesn't store back the TCG register to the target register after the
exception, as the TCG register doesn't exist anymore.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5679 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-11 11:47:06 +00:00
aurel32 505ad7c2ff target-mips: convert bitfield ops to TCG 
Bitfield operations can be written with very few TCG instructions
(between 2 and 5), so it is worth converting them to TCG.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5678 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-11 11:46:58 +00:00
aurel32 add69063e8 target-mips: fix mft* helpers/call 
This patch attempts to fix mft* helpers and the associated TCG calls.
mft* helpers do not take a register in argument, however:
- some helpers are called with an argument while they do not take one.
- some helpers are declared with an argument they don't use.

Acked-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5674 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-11 11:34:39 +00:00
blueswir1 e18231a3ff Show size for unassigned accesses (Robert Reif) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5436 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-10-06 18:46:28 +00:00
ths f01be15458 Move the active FPU registers into env again, and use more TCG registers 
to access them.

Signed-off-by: Thiemo Seufer <ths@networkno.de>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5252 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-18 11:57:27 +00:00
aurel32 bbc0d79cb7 MIPS: Fix tlbwi/tlbwr 
In CP0 Index register, bit 31 means 'Probe Failure', while lowest bits
contain the TLB index.

In tlbwi and tlbwr instructions, this Probe Failure bit must be ignored
when reading the TLB index.

Attached patch fixes it.

(Hervé Poussineau)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5215 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-14 17:09:56 +00:00
ths c904ef0e7c Use plain standard inline. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4929 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-23 16:16:31 +00:00
ths 0eaef5aa01 Less hardcoding of TARGET_USER_ONLY. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4928 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-23 16:14:22 +00:00
ths b6d96beda3 Use temporary registers for the MIPS FPU emulation. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4861 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-09 11:05:10 +00:00
ths d26968ecd8 Remove unnecessary helper arguments, and fix some typos. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4802 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-29 14:53:11 +00:00
ths 2796188e56 Avoid unused input arguments which triggered tcg errors. Spotted by 
Stefan Weil.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4795 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-27 10:03:42 +00:00
ths b5dc7732e1 More efficient target register / TC accesses. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4794 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-27 10:02:35 +00:00
ths 1a3fd9c3da Remove remaining uses of T0 in the MIPS target. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4788 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-24 21:58:35 +00:00
ths 6c5c1e2057 Use temporaries instead of fixed registers for some instructions. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4784 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-24 15:12:27 +00:00
ths be24bb4f30 Pass T0/T1 explicitly to helper functions, and clean up a few dyngen 
leftovers.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4780 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-23 12:57:09 +00:00
ths c8c2227e91 Convert unaligned load/store to TCG. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4759 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-20 15:12:14 +00:00
ths 92af06d216 Convert vr54xx multiply instructions to TCG. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4756 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-20 14:35:19 +00:00
ths a16336e479 Convert remaining MIPS FP instructions to TCG. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4753 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-19 18:35:02 +00:00
ths 214c465f86 Switch the standard multiplication instructions to TCG. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4740 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-12 12:43:29 +00:00
ths 2b0233abfb Switch bitfield instructions and assorted special ops to TCG. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4739 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-12 12:42:35 +00:00
ths 08ba79632f TCGify a few more instructions. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4736 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-12 03:15:13 +00:00
ths f1aa63203d Switch remaining CP0 instructions to TCG or helper functions. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4708 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-09 07:13:38 +00:00
pbrook 9b7b85d260 Fix off-by-one unwinding error. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4570 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-25 00:36:06 +00:00
ths 95af5ce5e2 Fix build failure for MIPS64 targets on 64-bit hosts. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4536 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-23 01:31:57 +00:00
ths 30898801ad Switch MIPS clo/clz and the condition tests to TCG. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4507 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-21 02:04:15 +00:00
ths 48d38ca52b Switch most MIPS logical and arithmetic instructions to TCG. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4496 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-18 22:50:49 +00:00
bellard a607922c75 fixed do_restore_state() 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4413 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-10 15:42:17 +00:00
ths d0dc7dc327 Make MIPS MT implementation more cache friendly. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3981 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-02-12 21:01:26 +00:00
ths 6b5435d77c Fix broken absoluteness check for cabs.d.*. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3900 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-01-08 18:11:08 +00:00
ths e9c71dd1c1 Support for VR5432, and some of its special instructions. Original patch 
by Dirk Behme.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3859 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-12-25 20:46:56 +00:00
ths 306ab3e86a Avoid host FPE for overflowing division on MIPS, by Richard Sandiford. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3856 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-12-25 03:18:19 +00:00
pbrook f090c9d4ad Add strict checking mode for softfp code. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3688 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-11-18 14:33:24 +00:00
ths c6d6dd7c74 Fix MIPS64 R2 instructions. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3686 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-11-18 03:36:07 +00:00
pbrook 5747c0733d Fix int/float inconsistencies. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3672 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-11-17 14:53:06 +00:00
ths d26bc2118e Clean out the N32 macros from target-mips, and introduce MIPS ABI specific 
defines for linux-user.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3556 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-11-08 18:05:37 +00:00
ths 273af66025 Adjust s390 addresses (the MSB is defined as "to be ignored"). 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3486 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-10-29 14:39:49 +00:00
ths 623a930ec3 Implement missing MIPS supervisor mode bits. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3472 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-10-28 19:45:05 +00:00
ths 05f778c8bd Add sharable clz/clo inline functions and use them for the mips target. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3455 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-10-27 13:05:54 +00:00
ths 647de6ca24 Handle IBE on MIPS properly. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3416 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-10-20 19:45:44 +00:00
j_mayer 6ebbf39000 Replace is_user variable with mmu_idx in softmmu core, 
allowing support of more than 2 mmu access modes.
Add backward compatibility is_user variable in targets code when needed.
Implement per target cpu_mmu_index function, avoiding duplicated code
  and #ifdef TARGET_xxx in softmmu core functions.
Implement per target mmu modes definitions. As an example, add PowerPC
  hypervisor mode definition and Alpha executive and kernel modes definitions.
Optimize PowerPC case, precomputing mmu_idx when MSR register changes
  and using the same definition in code translation code.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3384 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-10-14 07:07:08 +00:00
ths aa34373598 Use always_inline in the MIPS support where applicable. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3375 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-10-09 03:39:58 +00:00
ths 4e9f853731 Fix [ls][wd][lr] instructions, by Aurelien Jarno. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3372 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-10-09 03:12:08 +00:00
ths 540635ba65 Code provision for n32/n64 mips userland emulation. Not functional yet. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3284 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-09-30 01:58:33 +00:00
ths 544540979c Less magic constants. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3266 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-09-29 19:19:59 +00:00
ths 418d7c7169 Fix MIPS FP underflow handling, spotted by Daniel Jacobowitz. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3255 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-09-28 19:30:36 +00:00
ths 42532189df Timer start/stop implementation, by Aurelien Jarno. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3237 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-09-25 16:53:15 +00:00