sim-card
/
qemu
Archived
10
0
Fork 0
Code Releases Activity

Revert "Merge remote-tracking branch 'qemu-kvm/memory/batch' into staging" 

This reverts commit 8ef9ea85a2, reversing
changes made to 444dc48298.

From Avi:

  Please revert the entire pull (git revert 8ef9ea85a2) while I work this
  out - it isn't trivial.

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Anthony Liguori 2011-08-25 14:39:18 -05:00
parent f065aa0a00
commit 01e0451a08
49 changed files with 657 additions and 637 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Makefile.hw
View File

@ -10,7 +10,6 @@ include $(SRC_PATH)/rules.mak
$(call set-vpath, $(SRC_PATH):$(SRC_PATH)/hw) $(call set-vpath, $(SRC_PATH):$(SRC_PATH)/hw)
QEMU_CFLAGS+=-I.. QEMU_CFLAGS+=-I..
QEMU_CFLAGS += $(GLIB_CFLAGS)
include $(SRC_PATH)/Makefile.objs include $(SRC_PATH)/Makefile.objs

1
Makefile.target
View File

@ -195,6 +195,7 @@ obj-$(CONFIG_VIRTIO) += virtio.o virtio-blk.o virtio-balloon.o virtio-net.o virt
obj-y += vhost_net.o obj-y += vhost_net.o
obj-$(CONFIG_VHOST_NET) += vhost.o obj-$(CONFIG_VHOST_NET) += vhost.o
obj-$(CONFIG_REALLY_VIRTFS) += 9pfs/virtio-9p-device.o obj-$(CONFIG_REALLY_VIRTFS) += 9pfs/virtio-9p-device.o
obj-y += rwhandler.o
obj-$(CONFIG_KVM) += kvm.o kvm-all.o obj-$(CONFIG_KVM) += kvm.o kvm-all.o
obj-$(CONFIG_NO_KVM) += kvm-stub.o obj-$(CONFIG_NO_KVM) += kvm-stub.o
obj-y += memory.o obj-y += memory.o

12
hw/an5206.c
View File

@ -12,7 +12,6 @@
#include "boards.h" #include "boards.h"
#include "loader.h" #include "loader.h"
#include "elf.h" #include "elf.h"
#include "exec-memory.h"
#define KERNEL_LOAD_ADDR 0x10000 #define KERNEL_LOAD_ADDR 0x10000
#define AN5206_MBAR_ADDR 0x10000000 #define AN5206_MBAR_ADDR 0x10000000
@ -38,9 +37,6 @@ static void an5206_init(ram_addr_t ram_size,
int kernel_size; int kernel_size;
uint64_t elf_entry; uint64_t elf_entry;
target_phys_addr_t entry; target_phys_addr_t entry;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *sram = g_new(MemoryRegion, 1);
if (!cpu_model) if (!cpu_model)
cpu_model = "m5206"; cpu_model = "m5206";
@ -56,12 +52,12 @@ static void an5206_init(ram_addr_t ram_size,
env->rambar0 = AN5206_RAMBAR_ADDR | 1; env->rambar0 = AN5206_RAMBAR_ADDR | 1;
/* DRAM at address zero */ /* DRAM at address zero */
memory_region_init_ram(ram, NULL, "an5206.ram", ram_size); cpu_register_physical_memory(0, ram_size,
memory_region_add_subregion(address_space_mem, 0, ram); qemu_ram_alloc(NULL, "an5206.ram", ram_size) | IO_MEM_RAM);
/* Internal SRAM. */ /* Internal SRAM. */
memory_region_init_ram(sram, NULL, "an5206.sram", 512); cpu_register_physical_memory(AN5206_RAMBAR_ADDR, 512,
memory_region_add_subregion(address_space_mem, AN5206_RAMBAR_ADDR, sram); qemu_ram_alloc(NULL, "an5206.sram", 512) | IO_MEM_RAM);
mcf5206_init(AN5206_MBAR_ADDR, env); mcf5206_init(AN5206_MBAR_ADDR, env);

5
hw/arm-misc.h
View File

@ -11,16 +11,13 @@
#ifndef ARM_MISC_H #ifndef ARM_MISC_H
#define ARM_MISC_H 1 #define ARM_MISC_H 1
#include "memory.h"
/* The CPU is also modeled as an interrupt controller. */ /* The CPU is also modeled as an interrupt controller. */
#define ARM_PIC_CPU_IRQ 0 #define ARM_PIC_CPU_IRQ 0
#define ARM_PIC_CPU_FIQ 1 #define ARM_PIC_CPU_FIQ 1
qemu_irq *arm_pic_init_cpu(CPUState *env); qemu_irq *arm_pic_init_cpu(CPUState *env);
/* armv7m.c */ /* armv7m.c */
qemu_irq *armv7m_init(MemoryRegion *address_space_mem, qemu_irq *armv7m_init(int flash_size, int sram_size,
int flash_size, int sram_size,
const char *kernel_filename, const char *cpu_model); const char *kernel_filename, const char *cpu_model);
/* arm_boot.c */ /* arm_boot.c */

22
hw/armv7m.c
View File

@ -156,8 +156,7 @@ static void armv7m_reset(void *opaque)
flash_size and sram_size are in kb. flash_size and sram_size are in kb.
Returns the NVIC array. */ Returns the NVIC array. */
qemu_irq *armv7m_init(MemoryRegion *address_space_mem, qemu_irq *armv7m_init(int flash_size, int sram_size,
int flash_size, int sram_size,
const char *kernel_filename, const char *cpu_model) const char *kernel_filename, const char *cpu_model)
{ {
CPUState *env; CPUState *env;
@ -170,9 +169,6 @@ qemu_irq *armv7m_init(MemoryRegion *address_space_mem,
uint64_t lowaddr; uint64_t lowaddr;
int i; int i;
int big_endian; int big_endian;
MemoryRegion *sram = g_new(MemoryRegion, 1);
MemoryRegion *flash = g_new(MemoryRegion, 1);
MemoryRegion *hack = g_new(MemoryRegion, 1);
flash_size *= 1024; flash_size *= 1024;
sram_size *= 1024; sram_size *= 1024;
@ -198,11 +194,12 @@ qemu_irq *armv7m_init(MemoryRegion *address_space_mem,
#endif #endif
/* Flash programming is done via the SCU, so pretend it is ROM. */ /* Flash programming is done via the SCU, so pretend it is ROM. */
memory_region_init_ram(flash, NULL, "armv7m.flash", flash_size); cpu_register_physical_memory(0, flash_size,
memory_region_set_readonly(flash, true); qemu_ram_alloc(NULL, "armv7m.flash",
memory_region_add_subregion(address_space_mem, 0, flash); flash_size) | IO_MEM_ROM);
memory_region_init_ram(sram, NULL, "armv7m.sram", sram_size); cpu_register_physical_memory(0x20000000, sram_size,
memory_region_add_subregion(address_space_mem, 0x20000000, sram); qemu_ram_alloc(NULL, "armv7m.sram",
sram_size) | IO_MEM_RAM);
armv7m_bitband_init(); armv7m_bitband_init();
nvic = qdev_create(NULL, "armv7m_nvic"); nvic = qdev_create(NULL, "armv7m_nvic");
@ -235,8 +232,9 @@ qemu_irq *armv7m_init(MemoryRegion *address_space_mem,
/* Hack to map an additional page of ram at the top of the address /* Hack to map an additional page of ram at the top of the address
space. This stops qemu complaining about executing code outside RAM space. This stops qemu complaining about executing code outside RAM
when returning from an exception. */ when returning from an exception. */
memory_region_init_ram(hack, NULL, "armv7m.hack", 0x1000); cpu_register_physical_memory(0xfffff000, 0x1000,
memory_region_add_subregion(address_space_mem, 0xfffff000, hack); qemu_ram_alloc(NULL, "armv7m.hack",
0x1000) | IO_MEM_RAM);
qemu_register_reset(armv7m_reset, env); qemu_register_reset(armv7m_reset, env);
return pic; return pic;

16
hw/axis_dev88.c
View File

@ -31,7 +31,6 @@
#include "elf.h" #include "elf.h"
#include "cris-boot.h" #include "cris-boot.h"
#include "blockdev.h" #include "blockdev.h"
#include "exec-memory.h"
#define D(x) #define D(x)
#define DNAND(x) #define DNAND(x)
@ -260,9 +259,8 @@ void axisdev88_init (ram_addr_t ram_size,
int i; int i;
int nand_regs; int nand_regs;
int gpio_regs; int gpio_regs;
MemoryRegion *address_space_mem = get_system_memory(); ram_addr_t phys_ram;
MemoryRegion *phys_ram = g_new(MemoryRegion, 1); ram_addr_t phys_intmem;
MemoryRegion *phys_intmem = g_new(MemoryRegion, 1);
/* init CPUs */ /* init CPUs */
if (cpu_model == NULL) { if (cpu_model == NULL) {
@ -271,13 +269,15 @@ void axisdev88_init (ram_addr_t ram_size,
env = cpu_init(cpu_model); env = cpu_init(cpu_model);
/* allocate RAM */ /* allocate RAM */
memory_region_init_ram(phys_ram, NULL, "axisdev88.ram", ram_size); phys_ram = qemu_ram_alloc(NULL, "axisdev88.ram", ram_size);
memory_region_add_subregion(address_space_mem, 0x40000000, phys_ram); cpu_register_physical_memory(0x40000000, ram_size, phys_ram | IO_MEM_RAM);
/* The ETRAX-FS has 128Kb on chip ram, the docs refer to it as the /* The ETRAX-FS has 128Kb on chip ram, the docs refer to it as the
internal memory. */ internal memory. */
memory_region_init_ram(phys_intmem, NULL, "axisdev88.chipram", INTMEM_SIZE); phys_intmem = qemu_ram_alloc(NULL, "axisdev88.chipram", INTMEM_SIZE);
memory_region_add_subregion(address_space_mem, 0x38000000, phys_intmem); cpu_register_physical_memory(0x38000000, INTMEM_SIZE,
phys_intmem | IO_MEM_RAM);
/* Attach a NAND flash to CS1. */ /* Attach a NAND flash to CS1. */
nand = drive_get(IF_MTD, 0, 0); nand = drive_get(IF_MTD, 0, 0);

2
hw/cirrus_vga.c
View File

@ -2424,7 +2424,6 @@ static void cirrus_update_memory_access(CirrusVGAState *s)
{ {
unsigned mode; unsigned mode;
memory_region_transaction_begin();
if ((s->vga.sr[0x17] & 0x44) == 0x44) { if ((s->vga.sr[0x17] & 0x44) == 0x44) {
goto generic_io; goto generic_io;
} else if (s->cirrus_srcptr != s->cirrus_srcptr_end) { } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
@ -2444,7 +2443,6 @@ static void cirrus_update_memory_access(CirrusVGAState *s)
unmap_linear_vram(s); unmap_linear_vram(s);
} }
} }
memory_region_transaction_commit();
} }

16
hw/collie.c
View File

@ -26,7 +26,7 @@ static void collie_init(ram_addr_t ram_size,
{ {
StrongARMState *s; StrongARMState *s;
DriveInfo *dinfo; DriveInfo *dinfo;
MemoryRegion *phys_flash = g_new(MemoryRegion, 2); ram_addr_t phys_flash;
if (!cpu_model) { if (!cpu_model) {
cpu_model = "sa1110"; cpu_model = "sa1110";
@ -34,19 +34,17 @@ static void collie_init(ram_addr_t ram_size,
s = sa1110_init(collie_binfo.ram_size, cpu_model); s = sa1110_init(collie_binfo.ram_size, cpu_model);
memory_region_init_rom_device(&phys_flash[0], &pflash_cfi01_ops_le, phys_flash = qemu_ram_alloc(NULL, "collie.fl1", 0x02000000);
NULL, "collie.fl1", 0x02000000);
dinfo = drive_get(IF_PFLASH, 0, 0); dinfo = drive_get(IF_PFLASH, 0, 0);
pflash_cfi01_register(SA_CS0, &phys_flash[0], pflash_cfi01_register(SA_CS0, phys_flash,
dinfo ? dinfo->bdrv : NULL, (64 * 1024), dinfo ? dinfo->bdrv : NULL, (64 * 1024),
512, 4, 0x00, 0x00, 0x00, 0x00); 512, 4, 0x00, 0x00, 0x00, 0x00, 0);
memory_region_init_rom_device(&phys_flash[1], &pflash_cfi01_ops_le, phys_flash = qemu_ram_alloc(NULL, "collie.fl2", 0x02000000);
NULL, "collie.fl2", 0x02000000);
dinfo = drive_get(IF_PFLASH, 0, 1); dinfo = drive_get(IF_PFLASH, 0, 1);
pflash_cfi01_register(SA_CS1, &phys_flash[1], pflash_cfi01_register(SA_CS1, phys_flash,
dinfo ? dinfo->bdrv : NULL, (64 * 1024), dinfo ? dinfo->bdrv : NULL, (64 * 1024),
512, 4, 0x00, 0x00, 0x00, 0x00); 512, 4, 0x00, 0x00, 0x00, 0x00, 0);
sysbus_create_simple("scoop", 0x40800000, NULL); sysbus_create_simple("scoop", 0x40800000, NULL);

13
hw/dec_pci.c
View File

@ -80,15 +80,16 @@ PCIBus *pci_dec_21154_init(PCIBus *parent_bus, int devfn)
static int pci_dec_21154_init_device(SysBusDevice *dev) static int pci_dec_21154_init_device(SysBusDevice *dev)
{ {
DECState *s; DECState *s;
int pci_mem_config, pci_mem_data;
s = FROM_SYSBUS(DECState, dev); s = FROM_SYSBUS(DECState, dev);
memory_region_init_io(&s->host_state.conf_mem, &pci_host_conf_le_ops, pci_mem_config = pci_host_conf_register_mmio(&s->host_state,
&s->host_state, "pci-conf-idx", 0x1000); DEVICE_LITTLE_ENDIAN);
memory_region_init_io(&s->host_state.data_mem, &pci_host_data_le_ops, pci_mem_data = pci_host_data_register_mmio(&s->host_state,
&s->host_state, "pci-data-idx", 0x1000); DEVICE_LITTLE_ENDIAN);
sysbus_init_mmio_region(dev, &s->host_state.conf_mem); sysbus_init_mmio(dev, 0x1000, pci_mem_config);
sysbus_init_mmio_region(dev, &s->host_state.data_mem); sysbus_init_mmio(dev, 0x1000, pci_mem_data);
return 0; return 0;
} }

7
hw/dummy_m68k.c
View File

@ -10,7 +10,6 @@
#include "boards.h" #include "boards.h"
#include "loader.h" #include "loader.h"
#include "elf.h" #include "elf.h"
#include "exec-memory.h"
#define KERNEL_LOAD_ADDR 0x10000 #define KERNEL_LOAD_ADDR 0x10000
@ -22,8 +21,6 @@ static void dummy_m68k_init(ram_addr_t ram_size,
const char *initrd_filename, const char *cpu_model) const char *initrd_filename, const char *cpu_model)
{ {
CPUState *env; CPUState *env;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
int kernel_size; int kernel_size;
uint64_t elf_entry; uint64_t elf_entry;
target_phys_addr_t entry; target_phys_addr_t entry;
@ -40,8 +37,8 @@ static void dummy_m68k_init(ram_addr_t ram_size,
env->vbr = 0; env->vbr = 0;
/* RAM at address zero */ /* RAM at address zero */
memory_region_init_ram(ram, NULL, "dummy_m68k.ram", ram_size); cpu_register_physical_memory(0, ram_size,
memory_region_add_subregion(address_space_mem, 0, ram); qemu_ram_alloc(NULL, "dummy_m68k.ram", ram_size) | IO_MEM_RAM);
/* Load kernel. */ /* Load kernel. */
if (kernel_filename) { if (kernel_filename) {

16
hw/flash.h
View File

@ -1,27 +1,21 @@
#include "memory.h"
/* NOR flash devices */ /* NOR flash devices */
typedef struct pflash_t pflash_t; typedef struct pflash_t pflash_t;
/* pflash_cfi01.c */ /* pflash_cfi01.c */
extern const MemoryRegionOps pflash_cfi01_ops_be; pflash_t *pflash_cfi01_register(target_phys_addr_t base, ram_addr_t off,
extern const MemoryRegionOps pflash_cfi01_ops_le;
extern const MemoryRegionOps pflash_cfi02_ops_be;
extern const MemoryRegionOps pflash_cfi02_ops_le;
pflash_t *pflash_cfi01_register(target_phys_addr_t base, MemoryRegion *mem,
BlockDriverState *bs, BlockDriverState *bs,
uint32_t sector_len, int nb_blocs, int width, uint32_t sector_len, int nb_blocs, int width,
uint16_t id0, uint16_t id1, uint16_t id0, uint16_t id1,
uint16_t id2, uint16_t id3); uint16_t id2, uint16_t id3, int be);
/* pflash_cfi02.c */ /* pflash_cfi02.c */
pflash_t *pflash_cfi02_register(target_phys_addr_t base, MemoryRegion *mem, pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off,
BlockDriverState *bs, uint32_t sector_len, BlockDriverState *bs, uint32_t sector_len,
int nb_blocs, int nb_mappings, int width, int nb_blocs, int nb_mappings, int width,
uint16_t id0, uint16_t id1, uint16_t id0, uint16_t id1,
uint16_t id2, uint16_t id3, uint16_t id2, uint16_t id3,
uint16_t unlock_addr0, uint16_t unlock_addr1); uint16_t unlock_addr0, uint16_t unlock_addr1,
int be);
/* nand.c */ /* nand.c */
DeviceState *nand_init(BlockDriverState *bdrv, int manf_id, int chip_id); DeviceState *nand_init(BlockDriverState *bdrv, int manf_id, int chip_id);

60
hw/g364fb.c
View File

@ -36,7 +36,7 @@ do { fprintf(stderr, "g364 ERROR: " fmt , ## __VA_ARGS__);} while (0)
typedef struct G364State { typedef struct G364State {
/* hardware */ /* hardware */
uint8_t *vram; uint8_t *vram;
MemoryRegion vram_region; ram_addr_t vram_offset;
int vram_size; int vram_size;
qemu_irq irq; qemu_irq irq;
/* registers */ /* registers */
@ -68,17 +68,16 @@ typedef struct G364State {
#define CTLA_FORCE_BLANK 0x00000400 #define CTLA_FORCE_BLANK 0x00000400
#define CTLA_NO_CURSOR 0x00800000 #define CTLA_NO_CURSOR 0x00800000
static inline int check_dirty(G364State *s, ram_addr_t page) static inline int check_dirty(ram_addr_t page)
{ {
return memory_region_get_dirty(&s->vram_region, page, DIRTY_MEMORY_VGA); return cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG);
} }
static inline void reset_dirty(G364State *s, static inline void reset_dirty(G364State *s,
ram_addr_t page_min, ram_addr_t page_max) ram_addr_t page_min, ram_addr_t page_max)
{ {
memory_region_reset_dirty(&s->vram_region, page_min, cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE - 1,
page_max + TARGET_PAGE_SIZE - 1, VGA_DIRTY_FLAG);
DIRTY_MEMORY_VGA);
} }
static void g364fb_draw_graphic8(G364State *s) static void g364fb_draw_graphic8(G364State *s)
@ -115,7 +114,7 @@ static void g364fb_draw_graphic8(G364State *s)
return; return;
} }
page = 0; page = s->vram_offset;
page_min = (ram_addr_t)-1; page_min = (ram_addr_t)-1;
page_max = 0; page_max = 0;
@ -136,7 +135,7 @@ static void g364fb_draw_graphic8(G364State *s)
/* XXX: out of range in vram? */ /* XXX: out of range in vram? */
data_display = dd = ds_get_data(s->ds); data_display = dd = ds_get_data(s->ds);
while (y < s->height) { while (y < s->height) {
if (check_dirty(s, page)) { if (check_dirty(page)) {
if (y < ymin) if (y < ymin)
ymin = ymax = y; ymin = ymax = y;
if (page_min == (ram_addr_t)-1) if (page_min == (ram_addr_t)-1)
@ -276,7 +275,7 @@ static inline void g364fb_invalidate_display(void *opaque)
s->blanked = 0; s->blanked = 0;
for (i = 0; i < s->vram_size; i += TARGET_PAGE_SIZE) { for (i = 0; i < s->vram_size; i += TARGET_PAGE_SIZE) {
memory_region_set_dirty(&s->vram_region, i); cpu_physical_memory_set_dirty(s->vram_offset + i);
} }
} }
@ -412,7 +411,7 @@ static void g364_invalidate_cursor_position(G364State *s)
end = (ymax + 1) * ds_get_linesize(s->ds); end = (ymax + 1) * ds_get_linesize(s->ds);
for (i = start; i < end; i += TARGET_PAGE_SIZE) { for (i = start; i < end; i += TARGET_PAGE_SIZE) {
memory_region_set_dirty(&s->vram_region, i); cpu_physical_memory_set_dirty(s->vram_offset + i);
} }
} }
@ -523,20 +522,16 @@ static void g364fb_ctrl_writeb(void *opaque, target_phys_addr_t addr, uint32_t v
g364fb_ctrl_writel(opaque, addr & ~0x3, val); g364fb_ctrl_writel(opaque, addr & ~0x3, val);
} }
static const MemoryRegionOps g364fb_ctrl_ops = { static CPUReadMemoryFunc * const g364fb_ctrl_read[3] = {
.old_mmio = { g364fb_ctrl_readb,
.read = { g364fb_ctrl_readw,
g364fb_ctrl_readb, g364fb_ctrl_readl,
g364fb_ctrl_readw, };
g364fb_ctrl_readl,
}, static CPUWriteMemoryFunc * const g364fb_ctrl_write[3] = {
.write = { g364fb_ctrl_writeb,
g364fb_ctrl_writeb, g364fb_ctrl_writew,
g364fb_ctrl_writew, g364fb_ctrl_writel,
g364fb_ctrl_writel,
},
},
.endianness = DEVICE_NATIVE_ENDIAN,
}; };
static int g364fb_load(QEMUFile *f, void *opaque, int version_id) static int g364fb_load(QEMUFile *f, void *opaque, int version_id)
@ -588,19 +583,18 @@ static void g364fb_save(QEMUFile *f, void *opaque)
qemu_put_be32(f, s->height); qemu_put_be32(f, s->height);
} }
int g364fb_mm_init(MemoryRegion *system_memory, int g364fb_mm_init(target_phys_addr_t vram_base,
target_phys_addr_t vram_base,
target_phys_addr_t ctrl_base, int it_shift, target_phys_addr_t ctrl_base, int it_shift,
qemu_irq irq) qemu_irq irq)
{ {
G364State *s; G364State *s;
MemoryRegion *io_ctrl = g_new(MemoryRegion, 1); int io_ctrl;
s = g_malloc0(sizeof(G364State)); s = g_malloc0(sizeof(G364State));
s->vram_size = 8 * 1024 * 1024; s->vram_size = 8 * 1024 * 1024;
memory_region_init_ram(&s->vram_region, NULL, "g364fb.vram", s->vram_size); s->vram_offset = qemu_ram_alloc(NULL, "g364fb.vram", s->vram_size);
s->vram = memory_region_get_ram_ptr(&s->vram_region); s->vram = qemu_get_ram_ptr(s->vram_offset);
s->irq = irq; s->irq = irq;
qemu_register_reset(g364fb_reset, s); qemu_register_reset(g364fb_reset, s);
@ -611,11 +605,11 @@ int g364fb_mm_init(MemoryRegion *system_memory,
g364fb_invalidate_display, g364fb_invalidate_display,
g364fb_screen_dump, NULL, s); g364fb_screen_dump, NULL, s);
memory_region_add_subregion(system_memory, vram_base, &s->vram_region); cpu_register_physical_memory(vram_base, s->vram_size, s->vram_offset);
memory_region_init_io(io_ctrl, &g364fb_ctrl_ops, s, io_ctrl = cpu_register_io_memory(g364fb_ctrl_read, g364fb_ctrl_write, s,
"g364fb-ctrl", 0x200000); DEVICE_NATIVE_ENDIAN);
memory_region_add_subregion(system_memory, ctrl_base, io_ctrl); cpu_register_physical_memory(ctrl_base, 0x200000, io_ctrl);
return 0; return 0;
} }

13
hw/grackle_pci.c
View File

@ -92,15 +92,16 @@ PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic,
static int pci_grackle_init_device(SysBusDevice *dev) static int pci_grackle_init_device(SysBusDevice *dev)
{ {
GrackleState *s; GrackleState *s;
int pci_mem_config, pci_mem_data;
s = FROM_SYSBUS(GrackleState, dev); s = FROM_SYSBUS(GrackleState, dev);
memory_region_init_io(&s->host_state.conf_mem, &pci_host_conf_le_ops, pci_mem_config = pci_host_conf_register_mmio(&s->host_state,
&s->host_state, "pci-conf-idx", 0x1000); DEVICE_LITTLE_ENDIAN);
memory_region_init_io(&s->host_state.data_mem, &pci_host_data_le_ops, pci_mem_data = pci_host_data_register_mmio(&s->host_state,
&s->host_state, "pci-data-idx", 0x1000); DEVICE_LITTLE_ENDIAN);
sysbus_init_mmio_region(dev, &s->host_state.conf_mem); sysbus_init_mmio(dev, 0x1000, pci_mem_config);
sysbus_init_mmio_region(dev, &s->host_state.data_mem); sysbus_init_mmio(dev, 0x1000, pci_mem_data);
qemu_register_reset(pci_grackle_reset, &s->host_state); qemu_register_reset(pci_grackle_reset, &s->host_state);
return 0; return 0;

28
hw/gumstix.c
View File

@ -48,8 +48,7 @@ static void connex_init(ram_addr_t ram_size,
{ {
PXA2xxState *cpu; PXA2xxState *cpu;
DriveInfo *dinfo; DriveInfo *dinfo;
const MemoryRegionOps *flash_ops; int be;
MemoryRegion *flash = g_new(MemoryRegion, 1);
uint32_t connex_rom = 0x01000000; uint32_t connex_rom = 0x01000000;
uint32_t connex_ram = 0x04000000; uint32_t connex_ram = 0x04000000;
@ -64,15 +63,14 @@ static void connex_init(ram_addr_t ram_size,
} }
#ifdef TARGET_WORDS_BIGENDIAN #ifdef TARGET_WORDS_BIGENDIAN
flash_ops = &pflash_cfi01_ops_be; be = 1;
#else #else
flash_ops = &pflash_cfi01_ops_le; be = 0;
#endif #endif
memory_region_init_rom_device(flash, flash_ops, if (!pflash_cfi01_register(0x00000000, qemu_ram_alloc(NULL, "connext.rom",
NULL, "connext.rom", connex_rom); connex_rom),
if (!pflash_cfi01_register(0x00000000, flash,
dinfo->bdrv, sector_len, connex_rom / sector_len, dinfo->bdrv, sector_len, connex_rom / sector_len,
2, 0, 0, 0, 0)) { 2, 0, 0, 0, 0, be)) {
fprintf(stderr, "qemu: Error registering flash memory.\n"); fprintf(stderr, "qemu: Error registering flash memory.\n");
exit(1); exit(1);
} }
@ -89,8 +87,7 @@ static void verdex_init(ram_addr_t ram_size,
{ {
PXA2xxState *cpu; PXA2xxState *cpu;
DriveInfo *dinfo; DriveInfo *dinfo;
MemoryRegion *flash = g_new(MemoryRegion, 1); int be;
const MemoryRegionOps *flash_ops;
uint32_t verdex_rom = 0x02000000; uint32_t verdex_rom = 0x02000000;
uint32_t verdex_ram = 0x10000000; uint32_t verdex_ram = 0x10000000;
@ -105,15 +102,14 @@ static void verdex_init(ram_addr_t ram_size,
} }
#ifdef TARGET_WORDS_BIGENDIAN #ifdef TARGET_WORDS_BIGENDIAN
flash_ops = &pflash_cfi01_ops_be; be = 1;
#else #else
flash_ops = &pflash_cfi01_ops_le; be = 0;
#endif #endif
memory_region_init_rom_device(flash, flash_ops, if (!pflash_cfi01_register(0x00000000, qemu_ram_alloc(NULL, "verdex.rom",
NULL, "verdex.rom", verdex_rom); verdex_rom),
if (!pflash_cfi01_register(0x00000000, flash,
dinfo->bdrv, sector_len, verdex_rom / sector_len, dinfo->bdrv, sector_len, verdex_rom / sector_len,
2, 0, 0, 0, 0)) { 2, 0, 0, 0, 0, be)) {
fprintf(stderr, "qemu: Error registering flash memory.\n"); fprintf(stderr, "qemu: Error registering flash memory.\n");
exit(1); exit(1);
} }

28
hw/integratorcp.c
View File

@ -13,13 +13,11 @@
#include "boards.h" #include "boards.h"
#include "arm-misc.h" #include "arm-misc.h"
#include "net.h" #include "net.h"
#include "exec-memory.h"
typedef struct { typedef struct {
SysBusDevice busdev; SysBusDevice busdev;
uint32_t memsz; uint32_t memsz;
MemoryRegion flash; uint32_t flash_offset;
bool flash_mapped;
uint32_t cm_osc; uint32_t cm_osc;
uint32_t cm_ctrl; uint32_t cm_ctrl;
uint32_t cm_lock; uint32_t cm_lock;
@ -110,15 +108,9 @@ static uint32_t integratorcm_read(void *opaque, target_phys_addr_t offset)
static void integratorcm_do_remap(integratorcm_state *s, int flash) static void integratorcm_do_remap(integratorcm_state *s, int flash)
{ {
if (flash) { if (flash) {
if (s->flash_mapped) { cpu_register_physical_memory(0, 0x100000, IO_MEM_RAM);
sysbus_del_memory(&s->busdev, &s->flash);
s->flash_mapped = false;
}
} else { } else {
if (!s->flash_mapped) { cpu_register_physical_memory(0, 0x100000, s->flash_offset | IO_MEM_RAM);
sysbus_add_memory_overlap(&s->busdev, 0, &s->flash, 1);
s->flash_mapped = true;
}
} }
//??? tlb_flush (cpu_single_env, 1); //??? tlb_flush (cpu_single_env, 1);
} }
@ -260,8 +252,7 @@ static int integratorcm_init(SysBusDevice *dev)
} }
memcpy(integrator_spd + 73, "QEMU-MEMORY", 11); memcpy(integrator_spd + 73, "QEMU-MEMORY", 11);
s->cm_init = 0x00000112; s->cm_init = 0x00000112;
memory_region_init_ram(&s->flash, NULL, "integrator.flash", 0x100000); s->flash_offset = qemu_ram_alloc(NULL, "integrator.flash", 0x100000);
s->flash_mapped = false;
iomemtype = cpu_register_io_memory(integratorcm_readfn, iomemtype = cpu_register_io_memory(integratorcm_readfn,
integratorcm_writefn, s, integratorcm_writefn, s,
@ -465,9 +456,7 @@ static void integratorcp_init(ram_addr_t ram_size,
const char *initrd_filename, const char *cpu_model) const char *initrd_filename, const char *cpu_model)
{ {
CPUState *env; CPUState *env;
MemoryRegion *address_space_mem = get_system_memory(); ram_addr_t ram_offset;
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *ram_alias = g_new(MemoryRegion, 1);
qemu_irq pic[32]; qemu_irq pic[32];
qemu_irq *cpu_pic; qemu_irq *cpu_pic;
DeviceState *dev; DeviceState *dev;
@ -480,14 +469,13 @@ static void integratorcp_init(ram_addr_t ram_size,
fprintf(stderr, "Unable to find CPU definition\n"); fprintf(stderr, "Unable to find CPU definition\n");
exit(1); exit(1);
} }
memory_region_init_ram(ram, NULL, "integrator.ram", ram_size); ram_offset = qemu_ram_alloc(NULL, "integrator.ram", ram_size);
/* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash. */ /* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash. */
/* ??? RAM should repeat to fill physical memory space. */ /* ??? RAM should repeat to fill physical memory space. */
/* SDRAM at address zero*/ /* SDRAM at address zero*/
memory_region_add_subregion(address_space_mem, 0, ram); cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
/* And again at address 0x80000000 */ /* And again at address 0x80000000 */
memory_region_init_alias(ram_alias, "ram.alias", ram, 0, ram_size); cpu_register_physical_memory(0x80000000, ram_size, ram_offset | IO_MEM_RAM);
memory_region_add_subregion(address_space_mem, 0x80000000, ram_alias);
dev = qdev_create(NULL, "integrator_core"); dev = qdev_create(NULL, "integrator_core");
qdev_prop_set_uint32(dev, "memsz", ram_size >> 20); qdev_prop_set_uint32(dev, "memsz", ram_size >> 20);

15
hw/leon3.c
View File

@ -29,7 +29,6 @@
#include "loader.h" #include "loader.h"
#include "elf.h" #include "elf.h"
#include "trace.h" #include "trace.h"
#include "exec-memory.h"
#include "grlib.h" #include "grlib.h"
@ -101,9 +100,7 @@ static void leon3_generic_hw_init(ram_addr_t ram_size,
const char *cpu_model) const char *cpu_model)
{ {
CPUState *env; CPUState *env;
MemoryRegion *address_space_mem = get_system_memory(); ram_addr_t ram_offset, prom_offset;
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *prom = g_new(MemoryRegion, 1);
int ret; int ret;
char *filename; char *filename;
qemu_irq *cpu_irqs = NULL; qemu_irq *cpu_irqs = NULL;
@ -142,14 +139,14 @@ static void leon3_generic_hw_init(ram_addr_t ram_size,
exit(1); exit(1);
} }
memory_region_init_ram(ram, NULL, "leon3.ram", ram_size); ram_offset = qemu_ram_alloc(NULL, "leon3.ram", ram_size);
memory_region_add_subregion(address_space_mem, 0x40000000, ram); cpu_register_physical_memory(0x40000000, ram_size, ram_offset | IO_MEM_RAM);
/* Allocate BIOS */ /* Allocate BIOS */
prom_size = 8 * 1024 * 1024; /* 8Mb */ prom_size = 8 * 1024 * 1024; /* 8Mb */
memory_region_init_ram(prom, NULL, "Leon3.bios", prom_size); prom_offset = qemu_ram_alloc(NULL, "Leon3.bios", prom_size);
memory_region_set_readonly(prom, true); cpu_register_physical_memory(0x00000000, prom_size,
memory_region_add_subregion(address_space_mem, 0x00000000, prom); prom_offset | IO_MEM_ROM);
/* Load boot prom */ /* Load boot prom */
if (bios_name == NULL) { if (bios_name == NULL) {

29
hw/lm32_boards.c
View File

@ -28,7 +28,6 @@
#include "elf.h" #include "elf.h"
#include "lm32_hwsetup.h" #include "lm32_hwsetup.h"
#include "lm32.h" #include "lm32.h"
#include "exec-memory.h"
typedef struct { typedef struct {
CPUState *env; CPUState *env;
@ -77,9 +76,8 @@ static void lm32_evr_init(ram_addr_t ram_size_not_used,
{ {
CPUState *env; CPUState *env;
DriveInfo *dinfo; DriveInfo *dinfo;
MemoryRegion *address_space_mem = get_system_memory(); ram_addr_t phys_ram;
MemoryRegion *phys_ram = g_new(MemoryRegion, 1); ram_addr_t phys_flash;
MemoryRegion *phys_flash = g_new(MemoryRegion, 1);
qemu_irq *cpu_irq, irq[32]; qemu_irq *cpu_irq, irq[32];
ResetInfo *reset_info; ResetInfo *reset_info;
int i; int i;
@ -107,17 +105,16 @@ static void lm32_evr_init(ram_addr_t ram_size_not_used,
reset_info->flash_base = flash_base; reset_info->flash_base = flash_base;
memory_region_init_ram(phys_ram, NULL, "lm32_evr.sdram", ram_size); phys_ram = qemu_ram_alloc(NULL, "lm32_evr.sdram", ram_size);
memory_region_add_subregion(address_space_mem, ram_base, phys_ram); cpu_register_physical_memory(ram_base, ram_size, phys_ram | IO_MEM_RAM);
memory_region_init_rom_device(phys_flash, &pflash_cfi02_ops_be, phys_flash = qemu_ram_alloc(NULL, "lm32_evr.flash", flash_size);
NULL, "lm32_evr.flash", flash_size);
dinfo = drive_get(IF_PFLASH, 0, 0); dinfo = drive_get(IF_PFLASH, 0, 0);
/* Spansion S29NS128P */ /* Spansion S29NS128P */
pflash_cfi02_register(flash_base, phys_flash, pflash_cfi02_register(flash_base, phys_flash,
dinfo ? dinfo->bdrv : NULL, flash_sector_size, dinfo ? dinfo->bdrv : NULL, flash_sector_size,
flash_size / flash_sector_size, 1, 2, flash_size / flash_sector_size, 1, 2,
0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa); 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
/* create irq lines */ /* create irq lines */
cpu_irq = qemu_allocate_irqs(cpu_irq_handler, env, 1); cpu_irq = qemu_allocate_irqs(cpu_irq_handler, env, 1);
@ -167,9 +164,8 @@ static void lm32_uclinux_init(ram_addr_t ram_size_not_used,
{ {
CPUState *env; CPUState *env;
DriveInfo *dinfo; DriveInfo *dinfo;
MemoryRegion *address_space_mem = get_system_memory(); ram_addr_t phys_ram;
MemoryRegion *phys_ram = g_new(MemoryRegion, 1); ram_addr_t phys_flash;
MemoryRegion *phys_flash = g_new(MemoryRegion, 1);
qemu_irq *cpu_irq, irq[32]; qemu_irq *cpu_irq, irq[32];
HWSetup *hw; HWSetup *hw;
ResetInfo *reset_info; ResetInfo *reset_info;
@ -204,17 +200,16 @@ static void lm32_uclinux_init(ram_addr_t ram_size_not_used,
reset_info->flash_base = flash_base; reset_info->flash_base = flash_base;
memory_region_init_ram(phys_ram, NULL, "lm32_uclinux.sdram", ram_size); phys_ram = qemu_ram_alloc(NULL, "lm32_uclinux.sdram", ram_size);
memory_region_add_subregion(address_space_mem, ram_base, phys_ram); cpu_register_physical_memory(ram_base, ram_size, phys_ram | IO_MEM_RAM);
memory_region_init_rom_device(phys_flash, &pflash_cfi01_ops_be, phys_flash = qemu_ram_alloc(NULL, "lm32_uclinux.flash", flash_size);
NULL, "lm32_uclinux.flash", flash_size);
dinfo = drive_get(IF_PFLASH, 0, 0); dinfo = drive_get(IF_PFLASH, 0, 0);
/* Spansion S29NS128P */ /* Spansion S29NS128P */
pflash_cfi02_register(flash_base, phys_flash, pflash_cfi02_register(flash_base, phys_flash,
dinfo ? dinfo->bdrv : NULL, flash_sector_size, dinfo ? dinfo->bdrv : NULL, flash_sector_size,
flash_size / flash_sector_size, 1, 2, flash_size / flash_sector_size, 1, 2,
0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa); 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
/* create irq lines */ /* create irq lines */
cpu_irq = qemu_allocate_irqs(cpu_irq_handler, env, 1); cpu_irq = qemu_allocate_irqs(cpu_irq_handler, env, 1);

33
hw/mainstone.c
View File

@ -17,7 +17,6 @@
#include "flash.h" #include "flash.h"
#include "blockdev.h" #include "blockdev.h"
#include "sysbus.h" #include "sysbus.h"
#include "exec-memory.h"
/* Device addresses */ /* Device addresses */
#define MST_FPGA_PHYS 0x08000000 #define MST_FPGA_PHYS 0x08000000
@ -91,8 +90,7 @@ static struct arm_boot_info mainstone_binfo = {
.ram_size = 0x04000000, .ram_size = 0x04000000,
}; };
static void mainstone_common_init(MemoryRegion *address_space_mem, static void mainstone_common_init(ram_addr_t ram_size,
ram_addr_t ram_size,
const char *kernel_filename, const char *kernel_filename,
const char *kernel_cmdline, const char *initrd_filename, const char *kernel_cmdline, const char *initrd_filename,
const char *cpu_model, enum mainstone_model_e model, int arm_id) const char *cpu_model, enum mainstone_model_e model, int arm_id)
@ -103,23 +101,21 @@ static void mainstone_common_init(MemoryRegion *address_space_mem,
DeviceState *mst_irq; DeviceState *mst_irq;
DriveInfo *dinfo; DriveInfo *dinfo;
int i; int i;
MemoryRegion *rom = g_new(MemoryRegion, 1); int be;
MemoryRegion *flashes = g_new(MemoryRegion, 2);
const MemoryRegionOps *flash_ops;
if (!cpu_model) if (!cpu_model)
cpu_model = "pxa270-c5"; cpu_model = "pxa270-c5";
/* Setup CPU & memory */ /* Setup CPU & memory */
cpu = pxa270_init(mainstone_binfo.ram_size, cpu_model); cpu = pxa270_init(mainstone_binfo.ram_size, cpu_model);
memory_region_init_ram(rom, NULL, "mainstone.rom", MAINSTONE_ROM); cpu_register_physical_memory(0, MAINSTONE_ROM,
memory_region_set_readonly(rom, true); qemu_ram_alloc(NULL, "mainstone.rom",
memory_region_add_subregion(address_space_mem, 0, rom); MAINSTONE_ROM) | IO_MEM_ROM);
#ifdef TARGET_WORDS_BIGENDIAN #ifdef TARGET_WORDS_BIGENDIAN
flash_ops = &pflash_cfi01_ops_be; be = 1;
#else #else
flash_ops = &pflash_cfi01_ops_le; be = 0;
#endif #endif
/* There are two 32MiB flash devices on the board */ /* There are two 32MiB flash devices on the board */
for (i = 0; i < 2; i ++) { for (i = 0; i < 2; i ++) {
@ -130,14 +126,13 @@ static void mainstone_common_init(MemoryRegion *address_space_mem,
exit(1); exit(1);
} }
memory_region_init_rom_device(&flashes[i], flash_ops,
NULL, (i ? "mainstone.flash1"
: "mainstone.flash0"),
MAINSTONE_FLASH);
if (!pflash_cfi01_register(mainstone_flash_base[i], if (!pflash_cfi01_register(mainstone_flash_base[i],
&flashes[i], dinfo->bdrv, sector_len, qemu_ram_alloc(NULL, i ? "mainstone.flash1" :
MAINSTONE_FLASH / sector_len, 4, 0, 0, 0, "mainstone.flash0",
0)) { MAINSTONE_FLASH),
dinfo->bdrv, sector_len,
MAINSTONE_FLASH / sector_len, 4, 0, 0, 0, 0,
be)) {
fprintf(stderr, "qemu: Error registering flash memory.\n"); fprintf(stderr, "qemu: Error registering flash memory.\n");
exit(1); exit(1);
} }
@ -175,7 +170,7 @@ static void mainstone_init(ram_addr_t ram_size,
const char *kernel_filename, const char *kernel_cmdline, const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model) const char *initrd_filename, const char *cpu_model)
{ {
mainstone_common_init(get_system_memory(), ram_size, kernel_filename, mainstone_common_init(ram_size, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model, mainstone, 0x196); kernel_cmdline, initrd_filename, cpu_model, mainstone, 0x196);
} }

72
hw/mcf5208.c
View File

@ -13,7 +13,6 @@
#include "boards.h" #include "boards.h"
#include "loader.h" #include "loader.h"
#include "elf.h" #include "elf.h"
#include "exec-memory.h"
#define SYS_FREQ 66000000 #define SYS_FREQ 66000000
@ -28,7 +27,6 @@
#define PCSR_PRE_MASK 0x0f00 #define PCSR_PRE_MASK 0x0f00
typedef struct { typedef struct {
MemoryRegion iomem;
qemu_irq irq; qemu_irq irq;
ptimer_state *timer; ptimer_state *timer;
uint16_t pcsr; uint16_t pcsr;
@ -45,7 +43,7 @@ static void m5208_timer_update(m5208_timer_state *s)
} }
static void m5208_timer_write(void *opaque, target_phys_addr_t offset, static void m5208_timer_write(void *opaque, target_phys_addr_t offset,
uint64_t value, unsigned size) uint32_t value)
{ {
m5208_timer_state *s = (m5208_timer_state *)opaque; m5208_timer_state *s = (m5208_timer_state *)opaque;
int prescale; int prescale;
@ -106,8 +104,7 @@ static void m5208_timer_trigger(void *opaque)
m5208_timer_update(s); m5208_timer_update(s);
} }
static uint64_t m5208_timer_read(void *opaque, target_phys_addr_t addr, static uint32_t m5208_timer_read(void *opaque, target_phys_addr_t addr)
unsigned size)
{ {
m5208_timer_state *s = (m5208_timer_state *)opaque; m5208_timer_state *s = (m5208_timer_state *)opaque;
switch (addr) { switch (addr) {
@ -123,14 +120,19 @@ static uint64_t m5208_timer_read(void *opaque, target_phys_addr_t addr,
} }
} }
static const MemoryRegionOps m5208_timer_ops = { static CPUReadMemoryFunc * const m5208_timer_readfn[] = {
.read = m5208_timer_read, m5208_timer_read,
.write = m5208_timer_write, m5208_timer_read,
.endianness = DEVICE_NATIVE_ENDIAN, m5208_timer_read
}; };
static uint64_t m5208_sys_read(void *opaque, target_phys_addr_t addr, static CPUWriteMemoryFunc * const m5208_timer_writefn[] = {
unsigned size) m5208_timer_write,
m5208_timer_write,
m5208_timer_write
};
static uint32_t m5208_sys_read(void *opaque, target_phys_addr_t addr)
{ {
switch (addr) { switch (addr) {
case 0x110: /* SDCS0 */ case 0x110: /* SDCS0 */
@ -152,36 +154,45 @@ static uint64_t m5208_sys_read(void *opaque, target_phys_addr_t addr,
} }
static void m5208_sys_write(void *opaque, target_phys_addr_t addr, static void m5208_sys_write(void *opaque, target_phys_addr_t addr,
uint64_t value, unsigned size) uint32_t value)
{ {
hw_error("m5208_sys_write: Bad offset 0x%x\n", (int)addr); hw_error("m5208_sys_write: Bad offset 0x%x\n", (int)addr);
} }
static const MemoryRegionOps m5208_sys_ops = { static CPUReadMemoryFunc * const m5208_sys_readfn[] = {
.read = m5208_sys_read, m5208_sys_read,
.write = m5208_sys_write, m5208_sys_read,
.endianness = DEVICE_NATIVE_ENDIAN, m5208_sys_read
}; };
static void mcf5208_sys_init(MemoryRegion *address_space, qemu_irq *pic) static CPUWriteMemoryFunc * const m5208_sys_writefn[] = {
m5208_sys_write,
m5208_sys_write,
m5208_sys_write
};
static void mcf5208_sys_init(qemu_irq *pic)
{ {
MemoryRegion *iomem = g_new(MemoryRegion, 1); int iomemtype;
m5208_timer_state *s; m5208_timer_state *s;
QEMUBH *bh; QEMUBH *bh;
int i; int i;
iomemtype = cpu_register_io_memory(m5208_sys_readfn,
m5208_sys_writefn, NULL,
DEVICE_NATIVE_ENDIAN);
/* SDRAMC. */ /* SDRAMC. */
memory_region_init_io(iomem, &m5208_sys_ops, NULL, "m5208-sys", 0x00004000); cpu_register_physical_memory(0xfc0a8000, 0x00004000, iomemtype);
memory_region_add_subregion(address_space, 0xfc0a8000, iomem);
/* Timers. */ /* Timers. */
for (i = 0; i < 2; i++) { for (i = 0; i < 2; i++) {
s = (m5208_timer_state *)g_malloc0(sizeof(m5208_timer_state)); s = (m5208_timer_state *)g_malloc0(sizeof(m5208_timer_state));
bh = qemu_bh_new(m5208_timer_trigger, s); bh = qemu_bh_new(m5208_timer_trigger, s);
s->timer = ptimer_init(bh); s->timer = ptimer_init(bh);
memory_region_init_io(&s->iomem, &m5208_timer_ops, s, iomemtype = cpu_register_io_memory(m5208_timer_readfn,
"m5208-timer", 0x00004000); m5208_timer_writefn, s,
memory_region_add_subregion(address_space, 0xfc080000 + 0x4000 * i, DEVICE_NATIVE_ENDIAN);
&s->iomem); cpu_register_physical_memory(0xfc080000 + 0x4000 * i, 0x00004000,
iomemtype);
s->irq = pic[4 + i]; s->irq = pic[4 + i];
} }
} }
@ -196,9 +207,6 @@ static void mcf5208evb_init(ram_addr_t ram_size,
uint64_t elf_entry; uint64_t elf_entry;
target_phys_addr_t entry; target_phys_addr_t entry;
qemu_irq *pic; qemu_irq *pic;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *sram = g_new(MemoryRegion, 1);
if (!cpu_model) if (!cpu_model)
cpu_model = "m5208"; cpu_model = "m5208";
@ -213,12 +221,12 @@ static void mcf5208evb_init(ram_addr_t ram_size,
/* TODO: Configure BARs. */ /* TODO: Configure BARs. */
/* DRAM at 0x40000000 */ /* DRAM at 0x40000000 */
memory_region_init_ram(ram, NULL, "mcf5208.ram", ram_size); cpu_register_physical_memory(0x40000000, ram_size,
memory_region_add_subregion(address_space_mem, 0x40000000, ram); qemu_ram_alloc(NULL, "mcf5208.ram", ram_size) | IO_MEM_RAM);
/* Internal SRAM. */ /* Internal SRAM. */
memory_region_init_ram(sram, NULL, "mcf5208.sram", 16384); cpu_register_physical_memory(0x80000000, 16384,
memory_region_add_subregion(address_space_mem, 0x80000000, sram); qemu_ram_alloc(NULL, "mcf5208.sram", 16384) | IO_MEM_RAM);
/* Internal peripherals. */ /* Internal peripherals. */
pic = mcf_intc_init(0xfc048000, env); pic = mcf_intc_init(0xfc048000, env);
@ -227,7 +235,7 @@ static void mcf5208evb_init(ram_addr_t ram_size,
mcf_uart_mm_init(0xfc064000, pic[27], serial_hds[1]); mcf_uart_mm_init(0xfc064000, pic[27], serial_hds[1]);
mcf_uart_mm_init(0xfc068000, pic[28], serial_hds[2]); mcf_uart_mm_init(0xfc068000, pic[28], serial_hds[2]);
mcf5208_sys_init(address_space_mem, pic); mcf5208_sys_init(pic);
if (nb_nics > 1) { if (nb_nics > 1) {
fprintf(stderr, "Too many NICs\n"); fprintf(stderr, "Too many NICs\n");

43
hw/milkymist-minimac2.c
View File

@ -97,8 +97,6 @@ struct MilkymistMinimac2State {
NICConf conf; NICConf conf;
char *phy_model; char *phy_model;
target_phys_addr_t buffers_base; target_phys_addr_t buffers_base;
MemoryRegion buffers;
MemoryRegion regs_region;
qemu_irq rx_irq; qemu_irq rx_irq;
qemu_irq tx_irq; qemu_irq tx_irq;
@ -322,8 +320,8 @@ static ssize_t minimac2_rx(VLANClientState *nc, const uint8_t *buf, size_t size)
return size; return size;
} }
static uint64_t static uint32_t
minimac2_read(void *opaque, target_phys_addr_t addr, unsigned size) minimac2_read(void *opaque, target_phys_addr_t addr)
{ {
MilkymistMinimac2State *s = opaque; MilkymistMinimac2State *s = opaque;
uint32_t r = 0; uint32_t r = 0;
@ -352,8 +350,7 @@ minimac2_read(void *opaque, target_phys_addr_t addr, unsigned size)
} }
static void static void
minimac2_write(void *opaque, target_phys_addr_t addr, uint64_t value, minimac2_write(void *opaque, target_phys_addr_t addr, uint32_t value)
unsigned size)
{ {
MilkymistMinimac2State *s = opaque; MilkymistMinimac2State *s = opaque;
@ -398,14 +395,16 @@ minimac2_write(void *opaque, target_phys_addr_t addr, uint64_t value,
} }
} }
static const MemoryRegionOps minimac2_ops = { static CPUReadMemoryFunc * const minimac2_read_fn[] = {
.read = minimac2_read, NULL,
.write = minimac2_write, NULL,
.valid = { &minimac2_read,
.min_access_size = 4, };
.max_access_size = 4,
}, static CPUWriteMemoryFunc * const minimac2_write_fn[] = {
.endianness = DEVICE_NATIVE_ENDIAN, NULL,
NULL,
&minimac2_write,
}; };
static int minimac2_can_rx(VLANClientState *nc) static int minimac2_can_rx(VLANClientState *nc)
@ -458,23 +457,25 @@ static NetClientInfo net_milkymist_minimac2_info = {
static int milkymist_minimac2_init(SysBusDevice *dev) static int milkymist_minimac2_init(SysBusDevice *dev)
{ {
MilkymistMinimac2State *s = FROM_SYSBUS(typeof(*s), dev); MilkymistMinimac2State *s = FROM_SYSBUS(typeof(*s), dev);
int regs;
ram_addr_t buffers;
size_t buffers_size = TARGET_PAGE_ALIGN(3 * MINIMAC2_BUFFER_SIZE); size_t buffers_size = TARGET_PAGE_ALIGN(3 * MINIMAC2_BUFFER_SIZE);
sysbus_init_irq(dev, &s->rx_irq); sysbus_init_irq(dev, &s->rx_irq);
sysbus_init_irq(dev, &s->tx_irq); sysbus_init_irq(dev, &s->tx_irq);
memory_region_init_io(&s->regs_region, &minimac2_ops, s, regs = cpu_register_io_memory(minimac2_read_fn, minimac2_write_fn, s,
"minimac2-mmio", R_MAX * 4); DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio_region(dev, &s->regs_region); sysbus_init_mmio(dev, R_MAX * 4, regs);
/* register buffers memory */ /* register buffers memory */
memory_region_init_ram(&s->buffers, NULL, "milkymist_minimac2.buffers", buffers = qemu_ram_alloc(NULL, "milkymist_minimac2.buffers", buffers_size);
buffers_size); s->rx0_buf = qemu_get_ram_ptr(buffers);
s->rx0_buf = memory_region_get_ram_ptr(&s->buffers);
s->rx1_buf = s->rx0_buf + MINIMAC2_BUFFER_SIZE; s->rx1_buf = s->rx0_buf + MINIMAC2_BUFFER_SIZE;
s->tx_buf = s->rx1_buf + MINIMAC2_BUFFER_SIZE; s->tx_buf = s->rx1_buf + MINIMAC2_BUFFER_SIZE;
sysbus_add_memory(dev, s->buffers_base, &s->buffers); cpu_register_physical_memory(s->buffers_base, buffers_size,
buffers | IO_MEM_RAM);
qemu_macaddr_default_if_unset(&s->conf.macaddr); qemu_macaddr_default_if_unset(&s->conf.macaddr);
s->nic = qemu_new_nic(&net_milkymist_minimac2_info, &s->conf, s->nic = qemu_new_nic(&net_milkymist_minimac2_info, &s->conf,

48
hw/milkymist-softusb.c
View File

@ -49,9 +49,6 @@ struct MilkymistSoftUsbState {
HIDState hid_kbd; HIDState hid_kbd;
HIDState hid_mouse; HIDState hid_mouse;
MemoryRegion regs_region;
MemoryRegion pmem;
MemoryRegion dmem;
qemu_irq irq; qemu_irq irq;
/* device properties */ /* device properties */
@ -71,8 +68,7 @@ struct MilkymistSoftUsbState {
}; };
typedef struct MilkymistSoftUsbState MilkymistSoftUsbState; typedef struct MilkymistSoftUsbState MilkymistSoftUsbState;
static uint64_t softusb_read(void *opaque, target_phys_addr_t addr, static uint32_t softusb_read(void *opaque, target_phys_addr_t addr)
unsigned size)
{ {
MilkymistSoftUsbState *s = opaque; MilkymistSoftUsbState *s = opaque;
uint32_t r = 0; uint32_t r = 0;
@ -95,8 +91,7 @@ static uint64_t softusb_read(void *opaque, target_phys_addr_t addr,
} }
static void static void
softusb_write(void *opaque, target_phys_addr_t addr, uint64_t value, softusb_write(void *opaque, target_phys_addr_t addr, uint32_t value)
unsigned size)
{ {
MilkymistSoftUsbState *s = opaque; MilkymistSoftUsbState *s = opaque;
@ -115,14 +110,16 @@ softusb_write(void *opaque, target_phys_addr_t addr, uint64_t value,
} }
} }
static const MemoryRegionOps softusb_mmio_ops = { static CPUReadMemoryFunc * const softusb_read_fn[] = {
.read = softusb_read, NULL,
.write = softusb_write, NULL,
.endianness = DEVICE_NATIVE_ENDIAN, &softusb_read,
.valid = { };
.min_access_size = 4,
.max_access_size = 4, static CPUWriteMemoryFunc * const softusb_write_fn[] = {
}, NULL,
NULL,
&softusb_write,
}; };
static inline void softusb_read_dmem(MilkymistSoftUsbState *s, static inline void softusb_read_dmem(MilkymistSoftUsbState *s,
@ -259,20 +256,23 @@ static void milkymist_softusb_reset(DeviceState *d)
static int milkymist_softusb_init(SysBusDevice *dev) static int milkymist_softusb_init(SysBusDevice *dev)
{ {
MilkymistSoftUsbState *s = FROM_SYSBUS(typeof(*s), dev); MilkymistSoftUsbState *s = FROM_SYSBUS(typeof(*s), dev);
int softusb_regs;
ram_addr_t pmem_ram;
ram_addr_t dmem_ram;
sysbus_init_irq(dev, &s->irq); sysbus_init_irq(dev, &s->irq);
memory_region_init_io(&s->regs_region, &softusb_mmio_ops, s, softusb_regs = cpu_register_io_memory(softusb_read_fn, softusb_write_fn, s,
"milkymist-softusb", R_MAX * 4); DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio_region(dev, &s->regs_region); sysbus_init_mmio(dev, R_MAX * 4, softusb_regs);
/* register pmem and dmem */ /* register pmem and dmem */
memory_region_init_ram(&s->pmem, NULL, "milkymist_softusb.pmem", pmem_ram = qemu_ram_alloc(NULL, "milkymist_softusb.pmem", s->pmem_size);
s->pmem_size); cpu_register_physical_memory(s->pmem_base, s->pmem_size,
sysbus_add_memory(dev, s->pmem_base, &s->pmem); pmem_ram | IO_MEM_RAM);
memory_region_init_ram(&s->dmem, NULL, "milkymist_softusb.dmem", dmem_ram = qemu_ram_alloc(NULL, "milkymist_softusb.dmem", s->dmem_size);
s->dmem_size); cpu_register_physical_memory(s->dmem_base, s->dmem_size,
sysbus_add_memory(dev, s->dmem_base, &s->dmem); dmem_ram | IO_MEM_RAM);
hid_init(&s->hid_kbd, HID_KEYBOARD, softusb_kbd_hid_datain); hid_init(&s->hid_kbd, HID_KEYBOARD, softusb_kbd_hid_datain);
hid_init(&s->hid_mouse, HID_MOUSE, softusb_mouse_hid_datain); hid_init(&s->hid_mouse, HID_MOUSE, softusb_mouse_hid_datain);

16
hw/milkymist.c
View File

@ -29,7 +29,6 @@
#include "blockdev.h" #include "blockdev.h"
#include "milkymist-hw.h" #include "milkymist-hw.h"
#include "lm32.h" #include "lm32.h"
#include "exec-memory.h"
#define BIOS_FILENAME "mmone-bios.bin" #define BIOS_FILENAME "mmone-bios.bin"
#define BIOS_OFFSET 0x00860000 #define BIOS_OFFSET 0x00860000
@ -82,9 +81,8 @@ milkymist_init(ram_addr_t ram_size_not_used,
CPUState *env; CPUState *env;
int kernel_size; int kernel_size;
DriveInfo *dinfo; DriveInfo *dinfo;
MemoryRegion *address_space_mem = get_system_memory(); ram_addr_t phys_sdram;
MemoryRegion *phys_sdram = g_new(MemoryRegion, 1); ram_addr_t phys_flash;
MemoryRegion *phys_flash = g_new(MemoryRegion, 1);
qemu_irq irq[32], *cpu_irq; qemu_irq irq[32], *cpu_irq;
int i; int i;
char *bios_filename; char *bios_filename;
@ -111,17 +109,17 @@ milkymist_init(ram_addr_t ram_size_not_used,
cpu_lm32_set_phys_msb_ignore(env, 1); cpu_lm32_set_phys_msb_ignore(env, 1);
memory_region_init_ram(phys_sdram, NULL, "milkymist.sdram", sdram_size); phys_sdram = qemu_ram_alloc(NULL, "milkymist.sdram", sdram_size);
memory_region_add_subregion(address_space_mem, sdram_base, phys_sdram); cpu_register_physical_memory(sdram_base, sdram_size,
phys_sdram | IO_MEM_RAM);
memory_region_init_rom_device(phys_flash, &pflash_cfi01_ops_be, phys_flash = qemu_ram_alloc(NULL, "milkymist.flash", flash_size);
NULL, "milkymist.flash", flash_size);
dinfo = drive_get(IF_PFLASH, 0, 0); dinfo = drive_get(IF_PFLASH, 0, 0);
/* Numonyx JS28F256J3F105 */ /* Numonyx JS28F256J3F105 */
pflash_cfi01_register(flash_base, phys_flash, pflash_cfi01_register(flash_base, phys_flash,
dinfo ? dinfo->bdrv : NULL, flash_sector_size, dinfo ? dinfo->bdrv : NULL, flash_sector_size,
flash_size / flash_sector_size, 2, flash_size / flash_sector_size, 2,
0x00, 0x89, 0x00, 0x1d); 0x00, 0x89, 0x00, 0x1d, 1);
/* create irq lines */ /* create irq lines */
cpu_irq = qemu_allocate_irqs(cpu_irq_handler, env, 1); cpu_irq = qemu_allocate_irqs(cpu_irq_handler, env, 1);

4
hw/mips.h
View File

@ -2,8 +2,6 @@
#define HW_MIPS_H #define HW_MIPS_H
/* Definitions for mips board emulation. */ /* Definitions for mips board emulation. */
#include "memory.h"
/* gt64xxx.c */ /* gt64xxx.c */
PCIBus *gt64120_register(qemu_irq *pic); PCIBus *gt64120_register(qemu_irq *pic);
@ -11,7 +9,7 @@ PCIBus *gt64120_register(qemu_irq *pic);
PCIBus *bonito_init(qemu_irq *pic); PCIBus *bonito_init(qemu_irq *pic);
/* g364fb.c */ /* g364fb.c */
int g364fb_mm_init(MemoryRegion *system_memory, target_phys_addr_t vram_base, int g364fb_mm_init(target_phys_addr_t vram_base,
target_phys_addr_t ctrl_base, int it_shift, target_phys_addr_t ctrl_base, int it_shift,
qemu_irq irq); qemu_irq irq);

3
hw/mips_jazz.c
View File

@ -195,8 +195,7 @@ void mips_jazz_init (ram_addr_t ram_size,
/* Video card */ /* Video card */
switch (jazz_model) { switch (jazz_model) {
case JAZZ_MAGNUM: case JAZZ_MAGNUM:
g364fb_mm_init(get_system_memory(), 0x40000000, 0x60000000, 0, g364fb_mm_init(0x40000000, 0x60000000, 0, rc4030[3]);
rc4030[3]);
break; break;
case JAZZ_PICA61: case JAZZ_PICA61:
isa_vga_mm_init(0x40000000, 0x60000000, 0, get_system_memory()); isa_vga_mm_init(0x40000000, 0x60000000, 0, get_system_memory());

45
hw/mips_malta.c
View File

@ -46,7 +46,6 @@
#include "elf.h" #include "elf.h"
#include "mc146818rtc.h" #include "mc146818rtc.h"
#include "blockdev.h" #include "blockdev.h"
#include "exec-memory.h"
//#define DEBUG_BOARD_INIT //#define DEBUG_BOARD_INIT
@ -763,10 +762,7 @@ void mips_malta_init (ram_addr_t ram_size,
{ {
char *filename; char *filename;
ram_addr_t ram_offset; ram_addr_t ram_offset;
MemoryRegion *address_space_mem = get_system_memory(); ram_addr_t bios_offset;
MemoryRegion *bios = g_new(MemoryRegion, 1);
MemoryRegion *bios_1e0 = g_new(MemoryRegion, 1);
MemoryRegion *bios_1fc = g_new(MemoryRegion, 1);
target_long bios_size; target_long bios_size;
int64_t kernel_entry; int64_t kernel_entry;
PCIBus *pci_bus; PCIBus *pci_bus;
@ -781,7 +777,7 @@ void mips_malta_init (ram_addr_t ram_size,
DriveInfo *fd[MAX_FD]; DriveInfo *fd[MAX_FD];
int fl_idx = 0; int fl_idx = 0;
int fl_sectors = 0; int fl_sectors = 0;
const MemoryRegionOps *bios_ops; int be;
/* Make sure the first 3 serial ports are associated with a device. */ /* Make sure the first 3 serial ports are associated with a device. */
for(i = 0; i < 3; i++) { for(i = 0; i < 3; i++) {
@ -814,24 +810,23 @@ void mips_malta_init (ram_addr_t ram_size,
((unsigned int)ram_size / (1 << 20))); ((unsigned int)ram_size / (1 << 20)));
exit(1); exit(1);
} }
#ifdef TARGET_WORDS_BIGENDIAN
bios_ops = &pflash_cfi01_ops_be;
#else
bios_ops = &pflash_cfi01_ops_le;
#endif
ram_offset = qemu_ram_alloc(NULL, "mips_malta.ram", ram_size); ram_offset = qemu_ram_alloc(NULL, "mips_malta.ram", ram_size);
memory_region_init_rom_device(bios, bios_ops, NULL, bios_offset = qemu_ram_alloc(NULL, "mips_malta.bios", BIOS_SIZE);
"mips_malta.bios", BIOS_SIZE);
cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM); cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
/* Map the bios at two physical locations, as on the real board. */ /* Map the bios at two physical locations, as on the real board. */
memory_region_init_alias(bios_1e0, "bios-1e0", bios, 0, BIOS_SIZE); cpu_register_physical_memory(0x1e000000LL,
memory_region_add_subregion(address_space_mem, 0x1e000000LL, bios_1e0); BIOS_SIZE, bios_offset | IO_MEM_ROM);
memory_region_init_alias(bios_1fc, "bios-1fc", bios, 0, BIOS_SIZE); cpu_register_physical_memory(0x1fc00000LL,
memory_region_add_subregion(address_space_mem, 0x1fc00000LL, bios_1fc); BIOS_SIZE, bios_offset | IO_MEM_ROM);
#ifdef TARGET_WORDS_BIGENDIAN
be = 1;
#else
be = 0;
#endif
/* FPGA */ /* FPGA */
malta_fpga_init(0x1f000000LL, env->irq[2], serial_hds[2]); malta_fpga_init(0x1f000000LL, env->irq[2], serial_hds[2]);
@ -843,7 +838,7 @@ void mips_malta_init (ram_addr_t ram_size,
loaderparams.kernel_cmdline = kernel_cmdline; loaderparams.kernel_cmdline = kernel_cmdline;
loaderparams.initrd_filename = initrd_filename; loaderparams.initrd_filename = initrd_filename;
kernel_entry = load_kernel(); kernel_entry = load_kernel();
write_bootloader(env, memory_region_get_ram_ptr(bios), kernel_entry); write_bootloader(env, qemu_get_ram_ptr(bios_offset), kernel_entry);
} else { } else {
dinfo = drive_get(IF_PFLASH, 0, fl_idx); dinfo = drive_get(IF_PFLASH, 0, fl_idx);
if (dinfo) { if (dinfo) {
@ -852,13 +847,13 @@ void mips_malta_init (ram_addr_t ram_size,
fl_sectors = bios_size >> 16; fl_sectors = bios_size >> 16;
#ifdef DEBUG_BOARD_INIT #ifdef DEBUG_BOARD_INIT
printf("Register parallel flash %d size " TARGET_FMT_lx " at " printf("Register parallel flash %d size " TARGET_FMT_lx " at "
"addr %08llx '%s' %x\n", "offset %08lx addr %08llx '%s' %x\n",
fl_idx, bios_size, 0x1e000000LL, fl_idx, bios_size, bios_offset, 0x1e000000LL,
bdrv_get_device_name(dinfo->bdrv), fl_sectors); bdrv_get_device_name(dinfo->bdrv), fl_sectors);
#endif #endif
pflash_cfi01_register(0x1e000000LL, bios, pflash_cfi01_register(0x1e000000LL, bios_offset,
dinfo->bdrv, 65536, fl_sectors, dinfo->bdrv, 65536, fl_sectors,
4, 0x0000, 0x0000, 0x0000, 0x0000); 4, 0x0000, 0x0000, 0x0000, 0x0000, be);
fl_idx++; fl_idx++;
} else { } else {
/* Load a BIOS image. */ /* Load a BIOS image. */
@ -883,7 +878,7 @@ void mips_malta_init (ram_addr_t ram_size,
a neat trick which allows bi-endian firmware. */ a neat trick which allows bi-endian firmware. */
#ifndef TARGET_WORDS_BIGENDIAN #ifndef TARGET_WORDS_BIGENDIAN
{ {
uint32_t *addr = memory_region_get_ram_ptr(bios); uint32_t *addr = qemu_get_ram_ptr(bios_offset);;
uint32_t *end = addr + bios_size; uint32_t *end = addr + bios_size;
while (addr < end) { while (addr < end) {
bswap32s(addr); bswap32s(addr);
@ -895,7 +890,7 @@ void mips_malta_init (ram_addr_t ram_size,
/* Board ID = 0x420 (Malta Board with CoreLV) /* Board ID = 0x420 (Malta Board with CoreLV)
XXX: theoretically 0x1e000010 should map to flash and 0x1fc00010 should XXX: theoretically 0x1e000010 should map to flash and 0x1fc00010 should
map to the board ID. */ map to the board ID. */
stl_p(memory_region_get_ram_ptr(bios) + 0x10, 0x00000420); stl_p(qemu_get_ram_ptr(bios_offset) + 0x10, 0x00000420);
/* Init internal devices */ /* Init internal devices */
cpu_mips_irq_init_cpu(env); cpu_mips_irq_init_cpu(env);

20
hw/mips_r4k.c
View File

@ -23,7 +23,6 @@
#include "elf.h" #include "elf.h"
#include "mc146818rtc.h" #include "mc146818rtc.h"
#include "blockdev.h" #include "blockdev.h"
#include "exec-memory.h"
#define MAX_IDE_BUS 2 #define MAX_IDE_BUS 2
@ -164,8 +163,7 @@ void mips_r4k_init (ram_addr_t ram_size,
{ {
char *filename; char *filename;
ram_addr_t ram_offset; ram_addr_t ram_offset;
MemoryRegion *address_space_mem = get_system_memory(); ram_addr_t bios_offset;
MemoryRegion *bios = g_new(MemoryRegion, 1);
int bios_size; int bios_size;
CPUState *env; CPUState *env;
ResetData *reset_info; ResetData *reset_info;
@ -229,20 +227,18 @@ void mips_r4k_init (ram_addr_t ram_size,
be = 0; be = 0;
#endif #endif
if ((bios_size > 0) && (bios_size <= BIOS_SIZE)) { if ((bios_size > 0) && (bios_size <= BIOS_SIZE)) {
memory_region_init_ram(bios, NULL, "mips_r4k.bios", BIOS_SIZE); bios_offset = qemu_ram_alloc(NULL, "mips_r4k.bios", BIOS_SIZE);
memory_region_set_readonly(bios, true); cpu_register_physical_memory(0x1fc00000, BIOS_SIZE,
memory_region_add_subregion(address_space_mem, 0x1fc00000, bios); bios_offset | IO_MEM_ROM);
load_image_targphys(filename, 0x1fc00000, BIOS_SIZE); load_image_targphys(filename, 0x1fc00000, BIOS_SIZE);
} else if ((dinfo = drive_get(IF_PFLASH, 0, 0)) != NULL) { } else if ((dinfo = drive_get(IF_PFLASH, 0, 0)) != NULL) {
uint32_t mips_rom = 0x00400000; uint32_t mips_rom = 0x00400000;
memory_region_init_rom_device(bios, bios_offset = qemu_ram_alloc(NULL, "mips_r4k.bios", mips_rom);
(be ? &pflash_cfi01_ops_be if (!pflash_cfi01_register(0x1fc00000, bios_offset,
: &pflash_cfi01_ops_le),
NULL, "mips_r4k.bios", mips_rom);
if (!pflash_cfi01_register(0x1fc00000, bios,
dinfo->bdrv, sector_len, dinfo->bdrv, sector_len,
mips_rom / sector_len, mips_rom / sector_len,
4, 0, 0, 0, 0)) { 4, 0, 0, 0, 0, be)) {
fprintf(stderr, "qemu: Error registering flash memory.\n"); fprintf(stderr, "qemu: Error registering flash memory.\n");
} }
} }

15
hw/musicpal.c
View File

@ -1502,7 +1502,6 @@ static void musicpal_init(ram_addr_t ram_size,
unsigned long flash_size; unsigned long flash_size;
DriveInfo *dinfo; DriveInfo *dinfo;
ram_addr_t sram_off; ram_addr_t sram_off;
MemoryRegion *flash = g_new(MemoryRegion, 1);
if (!cpu_model) { if (!cpu_model) {
cpu_model = "arm926"; cpu_model = "arm926";
@ -1566,23 +1565,21 @@ static void musicpal_init(ram_addr_t ram_size,
* image is smaller than 32 MB. * image is smaller than 32 MB.
*/ */
#ifdef TARGET_WORDS_BIGENDIAN #ifdef TARGET_WORDS_BIGENDIAN
memory_region_init_rom_device(flash, &pflash_cfi02_ops_be, pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, qemu_ram_alloc(NULL,
NULL, "musicpal.flash", flash_size); "musicpal.flash", flash_size),
pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, flash,
dinfo->bdrv, 0x10000, dinfo->bdrv, 0x10000,
(flash_size + 0xffff) >> 16, (flash_size + 0xffff) >> 16,
MP_FLASH_SIZE_MAX / flash_size, MP_FLASH_SIZE_MAX / flash_size,
2, 0x00BF, 0x236D, 0x0000, 0x0000, 2, 0x00BF, 0x236D, 0x0000, 0x0000,
0x5555, 0x2AAA); 0x5555, 0x2AAA, 1);
#else #else
memory_region_init_rom_device(flash, &pflash_cfi02_ops_le, pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, qemu_ram_alloc(NULL,
NULL, "musicpal.flash", flash_size); "musicpal.flash", flash_size),
pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, flash,
dinfo->bdrv, 0x10000, dinfo->bdrv, 0x10000,
(flash_size + 0xffff) >> 16, (flash_size + 0xffff) >> 16,
MP_FLASH_SIZE_MAX / flash_size, MP_FLASH_SIZE_MAX / flash_size,
2, 0x00BF, 0x236D, 0x0000, 0x0000, 2, 0x00BF, 0x236D, 0x0000, 0x0000,
0x5555, 0x2AAA); 0x5555, 0x2AAA, 0);
#endif #endif
} }

21
hw/omap_sx1.c
View File

@ -129,8 +129,7 @@ static void sx1_init(ram_addr_t ram_size,
DriveInfo *dinfo; DriveInfo *dinfo;
int fl_idx; int fl_idx;
uint32_t flash_size = flash0_size; uint32_t flash_size = flash0_size;
const MemoryRegionOps *flash_ops; int be;
MemoryRegion *flash = g_new(MemoryRegion, 2);
if (version == 2) { if (version == 2) {
flash_size = flash2_size; flash_size = flash2_size;
@ -156,18 +155,17 @@ static void sx1_init(ram_addr_t ram_size,
fl_idx = 0; fl_idx = 0;
#ifdef TARGET_WORDS_BIGENDIAN #ifdef TARGET_WORDS_BIGENDIAN
flash_ops = &pflash_cfi01_ops_be; be = 1;
#else #else
flash_ops = &pflash_cfi01_ops_le; be = 0;
#endif #endif
if ((dinfo = drive_get(IF_PFLASH, 0, fl_idx)) != NULL) { if ((dinfo = drive_get(IF_PFLASH, 0, fl_idx)) != NULL) {
memory_region_init_rom_device(&flash[0], flash_ops, if (!pflash_cfi01_register(OMAP_CS0_BASE, qemu_ram_alloc(NULL,
NULL, "omap_sx1.flash0-1", flash_size); "omap_sx1.flash0-1", flash_size),
if (!pflash_cfi01_register(OMAP_CS0_BASE, &flash[0],
dinfo->bdrv, sector_size, dinfo->bdrv, sector_size,
flash_size / sector_size, flash_size / sector_size,
4, 0, 0, 0, 0)) { 4, 0, 0, 0, 0, be)) {
fprintf(stderr, "qemu: Error registering flash memory %d.\n", fprintf(stderr, "qemu: Error registering flash memory %d.\n",
fl_idx); fl_idx);
} }
@ -184,12 +182,11 @@ static void sx1_init(ram_addr_t ram_size,
cpu_register_physical_memory(OMAP_CS1_BASE + flash1_size, cpu_register_physical_memory(OMAP_CS1_BASE + flash1_size,
OMAP_CS1_SIZE - flash1_size, io); OMAP_CS1_SIZE - flash1_size, io);
memory_region_init_rom_device(&flash[1], flash_ops, if (!pflash_cfi01_register(OMAP_CS1_BASE, qemu_ram_alloc(NULL,
NULL, "omap_sx1.flash1-1", flash1_size); "omap_sx1.flash1-1", flash1_size),
if (!pflash_cfi01_register(OMAP_CS1_BASE, &flash[1],
dinfo->bdrv, sector_size, dinfo->bdrv, sector_size,
flash1_size / sector_size, flash1_size / sector_size,
4, 0, 0, 0, 0)) { 4, 0, 0, 0, 0, be)) {
fprintf(stderr, "qemu: Error registering flash memory %d.\n", fprintf(stderr, "qemu: Error registering flash memory %d.\n",
fl_idx); fl_idx);
} }

86
hw/pci_host.c
View File

@ -94,72 +94,82 @@ uint32_t pci_data_read(PCIBus *s, uint32_t addr, int len)
return val; return val;
} }
static void pci_host_config_write(void *opaque, target_phys_addr_t addr, static void pci_host_config_write(ReadWriteHandler *handler,
uint64_t val, unsigned len) pcibus_t addr, uint32_t val, int len)
{ {
PCIHostState *s = opaque; PCIHostState *s = container_of(handler, PCIHostState, conf_handler);
PCI_DPRINTF("%s addr " TARGET_FMT_plx " len %d val %"PRIx64"\n", PCI_DPRINTF("%s addr %" FMT_PCIBUS " %d val %"PRIx32"\n",
__func__, addr, len, val); __func__, addr, len, val);
s->config_reg = val; s->config_reg = val;
} }
static uint64_t pci_host_config_read(void *opaque, target_phys_addr_t addr, static uint32_t pci_host_config_read(ReadWriteHandler *handler,
unsigned len) pcibus_t addr, int len)
{ {
PCIHostState *s = opaque; PCIHostState *s = container_of(handler, PCIHostState, conf_handler);
uint32_t val = s->config_reg; uint32_t val = s->config_reg;
PCI_DPRINTF("%s addr " TARGET_FMT_plx " len %d val %"PRIx32"\n", PCI_DPRINTF("%s addr %" FMT_PCIBUS " len %d val %"PRIx32"\n",
__func__, addr, len, val); __func__, addr, len, val);
return val; return val;
} }
static void pci_host_data_write(void *opaque, target_phys_addr_t addr, static void pci_host_data_write(ReadWriteHandler *handler,
uint64_t val, unsigned len) pcibus_t addr, uint32_t val, int len)
{ {
PCIHostState *s = opaque; PCIHostState *s = container_of(handler, PCIHostState, data_handler);
PCI_DPRINTF("write addr " TARGET_FMT_plx " len %d val %x\n", PCI_DPRINTF("write addr %" FMT_PCIBUS " len %d val %x\n",
addr, len, (unsigned)val); addr, len, val);
if (s->config_reg & (1u << 31)) if (s->config_reg & (1u << 31))
pci_data_write(s->bus, s->config_reg | (addr & 3), val, len); pci_data_write(s->bus, s->config_reg | (addr & 3), val, len);
} }
static uint64_t pci_host_data_read(void *opaque, static uint32_t pci_host_data_read(ReadWriteHandler *handler,
target_phys_addr_t addr, unsigned len) pcibus_t addr, int len)
{ {
PCIHostState *s = opaque; PCIHostState *s = container_of(handler, PCIHostState, data_handler);
uint32_t val; uint32_t val;
if (!(s->config_reg & (1 << 31))) if (!(s->config_reg & (1 << 31)))
return 0xffffffff; return 0xffffffff;
val = pci_data_read(s->bus, s->config_reg | (addr & 3), len); val = pci_data_read(s->bus, s->config_reg | (addr & 3), len);
PCI_DPRINTF("read addr " TARGET_FMT_plx " len %d val %x\n", PCI_DPRINTF("read addr %" FMT_PCIBUS " len %d val %x\n",
addr, len, val); addr, len, val);
return val; return val;
} }
const MemoryRegionOps pci_host_conf_le_ops = { static void pci_host_init(PCIHostState *s)
.read = pci_host_config_read, {
.write = pci_host_config_write, s->conf_handler.write = pci_host_config_write;
.endianness = DEVICE_LITTLE_ENDIAN, s->conf_handler.read = pci_host_config_read;
}; s->data_handler.write = pci_host_data_write;
s->data_handler.read = pci_host_data_read;
}
const MemoryRegionOps pci_host_conf_be_ops = { int pci_host_conf_register_mmio(PCIHostState *s, int endian)
.read = pci_host_config_read, {
.write = pci_host_config_write, pci_host_init(s);
.endianness = DEVICE_BIG_ENDIAN, return cpu_register_io_memory_simple(&s->conf_handler, endian);
}; }
const MemoryRegionOps pci_host_data_le_ops = { void pci_host_conf_register_ioport(pio_addr_t ioport, PCIHostState *s)
.read = pci_host_data_read, {
.write = pci_host_data_write, pci_host_init(s);
.endianness = DEVICE_LITTLE_ENDIAN, register_ioport_simple(&s->conf_handler, ioport, 4, 4);
}; sysbus_init_ioports(&s->busdev, ioport, 4);
}
const MemoryRegionOps pci_host_data_be_ops = {
.read = pci_host_data_read,
.write = pci_host_data_write,
.endianness = DEVICE_BIG_ENDIAN,
};
int pci_host_data_register_mmio(PCIHostState *s, int endian)
{
pci_host_init(s);
return cpu_register_io_memory_simple(&s->data_handler, endian);
}
void pci_host_data_register_ioport(pio_addr_t ioport, PCIHostState *s)
{
pci_host_init(s);
register_ioport_simple(&s->data_handler, ioport, 4, 1);
register_ioport_simple(&s->data_handler, ioport, 4, 2);
register_ioport_simple(&s->data_handler, ioport, 4, 4);
sysbus_init_ioports(&s->busdev, ioport, 4);
}

16
hw/pci_host.h
View File

@ -29,11 +29,12 @@
#define PCI_HOST_H #define PCI_HOST_H
#include "sysbus.h" #include "sysbus.h"
#include "rwhandler.h"
struct PCIHostState { struct PCIHostState {
SysBusDevice busdev; SysBusDevice busdev;
MemoryRegion conf_mem; ReadWriteHandler conf_handler;
MemoryRegion data_mem; ReadWriteHandler data_handler;
MemoryRegion *address_space; MemoryRegion *address_space;
uint32_t config_reg; uint32_t config_reg;
PCIBus *bus; PCIBus *bus;
@ -48,9 +49,12 @@ uint32_t pci_host_config_read_common(PCIDevice *pci_dev, uint32_t addr,
void pci_data_write(PCIBus *s, uint32_t addr, uint32_t val, int len); void pci_data_write(PCIBus *s, uint32_t addr, uint32_t val, int len);
uint32_t pci_data_read(PCIBus *s, uint32_t addr, int len); uint32_t pci_data_read(PCIBus *s, uint32_t addr, int len);
extern const MemoryRegionOps pci_host_conf_le_ops; /* for mmio */
extern const MemoryRegionOps pci_host_conf_be_ops; int pci_host_conf_register_mmio(PCIHostState *s, int endian);
extern const MemoryRegionOps pci_host_data_le_ops; int pci_host_data_register_mmio(PCIHostState *s, int endian);
extern const MemoryRegionOps pci_host_data_be_ops;
/* for ioio */
void pci_host_conf_register_ioport(pio_addr_t ioport, PCIHostState *s);
void pci_host_data_register_ioport(pio_addr_t ioport, PCIHostState *s);
#endif /* PCI_HOST_H */ #endif /* PCI_HOST_H */

7
hw/petalogix_ml605_mmu.c
View File

@ -149,7 +149,7 @@ petalogix_ml605_init(ram_addr_t ram_size,
target_phys_addr_t ddr_base = MEMORY_BASEADDR; target_phys_addr_t ddr_base = MEMORY_BASEADDR;
ram_addr_t phys_lmb_bram; ram_addr_t phys_lmb_bram;
ram_addr_t phys_ram; ram_addr_t phys_ram;
MemoryRegion *phys_flash = g_new(MemoryRegion, 1); ram_addr_t phys_flash;
qemu_irq irq[32], *cpu_irq; qemu_irq irq[32], *cpu_irq;
/* init CPUs */ /* init CPUs */
@ -169,15 +169,14 @@ petalogix_ml605_init(ram_addr_t ram_size,
phys_ram = qemu_ram_alloc(NULL, "petalogix_ml605.ram", ram_size); phys_ram = qemu_ram_alloc(NULL, "petalogix_ml605.ram", ram_size);
cpu_register_physical_memory(ddr_base, ram_size, phys_ram | IO_MEM_RAM); cpu_register_physical_memory(ddr_base, ram_size, phys_ram | IO_MEM_RAM);
memory_region_init_rom_device(phys_flash, &pflash_cfi01_ops_le, phys_flash = qemu_ram_alloc(NULL, "petalogix_ml605.flash", FLASH_SIZE);
NULL, "petalogix_ml605.flash", FLASH_SIZE);
dinfo = drive_get(IF_PFLASH, 0, 0); dinfo = drive_get(IF_PFLASH, 0, 0);
/* 5th parameter 2 means bank-width /* 5th parameter 2 means bank-width
* 10th paremeter 0 means little-endian */ * 10th paremeter 0 means little-endian */
pflash_cfi01_register(FLASH_BASEADDR, phys_flash, pflash_cfi01_register(FLASH_BASEADDR, phys_flash,
dinfo ? dinfo->bdrv : NULL, (64 * 1024), dinfo ? dinfo->bdrv : NULL, (64 * 1024),
FLASH_SIZE >> 16, FLASH_SIZE >> 16,
2, 0x89, 0x18, 0x0000, 0x0); 2, 0x89, 0x18, 0x0000, 0x0, 0);
cpu_irq = microblaze_pic_init_cpu(env); cpu_irq = microblaze_pic_init_cpu(env);

8
hw/petalogix_s3adsp1800_mmu.c
View File

@ -127,7 +127,7 @@ petalogix_s3adsp1800_init(ram_addr_t ram_size,
target_phys_addr_t ddr_base = 0x90000000; target_phys_addr_t ddr_base = 0x90000000;
ram_addr_t phys_lmb_bram; ram_addr_t phys_lmb_bram;
ram_addr_t phys_ram; ram_addr_t phys_ram;
MemoryRegion *phys_flash = g_new(MemoryRegion, 1); ram_addr_t phys_flash;
qemu_irq irq[32], *cpu_irq; qemu_irq irq[32], *cpu_irq;
/* init CPUs */ /* init CPUs */
@ -148,14 +148,12 @@ petalogix_s3adsp1800_init(ram_addr_t ram_size,
phys_ram = qemu_ram_alloc(NULL, "petalogix_s3adsp1800.ram", ram_size); phys_ram = qemu_ram_alloc(NULL, "petalogix_s3adsp1800.ram", ram_size);
cpu_register_physical_memory(ddr_base, ram_size, phys_ram | IO_MEM_RAM); cpu_register_physical_memory(ddr_base, ram_size, phys_ram | IO_MEM_RAM);
memory_region_init_rom_device(phys_flash, &pflash_cfi01_ops_be, phys_flash = qemu_ram_alloc(NULL, "petalogix_s3adsp1800.flash", FLASH_SIZE);
NULL, "petalogix_s3adsp1800.flash",
FLASH_SIZE);
dinfo = drive_get(IF_PFLASH, 0, 0); dinfo = drive_get(IF_PFLASH, 0, 0);
pflash_cfi01_register(0xa0000000, phys_flash, pflash_cfi01_register(0xa0000000, phys_flash,
dinfo ? dinfo->bdrv : NULL, (64 * 1024), dinfo ? dinfo->bdrv : NULL, (64 * 1024),
FLASH_SIZE >> 16, FLASH_SIZE >> 16,
1, 0x89, 0x18, 0x0000, 0x0); 1, 0x89, 0x18, 0x0000, 0x0, 1);
cpu_irq = microblaze_pic_init_cpu(env); cpu_irq = microblaze_pic_init_cpu(env);
dev = xilinx_intc_create(0x81800000, cpu_irq[0], 2); dev = xilinx_intc_create(0x81800000, cpu_irq[0], 2);

67
hw/pflash_cfi01.c
View File

@ -40,7 +40,6 @@
#include "flash.h" #include "flash.h"
#include "block.h" #include "block.h"
#include "qemu-timer.h" #include "qemu-timer.h"
#include "exec-memory.h"
#define PFLASH_BUG(fmt, ...) \ #define PFLASH_BUG(fmt, ...) \
do { \ do { \
@ -75,7 +74,8 @@ struct pflash_t {
target_phys_addr_t counter; target_phys_addr_t counter;
unsigned int writeblock_size; unsigned int writeblock_size;
QEMUTimer *timer; QEMUTimer *timer;
MemoryRegion *mem; ram_addr_t off;
int fl_mem;
void *storage; void *storage;
}; };
@ -89,7 +89,8 @@ static void pflash_timer (void *opaque)
if (pfl->bypass) { if (pfl->bypass) {
pfl->wcycle = 2; pfl->wcycle = 2;
} else { } else {
memory_region_rom_device_set_readable(pfl->mem, true); cpu_register_physical_memory(pfl->base, pfl->total_len,
pfl->off | IO_MEM_ROMD | pfl->fl_mem);
pfl->wcycle = 0; pfl->wcycle = 0;
} }
pfl->cmd = 0; pfl->cmd = 0;
@ -262,7 +263,7 @@ static void pflash_write(pflash_t *pfl, target_phys_addr_t offset,
if (!pfl->wcycle) { if (!pfl->wcycle) {
/* Set the device in I/O access mode */ /* Set the device in I/O access mode */
memory_region_rom_device_set_readable(pfl->mem, false); cpu_register_physical_memory(pfl->base, pfl->total_len, pfl->fl_mem);
} }
switch (pfl->wcycle) { switch (pfl->wcycle) {
@ -421,7 +422,8 @@ static void pflash_write(pflash_t *pfl, target_phys_addr_t offset,
__func__, offset, pfl->wcycle, pfl->cmd, value); __func__, offset, pfl->wcycle, pfl->cmd, value);
reset_flash: reset_flash:
memory_region_rom_device_set_readable(pfl->mem, true); cpu_register_physical_memory(pfl->base, pfl->total_len,
pfl->off | IO_MEM_ROMD | pfl->fl_mem);
pfl->bypass = 0; pfl->bypass = 0;
pfl->wcycle = 0; pfl->wcycle = 0;
@ -512,20 +514,28 @@ static void pflash_writel_le(void *opaque, target_phys_addr_t addr,
pflash_write(pfl, addr, value, 4, 0); pflash_write(pfl, addr, value, 4, 0);
} }
const MemoryRegionOps pflash_cfi01_ops_be = { static CPUWriteMemoryFunc * const pflash_write_ops_be[] = {
.old_mmio = { &pflash_writeb_be,
.read = { pflash_readb_be, pflash_readw_be, pflash_readl_be, }, &pflash_writew_be,
.write = { pflash_writeb_be, pflash_writew_be, pflash_writel_be, }, &pflash_writel_be,
},
.endianness = DEVICE_NATIVE_ENDIAN,
}; };
const MemoryRegionOps pflash_cfi01_ops_le = { static CPUReadMemoryFunc * const pflash_read_ops_be[] = {
.old_mmio = { &pflash_readb_be,
.read = { pflash_readb_le, pflash_readw_le, pflash_readl_le, }, &pflash_readw_be,
.write = { pflash_writeb_le, pflash_writew_le, pflash_writel_le, }, &pflash_readl_be,
}, };
.endianness = DEVICE_NATIVE_ENDIAN,
static CPUWriteMemoryFunc * const pflash_write_ops_le[] = {
&pflash_writeb_le,
&pflash_writew_le,
&pflash_writel_le,
};
static CPUReadMemoryFunc * const pflash_read_ops_le[] = {
&pflash_readb_le,
&pflash_readw_le,
&pflash_readl_le,
}; };
/* Count trailing zeroes of a 32 bits quantity */ /* Count trailing zeroes of a 32 bits quantity */
@ -564,11 +574,12 @@ static int ctz32 (uint32_t n)
return ret; return ret;
} }
pflash_t *pflash_cfi01_register(target_phys_addr_t base, MemoryRegion *mem, pflash_t *pflash_cfi01_register(target_phys_addr_t base, ram_addr_t off,
BlockDriverState *bs, uint32_t sector_len, BlockDriverState *bs, uint32_t sector_len,
int nb_blocs, int width, int nb_blocs, int width,
uint16_t id0, uint16_t id1, uint16_t id0, uint16_t id1,
uint16_t id2, uint16_t id3) uint16_t id2, uint16_t id3,
int be)
{ {
pflash_t *pfl; pflash_t *pfl;
target_phys_addr_t total_len; target_phys_addr_t total_len;
@ -586,16 +597,26 @@ pflash_t *pflash_cfi01_register(target_phys_addr_t base, MemoryRegion *mem,
pfl = g_malloc0(sizeof(pflash_t)); pfl = g_malloc0(sizeof(pflash_t));
/* FIXME: Allocate ram ourselves. */ /* FIXME: Allocate ram ourselves. */
pfl->storage = memory_region_get_ram_ptr(mem); pfl->storage = qemu_get_ram_ptr(off);
pfl->mem = mem; if (be) {
memory_region_add_subregion(get_system_memory(), base, mem); pfl->fl_mem = cpu_register_io_memory(pflash_read_ops_be,
pflash_write_ops_be, pfl,
DEVICE_NATIVE_ENDIAN);
} else {
pfl->fl_mem = cpu_register_io_memory(pflash_read_ops_le,
pflash_write_ops_le, pfl,
DEVICE_NATIVE_ENDIAN);
}
pfl->off = off;
cpu_register_physical_memory(base, total_len,
off | pfl->fl_mem | IO_MEM_ROMD);
pfl->bs = bs; pfl->bs = bs;
if (pfl->bs) { if (pfl->bs) {
/* read the initial flash content */ /* read the initial flash content */
ret = bdrv_read(pfl->bs, 0, pfl->storage, total_len >> 9); ret = bdrv_read(pfl->bs, 0, pfl->storage, total_len >> 9);
if (ret < 0) { if (ret < 0) {
memory_region_del_subregion(get_system_memory(), mem); cpu_unregister_io_memory(pfl->fl_mem);
g_free(pfl); g_free(pfl);
return NULL; return NULL;
} }

93
hw/pflash_cfi02.c
View File

@ -39,7 +39,6 @@
#include "flash.h" #include "flash.h"
#include "qemu-timer.h" #include "qemu-timer.h"
#include "block.h" #include "block.h"
#include "exec-memory.h"
//#define PFLASH_DEBUG //#define PFLASH_DEBUG
#ifdef PFLASH_DEBUG #ifdef PFLASH_DEBUG
@ -70,39 +69,25 @@ struct pflash_t {
uint8_t cfi_len; uint8_t cfi_len;
uint8_t cfi_table[0x52]; uint8_t cfi_table[0x52];
QEMUTimer *timer; QEMUTimer *timer;
/* The device replicates the flash memory across its memory space. Emulate ram_addr_t off;
* that by having a container (.mem) filled with an array of aliases int fl_mem;
* (.mem_mappings) pointing to the flash memory (.orig_mem).
*/
MemoryRegion mem;
MemoryRegion *mem_mappings; /* array; one per mapping */
MemoryRegion *orig_mem;
int rom_mode; int rom_mode;
int read_counter; /* used for lazy switch-back to rom mode */ int read_counter; /* used for lazy switch-back to rom mode */
void *storage; void *storage;
}; };
/*
* Set up replicated mappings of the same region.
*/
static void pflash_setup_mappings(pflash_t *pfl, MemoryRegion *mem)
{
unsigned i;
target_phys_addr_t size = memory_region_size(mem);
pfl->orig_mem = mem;
memory_region_init(&pfl->mem, "pflash", pfl->mappings * size);
pfl->mem_mappings = g_new(MemoryRegion, pfl->mappings);
for (i = 0; i < pfl->mappings; ++i) {
memory_region_init_alias(&pfl->mem_mappings[i], "pflash-alias", mem,
0, size);
memory_region_add_subregion(&pfl->mem, i * size, &pfl->mem_mappings[i]);
}
}
static void pflash_register_memory(pflash_t *pfl, int rom_mode) static void pflash_register_memory(pflash_t *pfl, int rom_mode)
{ {
memory_region_rom_device_set_readable(pfl->orig_mem, rom_mode); unsigned long phys_offset = pfl->fl_mem;
int i;
if (rom_mode)
phys_offset |= pfl->off | IO_MEM_ROMD;
pfl->rom_mode = rom_mode;
for (i = 0; i < pfl->mappings; i++)
cpu_register_physical_memory(pfl->base + i * pfl->chip_len,
pfl->chip_len, phys_offset);
} }
static void pflash_timer (void *opaque) static void pflash_timer (void *opaque)
@ -553,20 +538,28 @@ static void pflash_writel_le(void *opaque, target_phys_addr_t addr,
pflash_write(pfl, addr, value, 4, 0); pflash_write(pfl, addr, value, 4, 0);
} }
const MemoryRegionOps pflash_cfi02_ops_be = { static CPUWriteMemoryFunc * const pflash_write_ops_be[] = {
.old_mmio = { &pflash_writeb_be,
.read = { pflash_readb_be, pflash_readw_be, pflash_readl_be, }, &pflash_writew_be,
.write = { pflash_writeb_be, pflash_writew_be, pflash_writel_be, }, &pflash_writel_be,
},
.endianness = DEVICE_NATIVE_ENDIAN,
}; };
const MemoryRegionOps pflash_cfi02_ops_le = { static CPUReadMemoryFunc * const pflash_read_ops_be[] = {
.old_mmio = { &pflash_readb_be,
.read = { pflash_readb_le, pflash_readw_le, pflash_readl_le, }, &pflash_readw_be,
.write = { pflash_writeb_le, pflash_writew_le, pflash_writel_le, }, &pflash_readl_be,
}, };
.endianness = DEVICE_NATIVE_ENDIAN,
static CPUWriteMemoryFunc * const pflash_write_ops_le[] = {
&pflash_writeb_le,
&pflash_writew_le,
&pflash_writel_le,
};
static CPUReadMemoryFunc * const pflash_read_ops_le[] = {
&pflash_readb_le,
&pflash_readw_le,
&pflash_readl_le,
}; };
/* Count trailing zeroes of a 32 bits quantity */ /* Count trailing zeroes of a 32 bits quantity */
@ -605,12 +598,13 @@ static int ctz32 (uint32_t n)
return ret; return ret;
} }
pflash_t *pflash_cfi02_register(target_phys_addr_t base, MemoryRegion *mem, pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off,
BlockDriverState *bs, uint32_t sector_len, BlockDriverState *bs, uint32_t sector_len,
int nb_blocs, int nb_mappings, int width, int nb_blocs, int nb_mappings, int width,
uint16_t id0, uint16_t id1, uint16_t id0, uint16_t id1,
uint16_t id2, uint16_t id3, uint16_t id2, uint16_t id3,
uint16_t unlock_addr0, uint16_t unlock_addr1) uint16_t unlock_addr0, uint16_t unlock_addr1,
int be)
{ {
pflash_t *pfl; pflash_t *pfl;
int32_t chip_len; int32_t chip_len;
@ -625,22 +619,31 @@ pflash_t *pflash_cfi02_register(target_phys_addr_t base, MemoryRegion *mem,
#endif #endif
pfl = g_malloc0(sizeof(pflash_t)); pfl = g_malloc0(sizeof(pflash_t));
/* FIXME: Allocate ram ourselves. */ /* FIXME: Allocate ram ourselves. */
pfl->storage = memory_region_get_ram_ptr(mem); pfl->storage = qemu_get_ram_ptr(off);
if (be) {
pfl->fl_mem = cpu_register_io_memory(pflash_read_ops_be,
pflash_write_ops_be,
pfl, DEVICE_NATIVE_ENDIAN);
} else {
pfl->fl_mem = cpu_register_io_memory(pflash_read_ops_le,
pflash_write_ops_le,
pfl, DEVICE_NATIVE_ENDIAN);
}
pfl->off = off;
pfl->base = base; pfl->base = base;
pfl->chip_len = chip_len; pfl->chip_len = chip_len;
pfl->mappings = nb_mappings; pfl->mappings = nb_mappings;
pflash_register_memory(pfl, 1);
pfl->bs = bs; pfl->bs = bs;
if (pfl->bs) { if (pfl->bs) {
/* read the initial flash content */ /* read the initial flash content */
ret = bdrv_read(pfl->bs, 0, pfl->storage, chip_len >> 9); ret = bdrv_read(pfl->bs, 0, pfl->storage, chip_len >> 9);
if (ret < 0) { if (ret < 0) {
cpu_unregister_io_memory(pfl->fl_mem);
g_free(pfl); g_free(pfl);
return NULL; return NULL;
} }
} }
pflash_setup_mappings(pfl, mem);
pfl->rom_mode = 1;
memory_region_add_subregion(get_system_memory(), pfl->base, &pfl->mem);
#if 0 /* XXX: there should be a bit to set up read-only, #if 0 /* XXX: there should be a bit to set up read-only,
* the same way the hardware does (with WP pin). * the same way the hardware does (with WP pin).
*/ */

13
hw/piix_pci.c
View File

@ -142,7 +142,6 @@ static void i440fx_update_memory_mappings(PCII440FXState *d)
int i, r; int i, r;
uint32_t smram; uint32_t smram;
memory_region_transaction_begin();
update_pam(d, 0xf0000, 0x100000, (d->dev.config[I440FX_PAM] >> 4) & 3, update_pam(d, 0xf0000, 0x100000, (d->dev.config[I440FX_PAM] >> 4) & 3,
&d->pam_regions[0]); &d->pam_regions[0]);
for(i = 0; i < 12; i++) { for(i = 0; i < 12; i++) {
@ -163,7 +162,6 @@ static void i440fx_update_memory_mappings(PCII440FXState *d)
d->smram_enabled = false; d->smram_enabled = false;
} }
} }
memory_region_transaction_commit();
} }
static void i440fx_set_smm(int val, void *arg) static void i440fx_set_smm(int val, void *arg)
@ -237,16 +235,9 @@ static int i440fx_pcihost_initfn(SysBusDevice *dev)
{ {
I440FXState *s = FROM_SYSBUS(I440FXState, dev); I440FXState *s = FROM_SYSBUS(I440FXState, dev);
memory_region_init_io(&s->conf_mem, &pci_host_conf_le_ops, s, pci_host_conf_register_ioport(0xcf8, s);
"pci-conf-idx", 4);
sysbus_add_io(dev, 0xcf8, &s->conf_mem);
sysbus_init_ioports(&s->busdev, 0xcf8, 4);
memory_region_init_io(&s->data_mem, &pci_host_data_le_ops, s,
"pci-conf-data", 4);
sysbus_add_io(dev, 0xcfc, &s->data_mem);
sysbus_init_ioports(&s->busdev, 0xcfc, 4);
pci_host_data_register_ioport(0xcfc, s);
return 0; return 0;
} }

63
hw/ppc405_boards.c
View File

@ -32,7 +32,6 @@
#include "qemu-log.h" #include "qemu-log.h"
#include "loader.h" #include "loader.h"
#include "blockdev.h" #include "blockdev.h"
#include "exec-memory.h"
#define BIOS_FILENAME "ppc405_rom.bin" #define BIOS_FILENAME "ppc405_rom.bin"
#define BIOS_SIZE (2048 * 1024) #define BIOS_SIZE (2048 * 1024)
@ -182,9 +181,7 @@ static void ref405ep_init (ram_addr_t ram_size,
ppc4xx_bd_info_t bd; ppc4xx_bd_info_t bd;
CPUPPCState *env; CPUPPCState *env;
qemu_irq *pic; qemu_irq *pic;
ram_addr_t sram_offset, bdloc; ram_addr_t sram_offset, bios_offset, bdloc;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *bios = g_new(MemoryRegion, 1);
MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories)); MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories));
target_phys_addr_t ram_bases[2], ram_sizes[2]; target_phys_addr_t ram_bases[2], ram_sizes[2];
target_ulong sram_size; target_ulong sram_size;
@ -227,18 +224,18 @@ static void ref405ep_init (ram_addr_t ram_size,
dinfo = drive_get(IF_PFLASH, 0, fl_idx); dinfo = drive_get(IF_PFLASH, 0, fl_idx);
if (dinfo) { if (dinfo) {
bios_size = bdrv_getlength(dinfo->bdrv); bios_size = bdrv_getlength(dinfo->bdrv);
memory_region_init_rom_device(bios, &pflash_cfi02_ops_be, bios_offset = qemu_ram_alloc(NULL, "ef405ep.bios", bios_size);
NULL, "ef405ep.bios", bios_size);
fl_sectors = (bios_size + 65535) >> 16; fl_sectors = (bios_size + 65535) >> 16;
#ifdef DEBUG_BOARD_INIT #ifdef DEBUG_BOARD_INIT
printf("Register parallel flash %d size %lx" printf("Register parallel flash %d size %lx"
" at addr %lx '%s' %d\n", " at offset %08lx addr %lx '%s' %d\n",
fl_idx, bios_size, -bios_size, fl_idx, bios_size, bios_offset, -bios_size,
bdrv_get_device_name(dinfo->bdrv), fl_sectors); bdrv_get_device_name(dinfo->bdrv), fl_sectors);
#endif #endif
pflash_cfi02_register((uint32_t)(-bios_size), bios, pflash_cfi02_register((uint32_t)(-bios_size), bios_offset,
dinfo->bdrv, 65536, fl_sectors, 1, dinfo->bdrv, 65536, fl_sectors, 1,
2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA); 2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
1);
fl_idx++; fl_idx++;
} else } else
#endif #endif
@ -246,12 +243,12 @@ static void ref405ep_init (ram_addr_t ram_size,
#ifdef DEBUG_BOARD_INIT #ifdef DEBUG_BOARD_INIT
printf("Load BIOS from file\n"); printf("Load BIOS from file\n");
#endif #endif
memory_region_init_ram(bios, NULL, "ef405ep.bios", BIOS_SIZE); bios_offset = qemu_ram_alloc(NULL, "ef405ep.bios", BIOS_SIZE);
if (bios_name == NULL) if (bios_name == NULL)
bios_name = BIOS_FILENAME; bios_name = BIOS_FILENAME;
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
if (filename) { if (filename) {
bios_size = load_image(filename, memory_region_get_ram_ptr(bios)); bios_size = load_image(filename, qemu_get_ram_ptr(bios_offset));
g_free(filename); g_free(filename);
} else { } else {
bios_size = -1; bios_size = -1;
@ -262,9 +259,8 @@ static void ref405ep_init (ram_addr_t ram_size,
exit(1); exit(1);
} }
bios_size = (bios_size + 0xfff) & ~0xfff; bios_size = (bios_size + 0xfff) & ~0xfff;
memory_region_set_readonly(bios, true); cpu_register_physical_memory((uint32_t)(-bios_size),
memory_region_add_subregion(address_space_mem, (uint32_t)(-bios_size), bios_size, bios_offset | IO_MEM_ROM);
bios);
} }
/* Register FPGA */ /* Register FPGA */
#ifdef DEBUG_BOARD_INIT #ifdef DEBUG_BOARD_INIT
@ -511,9 +507,7 @@ static void taihu_405ep_init(ram_addr_t ram_size,
{ {
char *filename; char *filename;
qemu_irq *pic; qemu_irq *pic;
MemoryRegion *address_space_mem = get_system_memory(); ram_addr_t bios_offset;
MemoryRegion *bios = g_new(MemoryRegion, 1);
MemoryRegion *flash = g_new(MemoryRegion, 1);
MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories)); MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories));
target_phys_addr_t ram_bases[2], ram_sizes[2]; target_phys_addr_t ram_bases[2], ram_sizes[2];
long bios_size; long bios_size;
@ -550,17 +544,17 @@ static void taihu_405ep_init(ram_addr_t ram_size,
/* XXX: should check that size is 2MB */ /* XXX: should check that size is 2MB */
// bios_size = 2 * 1024 * 1024; // bios_size = 2 * 1024 * 1024;
fl_sectors = (bios_size + 65535) >> 16; fl_sectors = (bios_size + 65535) >> 16;
memory_region_init_rom_device(bios, &pflash_cfi02_ops_be, bios_offset = qemu_ram_alloc(NULL, "taihu_405ep.bios", bios_size);
NULL, "taihu_405ep.bios", bios_size);
#ifdef DEBUG_BOARD_INIT #ifdef DEBUG_BOARD_INIT
printf("Register parallel flash %d size %lx" printf("Register parallel flash %d size %lx"
" at addr %lx '%s' %d\n", " at offset %08lx addr %lx '%s' %d\n",
fl_idx, bios_size, -bios_size, fl_idx, bios_size, bios_offset, -bios_size,
bdrv_get_device_name(dinfo->bdrv), fl_sectors); bdrv_get_device_name(dinfo->bdrv), fl_sectors);
#endif #endif
pflash_cfi02_register((uint32_t)(-bios_size), bios, pflash_cfi02_register((uint32_t)(-bios_size), bios_offset,
dinfo->bdrv, 65536, fl_sectors, 1, dinfo->bdrv, 65536, fl_sectors, 1,
4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA); 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
1);
fl_idx++; fl_idx++;
} else } else
#endif #endif
@ -570,10 +564,10 @@ static void taihu_405ep_init(ram_addr_t ram_size,
#endif #endif
if (bios_name == NULL) if (bios_name == NULL)
bios_name = BIOS_FILENAME; bios_name = BIOS_FILENAME;
memory_region_init_ram(bios, NULL, "taihu_405ep.bios", BIOS_SIZE); bios_offset = qemu_ram_alloc(NULL, "taihu_405ep.bios", BIOS_SIZE);
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
if (filename) { if (filename) {
bios_size = load_image(filename, memory_region_get_ram_ptr(bios)); bios_size = load_image(filename, qemu_get_ram_ptr(bios_offset));
g_free(filename); g_free(filename);
} else { } else {
bios_size = -1; bios_size = -1;
@ -584,9 +578,8 @@ static void taihu_405ep_init(ram_addr_t ram_size,
exit(1); exit(1);
} }
bios_size = (bios_size + 0xfff) & ~0xfff; bios_size = (bios_size + 0xfff) & ~0xfff;
memory_region_set_readonly(bios, true); cpu_register_physical_memory((uint32_t)(-bios_size),
memory_region_add_subregion(address_space_mem, bios_size, bios_offset | IO_MEM_ROM);
(uint32_t)(-bios_size), bios);
} }
/* Register Linux flash */ /* Register Linux flash */
dinfo = drive_get(IF_PFLASH, 0, fl_idx); dinfo = drive_get(IF_PFLASH, 0, fl_idx);
@ -597,15 +590,15 @@ static void taihu_405ep_init(ram_addr_t ram_size,
fl_sectors = (bios_size + 65535) >> 16; fl_sectors = (bios_size + 65535) >> 16;
#ifdef DEBUG_BOARD_INIT #ifdef DEBUG_BOARD_INIT
printf("Register parallel flash %d size %lx" printf("Register parallel flash %d size %lx"
" at addr " TARGET_FMT_lx " '%s'\n", " at offset %08lx addr " TARGET_FMT_lx " '%s'\n",
fl_idx, bios_size, (target_ulong)0xfc000000, fl_idx, bios_size, bios_offset, (target_ulong)0xfc000000,
bdrv_get_device_name(dinfo->bdrv)); bdrv_get_device_name(dinfo->bdrv));
#endif #endif
memory_region_init_rom_device(flash, &pflash_cfi02_ops_be, bios_offset = qemu_ram_alloc(NULL, "taihu_405ep.flash", bios_size);
NULL, "taihu_405ep.flash", bios_size); pflash_cfi02_register(0xfc000000, bios_offset,
pflash_cfi02_register(0xfc000000, flash,
dinfo->bdrv, 65536, fl_sectors, 1, dinfo->bdrv, 65536, fl_sectors, 1,
4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA); 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
1);
fl_idx++; fl_idx++;
} }
/* Register CLPD & LCD display */ /* Register CLPD & LCD display */

10
hw/ppc4xx_pci.c
View File

@ -368,12 +368,10 @@ PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4],
cpu_register_physical_memory(config_space + PCIC0_CFGADDR, 4, index); cpu_register_physical_memory(config_space + PCIC0_CFGADDR, 4, index);
/* CFGDATA */ /* CFGDATA */
memory_region_init_io(&controller->pci_state.data_mem, index = pci_host_data_register_mmio(&controller->pci_state, 1);
&pci_host_data_be_ops, if (index < 0)
&controller->pci_state, "pci-conf-data", 4); goto free;
memory_region_add_subregion(get_system_memory(), cpu_register_physical_memory(config_space + PCIC0_CFGDATA, 4, index);
config_space + PCIC0_CFGDATA,
&controller->pci_state.data_mem);
/* Internal registers */ /* Internal registers */
index = cpu_register_io_memory(pci_reg_read, pci_reg_write, controller, index = cpu_register_io_memory(pci_reg_read, pci_reg_write, controller,

21
hw/ppce500_pci.c
View File

@ -79,6 +79,8 @@ struct PPCE500PCIState {
uint32_t gasket_time; uint32_t gasket_time;
qemu_irq irq[4]; qemu_irq irq[4];
/* mmio maps */ /* mmio maps */
int cfgaddr;
int cfgdata;
int reg; int reg;
}; };
@ -266,18 +268,18 @@ static void e500_pci_map(SysBusDevice *dev, target_phys_addr_t base)
PCIHostState *h = FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev)); PCIHostState *h = FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev));
PPCE500PCIState *s = DO_UPCAST(PPCE500PCIState, pci_state, h); PPCE500PCIState *s = DO_UPCAST(PPCE500PCIState, pci_state, h);
sysbus_add_memory(dev, base + PCIE500_CFGADDR, &h->conf_mem); cpu_register_physical_memory(base + PCIE500_CFGADDR, 4, s->cfgaddr);
sysbus_add_memory(dev, base + PCIE500_CFGDATA, &h->data_mem); cpu_register_physical_memory(base + PCIE500_CFGDATA, 4, s->cfgdata);
cpu_register_physical_memory(base + PCIE500_REG_BASE, PCIE500_REG_SIZE, cpu_register_physical_memory(base + PCIE500_REG_BASE, PCIE500_REG_SIZE,
s->reg); s->reg);
} }
static void e500_pci_unmap(SysBusDevice *dev, target_phys_addr_t base) static void e500_pci_unmap(SysBusDevice *dev, target_phys_addr_t base)
{ {
PCIHostState *h = FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev)); cpu_register_physical_memory(base + PCIE500_CFGADDR, 4,
IO_MEM_UNASSIGNED);
sysbus_del_memory(dev, &h->conf_mem); cpu_register_physical_memory(base + PCIE500_CFGDATA, 4,
sysbus_del_memory(dev, &h->data_mem); IO_MEM_UNASSIGNED);
cpu_register_physical_memory(base + PCIE500_REG_BASE, PCIE500_REG_SIZE, cpu_register_physical_memory(base + PCIE500_REG_BASE, PCIE500_REG_SIZE,
IO_MEM_UNASSIGNED); IO_MEM_UNASSIGNED);
} }
@ -307,10 +309,9 @@ static int e500_pcihost_initfn(SysBusDevice *dev)
pci_create_simple(b, 0, "e500-host-bridge"); pci_create_simple(b, 0, "e500-host-bridge");
memory_region_init_io(&h->conf_mem, &pci_host_conf_be_ops, h, s->cfgaddr = pci_host_conf_register_mmio(&s->pci_state, DEVICE_BIG_ENDIAN);
"pci-conf-idx", 4); s->cfgdata = pci_host_data_register_mmio(&s->pci_state,
memory_region_init_io(&h->data_mem, &pci_host_data_le_ops, h, DEVICE_LITTLE_ENDIAN);
"pci-conf-data", 4);
s->reg = cpu_register_io_memory(e500_pci_reg_read, e500_pci_reg_write, s, s->reg = cpu_register_io_memory(e500_pci_reg_read, e500_pci_reg_write, s,
DEVICE_BIG_ENDIAN); DEVICE_BIG_ENDIAN);
sysbus_init_mmio_cb2(dev, e500_pci_map, e500_pci_unmap); sysbus_init_mmio_cb2(dev, e500_pci_map, e500_pci_unmap);

10
hw/prep_pci.c
View File

@ -125,15 +125,9 @@ PCIBus *pci_prep_init(qemu_irq *pic,
address_space_io, address_space_io,
0, 4); 0, 4);
memory_region_init_io(&s->conf_mem, &pci_host_conf_be_ops, s, pci_host_conf_register_ioport(0xcf8, s);
"pci-conf-idx", 1);
memory_region_add_subregion(address_space_io, 0xcf8, &s->conf_mem);
sysbus_init_ioports(&s->busdev, 0xcf8, 1);
memory_region_init_io(&s->conf_mem, &pci_host_data_be_ops, s, pci_host_data_register_ioport(0xcfc, s);
"pci-conf-data", 1);
memory_region_add_subregion(address_space_io, 0xcfc, &s->data_mem);
sysbus_init_ioports(&s->busdev, 0xcfc, 1);
PPC_io_memory = cpu_register_io_memory(PPC_PCIIO_read, PPC_io_memory = cpu_register_io_memory(PPC_PCIIO_read,
PPC_PCIIO_write, s, PPC_PCIIO_write, s,

7
hw/r2d.c
View File

@ -235,7 +235,6 @@ static void r2d_init(ram_addr_t ram_size,
qemu_irq *irq; qemu_irq *irq;
DriveInfo *dinfo; DriveInfo *dinfo;
int i; int i;
MemoryRegion *flash = g_new(MemoryRegion, 1);
if (!cpu_model) if (!cpu_model)
cpu_model = "SH7751R"; cpu_model = "SH7751R";
@ -268,13 +267,11 @@ static void r2d_init(ram_addr_t ram_size,
/* onboard flash memory */ /* onboard flash memory */
dinfo = drive_get(IF_PFLASH, 0, 0); dinfo = drive_get(IF_PFLASH, 0, 0);
memory_region_init_rom_device(flash, &pflash_cfi02_ops_le, pflash_cfi02_register(0x0, qemu_ram_alloc(NULL, "r2d.flash", FLASH_SIZE),
NULL, "r2d.flash", FLASH_SIZE);
pflash_cfi02_register(0x0, flash,
dinfo ? dinfo->bdrv : NULL, (16 * 1024), dinfo ? dinfo->bdrv : NULL, (16 * 1024),
FLASH_SIZE >> 16, FLASH_SIZE >> 16,
1, 4, 0x0000, 0x0000, 0x0000, 0x0000, 1, 4, 0x0000, 0x0000, 0x0000, 0x0000,
0x555, 0x2aa); 0x555, 0x2aa, 0);
/* NIC: rtl8139 on-board, and 2 slots. */ /* NIC: rtl8139 on-board, and 2 slots. */
for (i = 0; i < nb_nics; i++) for (i = 0; i < nb_nics; i++)

5
hw/stellaris.c
View File

@ -15,7 +15,6 @@
#include "i2c.h" #include "i2c.h"
#include "net.h" #include "net.h"
#include "boards.h" #include "boards.h"
#include "exec-memory.h"
#define GPIO_A 0 #define GPIO_A 0
#define GPIO_B 1 #define GPIO_B 1
@ -1261,7 +1260,6 @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model,
0x40024000, 0x40025000, 0x40026000}; 0x40024000, 0x40025000, 0x40026000};
static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31}; static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31};
MemoryRegion *address_space_mem = get_system_memory();
qemu_irq *pic; qemu_irq *pic;
DeviceState *gpio_dev[7]; DeviceState *gpio_dev[7];
qemu_irq gpio_in[7][8]; qemu_irq gpio_in[7][8];
@ -1276,8 +1274,7 @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model,
flash_size = ((board->dc0 & 0xffff) + 1) << 1; flash_size = ((board->dc0 & 0xffff) + 1) << 1;
sram_size = (board->dc0 >> 18) + 1; sram_size = (board->dc0 >> 18) + 1;
pic = armv7m_init(address_space_mem, pic = armv7m_init(flash_size, sram_size, kernel_filename, cpu_model);
flash_size, sram_size, kernel_filename, cpu_model);
if (board->dc1 & (1 << 16)) { if (board->dc1 & (1 << 16)) {
dev = sysbus_create_varargs("stellaris-adc", 0x40038000, dev = sysbus_create_varargs("stellaris-adc", 0x40038000,

29
hw/stellaris_enet.c
View File

@ -69,7 +69,7 @@ typedef struct {
NICState *nic; NICState *nic;
NICConf conf; NICConf conf;
qemu_irq irq; qemu_irq irq;
MemoryRegion mmio; int mmio_index;
} stellaris_enet_state; } stellaris_enet_state;
static void stellaris_enet_update(stellaris_enet_state *s) static void stellaris_enet_update(stellaris_enet_state *s)
@ -130,8 +130,7 @@ static int stellaris_enet_can_receive(VLANClientState *nc)
return (s->np < 31); return (s->np < 31);
} }
static uint64_t stellaris_enet_read(void *opaque, target_phys_addr_t offset, static uint32_t stellaris_enet_read(void *opaque, target_phys_addr_t offset)
unsigned size)
{ {
stellaris_enet_state *s = (stellaris_enet_state *)opaque; stellaris_enet_state *s = (stellaris_enet_state *)opaque;
uint32_t val; uint32_t val;
@ -199,7 +198,7 @@ static uint64_t stellaris_enet_read(void *opaque, target_phys_addr_t offset,
} }
static void stellaris_enet_write(void *opaque, target_phys_addr_t offset, static void stellaris_enet_write(void *opaque, target_phys_addr_t offset,
uint64_t value, unsigned size) uint32_t value)
{ {
stellaris_enet_state *s = (stellaris_enet_state *)opaque; stellaris_enet_state *s = (stellaris_enet_state *)opaque;
@ -304,12 +303,17 @@ static void stellaris_enet_write(void *opaque, target_phys_addr_t offset,
} }
} }
static const MemoryRegionOps stellaris_enet_ops = { static CPUReadMemoryFunc * const stellaris_enet_readfn[] = {
.read = stellaris_enet_read, stellaris_enet_read,
.write = stellaris_enet_write, stellaris_enet_read,
.endianness = DEVICE_NATIVE_ENDIAN, stellaris_enet_read
}; };
static CPUWriteMemoryFunc * const stellaris_enet_writefn[] = {
stellaris_enet_write,
stellaris_enet_write,
stellaris_enet_write
};
static void stellaris_enet_reset(stellaris_enet_state *s) static void stellaris_enet_reset(stellaris_enet_state *s)
{ {
s->mdv = 0x80; s->mdv = 0x80;
@ -387,7 +391,7 @@ static void stellaris_enet_cleanup(VLANClientState *nc)
unregister_savevm(&s->busdev.qdev, "stellaris_enet", s); unregister_savevm(&s->busdev.qdev, "stellaris_enet", s);
memory_region_destroy(&s->mmio); cpu_unregister_io_memory(s->mmio_index);
g_free(s); g_free(s);
} }
@ -404,9 +408,10 @@ static int stellaris_enet_init(SysBusDevice *dev)
{ {
stellaris_enet_state *s = FROM_SYSBUS(stellaris_enet_state, dev); stellaris_enet_state *s = FROM_SYSBUS(stellaris_enet_state, dev);
memory_region_init_io(&s->mmio, &stellaris_enet_ops, s, "stellaris_enet", s->mmio_index = cpu_register_io_memory(stellaris_enet_readfn,
0x1000); stellaris_enet_writefn, s,
sysbus_init_mmio_region(dev, &s->mmio); DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, s->mmio_index);
sysbus_init_irq(dev, &s->irq); sysbus_init_irq(dev, &s->irq);
qemu_macaddr_default_if_unset(&s->conf.macaddr); qemu_macaddr_default_if_unset(&s->conf.macaddr);

29
hw/sysbus.c
View File

@ -256,32 +256,3 @@ static char *sysbus_get_fw_dev_path(DeviceState *dev)
return strdup(path); return strdup(path);
} }
void sysbus_add_memory(SysBusDevice *dev, target_phys_addr_t addr,
MemoryRegion *mem)
{
memory_region_add_subregion(get_system_memory(), addr, mem);
}
void sysbus_add_memory_overlap(SysBusDevice *dev, target_phys_addr_t addr,
MemoryRegion *mem, unsigned priority)
{
memory_region_add_subregion_overlap(get_system_memory(), addr, mem,
priority);
}
void sysbus_del_memory(SysBusDevice *dev, MemoryRegion *mem)
{
memory_region_del_subregion(get_system_memory(), mem);
}
void sysbus_add_io(SysBusDevice *dev, target_phys_addr_t addr,
MemoryRegion *mem)
{
memory_region_add_subregion(get_system_io(), addr, mem);
}
void sysbus_del_io(SysBusDevice *dev, MemoryRegion *mem)
{
memory_region_del_subregion(get_system_io(), mem);
}

8
hw/sysbus.h
View File

@ -57,14 +57,6 @@ void sysbus_init_ioports(SysBusDevice *dev, pio_addr_t ioport, pio_addr_t size);
void sysbus_connect_irq(SysBusDevice *dev, int n, qemu_irq irq); void sysbus_connect_irq(SysBusDevice *dev, int n, qemu_irq irq);
void sysbus_mmio_map(SysBusDevice *dev, int n, target_phys_addr_t addr); void sysbus_mmio_map(SysBusDevice *dev, int n, target_phys_addr_t addr);
void sysbus_add_memory(SysBusDevice *dev, target_phys_addr_t addr,
MemoryRegion *mem);
void sysbus_add_memory_overlap(SysBusDevice *dev, target_phys_addr_t addr,
MemoryRegion *mem, unsigned priority);
void sysbus_del_memory(SysBusDevice *dev, MemoryRegion *mem);
void sysbus_add_io(SysBusDevice *dev, target_phys_addr_t addr,
MemoryRegion *mem);
void sysbus_del_io(SysBusDevice *dev, MemoryRegion *mem);
/* Legacy helper function for creating devices. */ /* Legacy helper function for creating devices. */
DeviceState *sysbus_create_varargs(const char *name, DeviceState *sysbus_create_varargs(const char *name,

82
hw/unin_pci.c
View File

@ -41,6 +41,7 @@ static const int unin_irq_line[] = { 0x1b, 0x1c, 0x1d, 0x1e };
typedef struct UNINState { typedef struct UNINState {
SysBusDevice busdev; SysBusDevice busdev;
PCIHostState host_state; PCIHostState host_state;
ReadWriteHandler data_handler;
} UNINState; } UNINState;
static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num) static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
@ -99,70 +100,67 @@ static uint32_t unin_get_config_reg(uint32_t reg, uint32_t addr)
return retval; return retval;
} }
static void unin_data_write(void *opaque, target_phys_addr_t addr, static void unin_data_write(ReadWriteHandler *handler,
uint64_t val, unsigned len) pcibus_t addr, uint32_t val, int len)
{ {
UNINState *s = opaque; UNINState *s = container_of(handler, UNINState, data_handler);
UNIN_DPRINTF("write addr %" TARGET_FMT_plx " len %d val %"PRIx64"\n", UNIN_DPRINTF("write addr %" FMT_PCIBUS " len %d val %x\n", addr, len, val);
addr, len, val);
pci_data_write(s->host_state.bus, pci_data_write(s->host_state.bus,
unin_get_config_reg(s->host_state.config_reg, addr), unin_get_config_reg(s->host_state.config_reg, addr),
val, len); val, len);
} }
static uint64_t unin_data_read(void *opaque, target_phys_addr_t addr, static uint32_t unin_data_read(ReadWriteHandler *handler,
unsigned len) pcibus_t addr, int len)
{ {
UNINState *s = opaque; UNINState *s = container_of(handler, UNINState, data_handler);
uint32_t val; uint32_t val;
val = pci_data_read(s->host_state.bus, val = pci_data_read(s->host_state.bus,
unin_get_config_reg(s->host_state.config_reg, addr), unin_get_config_reg(s->host_state.config_reg, addr),
len); len);
UNIN_DPRINTF("read addr %" TARGET_FMT_plx " len %d val %x\n", UNIN_DPRINTF("read addr %" FMT_PCIBUS " len %d val %x\n", addr, len, val);
addr, len, val);
return val; return val;
} }
static const MemoryRegionOps unin_data_ops = {
.read = unin_data_read,
.write = unin_data_write,
.endianness = DEVICE_LITTLE_ENDIAN,
};
static int pci_unin_main_init_device(SysBusDevice *dev) static int pci_unin_main_init_device(SysBusDevice *dev)
{ {
UNINState *s; UNINState *s;
int pci_mem_config, pci_mem_data;
/* Use values found on a real PowerMac */ /* Use values found on a real PowerMac */
/* Uninorth main bus */ /* Uninorth main bus */
s = FROM_SYSBUS(UNINState, dev); s = FROM_SYSBUS(UNINState, dev);
memory_region_init_io(&s->host_state.conf_mem, &pci_host_conf_le_ops, pci_mem_config = pci_host_conf_register_mmio(&s->host_state,
&s->host_state, "pci-conf-idx", 0x1000); DEVICE_LITTLE_ENDIAN);
memory_region_init_io(&s->host_state.data_mem, &unin_data_ops, s, s->data_handler.read = unin_data_read;
"pci-conf-data", 0x1000); s->data_handler.write = unin_data_write;
sysbus_init_mmio_region(dev, &s->host_state.conf_mem); pci_mem_data = cpu_register_io_memory_simple(&s->data_handler,
sysbus_init_mmio_region(dev, &s->host_state.data_mem); DEVICE_LITTLE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, pci_mem_config);
sysbus_init_mmio(dev, 0x1000, pci_mem_data);
qemu_register_reset(pci_unin_reset, &s->host_state); qemu_register_reset(pci_unin_reset, &s->host_state);
return 0; return 0;
} }
static int pci_u3_agp_init_device(SysBusDevice *dev) static int pci_u3_agp_init_device(SysBusDevice *dev)
{ {
UNINState *s; UNINState *s;
int pci_mem_config, pci_mem_data;
/* Uninorth U3 AGP bus */ /* Uninorth U3 AGP bus */
s = FROM_SYSBUS(UNINState, dev); s = FROM_SYSBUS(UNINState, dev);
memory_region_init_io(&s->host_state.conf_mem, &pci_host_conf_le_ops, pci_mem_config = pci_host_conf_register_mmio(&s->host_state,
&s->host_state, "pci-conf-idx", 0x1000); DEVICE_LITTLE_ENDIAN);
memory_region_init_io(&s->host_state.data_mem, &unin_data_ops, s, s->data_handler.read = unin_data_read;
"pci-conf-data", 0x1000); s->data_handler.write = unin_data_write;
sysbus_init_mmio_region(dev, &s->host_state.conf_mem); pci_mem_data = cpu_register_io_memory_simple(&s->data_handler,
sysbus_init_mmio_region(dev, &s->host_state.data_mem); DEVICE_LITTLE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, pci_mem_config);
sysbus_init_mmio(dev, 0x1000, pci_mem_data);
qemu_register_reset(pci_unin_reset, &s->host_state); qemu_register_reset(pci_unin_reset, &s->host_state);
@ -172,32 +170,34 @@ static int pci_u3_agp_init_device(SysBusDevice *dev)
static int pci_unin_agp_init_device(SysBusDevice *dev) static int pci_unin_agp_init_device(SysBusDevice *dev)
{ {
UNINState *s; UNINState *s;
int pci_mem_config, pci_mem_data;
/* Uninorth AGP bus */ /* Uninorth AGP bus */
s = FROM_SYSBUS(UNINState, dev); s = FROM_SYSBUS(UNINState, dev);
memory_region_init_io(&s->host_state.conf_mem, &pci_host_conf_le_ops, pci_mem_config = pci_host_conf_register_mmio(&s->host_state,
&s->host_state, "pci-conf-idx", 0x1000); DEVICE_LITTLE_ENDIAN);
memory_region_init_io(&s->host_state.data_mem, &pci_host_data_le_ops, pci_mem_data = pci_host_data_register_mmio(&s->host_state,
&s->host_state, "pci-conf-data", 0x1000); DEVICE_LITTLE_ENDIAN);
sysbus_init_mmio_region(dev, &s->host_state.conf_mem); sysbus_init_mmio(dev, 0x1000, pci_mem_config);
sysbus_init_mmio_region(dev, &s->host_state.data_mem); sysbus_init_mmio(dev, 0x1000, pci_mem_data);
return 0; return 0;
} }
static int pci_unin_internal_init_device(SysBusDevice *dev) static int pci_unin_internal_init_device(SysBusDevice *dev)
{ {
UNINState *s; UNINState *s;
int pci_mem_config, pci_mem_data;
/* Uninorth internal bus */ /* Uninorth internal bus */
s = FROM_SYSBUS(UNINState, dev); s = FROM_SYSBUS(UNINState, dev);
memory_region_init_io(&s->host_state.conf_mem, &pci_host_conf_le_ops, pci_mem_config = pci_host_conf_register_mmio(&s->host_state,
&s->host_state, "pci-conf-idx", 0x1000); DEVICE_LITTLE_ENDIAN);
memory_region_init_io(&s->host_state.data_mem, &pci_host_data_le_ops, pci_mem_data = pci_host_data_register_mmio(&s->host_state,
&s->host_state, "pci-conf-data", 0x1000); DEVICE_LITTLE_ENDIAN);
sysbus_init_mmio_region(dev, &s->host_state.conf_mem); sysbus_init_mmio(dev, 0x1000, pci_mem_config);
sysbus_init_mmio_region(dev, &s->host_state.data_mem); sysbus_init_mmio(dev, 0x1000, pci_mem_data);
return 0; return 0;
} }

7
hw/virtex_ml507.c
View File

@ -196,7 +196,7 @@ static void virtex_init(ram_addr_t ram_size,
target_phys_addr_t ram_base = 0; target_phys_addr_t ram_base = 0;
DriveInfo *dinfo; DriveInfo *dinfo;
ram_addr_t phys_ram; ram_addr_t phys_ram;
MemoryRegion *phys_flash = g_new(MemoryRegion, 1); ram_addr_t phys_flash;
qemu_irq irq[32], *cpu_irq; qemu_irq irq[32], *cpu_irq;
clk_setup_t clk_setup[7]; clk_setup_t clk_setup[7];
int kernel_size; int kernel_size;
@ -215,13 +215,12 @@ static void virtex_init(ram_addr_t ram_size,
phys_ram = qemu_ram_alloc(NULL, "ram", ram_size); phys_ram = qemu_ram_alloc(NULL, "ram", ram_size);
cpu_register_physical_memory(ram_base, ram_size, phys_ram | IO_MEM_RAM); cpu_register_physical_memory(ram_base, ram_size, phys_ram | IO_MEM_RAM);
memory_region_init_rom_device(phys_flash, &pflash_cfi01_ops_be, phys_flash = qemu_ram_alloc(NULL, "virtex.flash", FLASH_SIZE);
NULL, "virtex.flash", FLASH_SIZE);
dinfo = drive_get(IF_PFLASH, 0, 0); dinfo = drive_get(IF_PFLASH, 0, 0);
pflash_cfi01_register(0xfc000000, phys_flash, pflash_cfi01_register(0xfc000000, phys_flash,
dinfo ? dinfo->bdrv : NULL, (64 * 1024), dinfo ? dinfo->bdrv : NULL, (64 * 1024),
FLASH_SIZE >> 16, FLASH_SIZE >> 16,
1, 0x89, 0x18, 0x0000, 0x0); 1, 0x89, 0x18, 0x0000, 0x0, 1);
cpu_irq = (qemu_irq *) &env->irq_inputs[PPC40x_INPUT_INT]; cpu_irq = (qemu_irq *) &env->irq_inputs[PPC40x_INPUT_INT];
dev = xilinx_intc_create(0x81800000, cpu_irq[0], 0); dev = xilinx_intc_create(0x81800000, cpu_irq[0], 0);

15
hw/z2.c
View File

@ -280,11 +280,10 @@ static void z2_init(ram_addr_t ram_size,
uint32_t sector_len = 0x10000; uint32_t sector_len = 0x10000;
PXA2xxState *cpu; PXA2xxState *cpu;
DriveInfo *dinfo; DriveInfo *dinfo;
const MemoryRegionOps *flash_ops; int be;
void *z2_lcd; void *z2_lcd;
i2c_bus *bus; i2c_bus *bus;
DeviceState *wm; DeviceState *wm;
MemoryRegion *flash = g_new(MemoryRegion, 1);
if (!cpu_model) { if (!cpu_model) {
cpu_model = "pxa270-c5"; cpu_model = "pxa270-c5";
@ -294,9 +293,9 @@ static void z2_init(ram_addr_t ram_size,
cpu = pxa270_init(z2_binfo.ram_size, cpu_model); cpu = pxa270_init(z2_binfo.ram_size, cpu_model);
#ifdef TARGET_WORDS_BIGENDIAN #ifdef TARGET_WORDS_BIGENDIAN
flash_ops = &pflash_cfi01_ops_be; be = 1;
#else #else
flash_ops = &pflash_cfi01_ops_le; be = 0;
#endif #endif
dinfo = drive_get(IF_PFLASH, 0, 0); dinfo = drive_get(IF_PFLASH, 0, 0);
if (!dinfo) { if (!dinfo) {
@ -305,11 +304,11 @@ static void z2_init(ram_addr_t ram_size,
exit(1); exit(1);
} }
memory_region_init_rom_device(flash, flash_ops, if (!pflash_cfi01_register(Z2_FLASH_BASE,
NULL, "z2.flash0", Z2_FLASH_SIZE); qemu_ram_alloc(NULL, "z2.flash0", Z2_FLASH_SIZE),
if (!pflash_cfi01_register(Z2_FLASH_BASE, flash,
dinfo->bdrv, sector_len, dinfo->bdrv, sector_len,
Z2_FLASH_SIZE / sector_len, 4, 0, 0, 0, 0)) { Z2_FLASH_SIZE / sector_len, 4, 0, 0, 0, 0,
be)) {
fprintf(stderr, "qemu: Error registering flash memory.\n"); fprintf(stderr, "qemu: Error registering flash memory.\n");
exit(1); exit(1);
} }

87
rwhandler.c Normal file
View File

@ -0,0 +1,87 @@
#include "rwhandler.h"
#include "ioport.h"
#include "cpu-all.h"
#define RWHANDLER_WRITE(name, len, type) \
static void name(void *opaque, type addr, uint32_t value) \
{\
struct ReadWriteHandler *handler = opaque;\
handler->write(handler, addr, value, len);\
}
#define RWHANDLER_READ(name, len, type) \
static uint32_t name(void *opaque, type addr) \
{ \
struct ReadWriteHandler *handler = opaque; \
return handler->read(handler, addr, len); \
}
RWHANDLER_WRITE(cpu_io_memory_simple_writeb, 1, target_phys_addr_t);
RWHANDLER_READ(cpu_io_memory_simple_readb, 1, target_phys_addr_t);
RWHANDLER_WRITE(cpu_io_memory_simple_writew, 2, target_phys_addr_t);
RWHANDLER_READ(cpu_io_memory_simple_readw, 2, target_phys_addr_t);
RWHANDLER_WRITE(cpu_io_memory_simple_writel, 4, target_phys_addr_t);
RWHANDLER_READ(cpu_io_memory_simple_readl, 4, target_phys_addr_t);
static CPUWriteMemoryFunc * const cpu_io_memory_simple_write[] = {
&cpu_io_memory_simple_writeb,
&cpu_io_memory_simple_writew,
&cpu_io_memory_simple_writel,
};
static CPUReadMemoryFunc * const cpu_io_memory_simple_read[] = {
&cpu_io_memory_simple_readb,
&cpu_io_memory_simple_readw,
&cpu_io_memory_simple_readl,
};
int cpu_register_io_memory_simple(struct ReadWriteHandler *handler, int endian)
{
if (!handler->read || !handler->write) {
return -1;
}
return cpu_register_io_memory(cpu_io_memory_simple_read,
cpu_io_memory_simple_write,
handler, endian);
}
RWHANDLER_WRITE(ioport_simple_writeb, 1, uint32_t);
RWHANDLER_READ(ioport_simple_readb, 1, uint32_t);
RWHANDLER_WRITE(ioport_simple_writew, 2, uint32_t);
RWHANDLER_READ(ioport_simple_readw, 2, uint32_t);
RWHANDLER_WRITE(ioport_simple_writel, 4, uint32_t);
RWHANDLER_READ(ioport_simple_readl, 4, uint32_t);
int register_ioport_simple(ReadWriteHandler* handler,
pio_addr_t start, int length, int size)
{
IOPortWriteFunc *write;
IOPortReadFunc *read;
int r;
switch (size) {
case 1:
write = ioport_simple_writeb;
read = ioport_simple_readb;
break;
case 2:
write = ioport_simple_writew;
read = ioport_simple_readw;
break;
default:
write = ioport_simple_writel;
read = ioport_simple_readl;
}
if (handler->write) {
r = register_ioport_write(start, length, size, write, handler);
if (r < 0) {
return r;
}
}
if (handler->read) {
r = register_ioport_read(start, length, size, read, handler);
if (r < 0) {
return r;
}
}
return 0;
}

27
rwhandler.h Normal file
View File

@ -0,0 +1,27 @@
#ifndef READ_WRITE_HANDLER_H
#define READ_WRITE_HANDLER_H
#include "qemu-common.h"
#include "ioport.h"
typedef struct ReadWriteHandler ReadWriteHandler;
/* len is guaranteed to be one of 1, 2 or 4, addr is guaranteed to fit in an
* appropriate type (io/memory/etc). They do not need to be range checked. */
typedef void WriteHandlerFunc(ReadWriteHandler *, pcibus_t addr,
uint32_t value, int len);
typedef uint32_t ReadHandlerFunc(ReadWriteHandler *, pcibus_t addr, int len);
struct ReadWriteHandler {
WriteHandlerFunc *write;
ReadHandlerFunc *read;
};
/* Helpers for when we want to use a single routine with length. */
/* CPU memory handler: both read and write must be present. */
int cpu_register_io_memory_simple(ReadWriteHandler *, int endian);
/* io port handler: can supply only read or write handlers. */
int register_ioport_simple(ReadWriteHandler *,
pio_addr_t start, int length, int size);
#endif