122 lines
2.2 KiB
Coq
122 lines
2.2 KiB
Coq
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/*
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* sig_delay.c
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*
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* Signal delay line - runtime configurable length
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*
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* Copyright (C) 2018 sysmocom - systems for mobile communications GmbH
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*
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* vim: ts=4 sw=4
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*/
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`ifdef SIM
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`default_nettype none
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`endif
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module sig_delay #(
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parameter integer WIDTH = 12
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)(
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input wire data_valid,
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input wire [WIDTH-1:0] data_in,
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output wire [WIDTH-1:0] data_out,
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input wire [14:0] delay,
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input wire clk,
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input wire rst
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);
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// Signals
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// -------
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reg [14:0] wr_addr;
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reg [14:0] rd_addr;
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wire ce;
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// Control
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// -------
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assign ce = data_valid;
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always @(posedge clk)
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begin
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if (rst) begin
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wr_addr <= 0;
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rd_addr <= 0;
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end else if (ce) begin
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wr_addr <= wr_addr + 1;
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rd_addr <= wr_addr - delay;
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end
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end
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// Storage
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// -------
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genvar i;
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generate
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for (i=0; i<WIDTH; i=i+1)
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begin
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// Signals
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wire [31:0] ram_do;
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wire [31:0] ram_di;
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// Connections
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assign data_out[i] = ram_do[0];
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assign ram_di = { 31'd0, data_in[i] };
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// Instantiate RAM Block
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RAMB36E1 #(
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.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
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.SIM_COLLISION_CHECK("NONE"),
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.DOA_REG(1),
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.DOB_REG(1),
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.EN_ECC_READ("FALSE"),
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.EN_ECC_WRITE("FALSE"),
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.RAM_EXTENSION_A("NONE"),
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.RAM_EXTENSION_B("NONE"),
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.RAM_MODE("TDP"),
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.READ_WIDTH_A(1),
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.READ_WIDTH_B(1),
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.WRITE_WIDTH_A(1),
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.WRITE_WIDTH_B(1),
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.RSTREG_PRIORITY_A("RSTREG"),
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.RSTREG_PRIORITY_B("RSTREG"),
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.SIM_DEVICE("7SERIES"),
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.SRVAL_A(36'h000000000),
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.SRVAL_B(36'h000000000),
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.WRITE_MODE_A("READ_FIRST"),
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.WRITE_MODE_B("READ_FIRST")
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)
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mem_elem_I (
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.DOADO(ram_do),
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.DOPADOP(),
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.DOBDO(),
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.DOPBDOP(),
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.CASCADEINA(1'b0),
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.CASCADEINB(1'b0),
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.INJECTDBITERR(1'b0),
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.INJECTSBITERR(1'b0),
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.ADDRARDADDR({1'b1, rd_addr}),
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.CLKARDCLK(clk),
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.ENARDEN(ce),
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.REGCEAREGCE(ce),
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.RSTRAMARSTRAM(rst),
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.RSTREGARSTREG(rst),
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.WEA(4'd0),
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.DIADI(32'd0),
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.DIPADIP(4'd0),
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.ADDRBWRADDR({1'b1, wr_addr}),
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.CLKBWRCLK(clk),
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.ENBWREN(1'b1),
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.REGCEB(1'b0),
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.RSTRAMB(rst),
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.RSTREGB(rst),
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.WEBWE({7'd0, ce}),
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.DIBDI(ram_di),
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.DIPBDIP(4'd0)
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);
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end
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endgenerate
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endmodule // sig_delay
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