gw: Import the gateware (RTL & Sim)

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
master
Sylvain Munaut 4 years ago
parent c3485e9119
commit 18adc3602a
  1. 23
      gw/Makefile
  2. 80
      gw/sig_chain_tb.v
  3. 122
      gw/sig_combine.v
  4. 121
      gw/sig_delay.v
  5. 1550
      gw/xilinx/DSP48E1.v
  6. 4752
      gw/xilinx/RAMB36E1.v
  7. 66
      gw/xilinx/glbl.v

@ -0,0 +1,23 @@
#
# Simulation Makefile
#
XILINX_LIBS=\
xilinx/glbl.v \
xilinx/DSP48E1.v \
xilinx/RAMB36E1.v
OBJS=\
sig_combine.v \
sig_delay.v
TESTBENCHES=\
sig_chain_tb
all: $(TESTBENCHES)
%_tb: %_tb.v $(XILINX_LIBS) $(OBJS)
iverilog -Wall -DSIM=1 -o $@ $(XILINX_LIBS) $(OBJS) $<
clean:
rm -f $(TESTBENCHES) *.vcd

@ -0,0 +1,80 @@
/*
* sig_chain_tb.v
*
* Copyright (C) 2018 sysmocom - systems for mobile communications GmbH
*
* vim: ts=4 sw=4
*/
`default_nettype none
`timescale 1ns/1ps
module sig_chain_tb;
// Signals
reg rst = 1;
reg clk = 0;
reg data_valid;
reg [11:0] data_in;
wire [11:0] data_out;
wire [11:0] data_comb_3;
wire [14:0] cfg_delay;
// Setup recording
initial begin
$dumpfile("sig_chain_tb.vcd");
$dumpvars(0,sig_chain_tb);
end
// Reset pulse
initial begin
# 21 rst = 0;
# 50000 $finish;
end
// Clock
always #5 clk = !clk;
// DUT
sig_delay #(
.WIDTH(12)
) dut_A_I (
.data_valid(data_valid),
.data_in(data_in),
.data_out(data_out),
.delay(cfg_delay),
.clk(clk),
.rst(rst)
);
sig_combine #(
.D_WIDTH(12),
.S_WIDTH(16),
.S_FRAC(14)
) dut_B_I (
.in_data_0(data_out),
.in_scale_0(16'h2000), // 0.5
.in_chain_0(data_in),
.out_3(data_comb_3),
.clk(clk),
.rst(rst)
);
// Data gen
always @(posedge clk)
if (rst)
data_in <= 0;
else if (data_valid)
data_in <= data_in + 1;
always @(posedge clk)
if (rst)
data_valid <= 1'b0;
else
data_valid <= ($random & 3) == 0;
// Config
assign cfg_delay = 14'h00;
endmodule // sig_chain_tb

@ -0,0 +1,122 @@
/*
* sig_combine.v
*
* Simple signal combiner using DSP48E
*
* Copyright (C) 2018 sysmocom - systems for mobile communications GmbH
*
* vim: ts=4 sw=4
*/
`ifdef SIM
`default_nettype none
`endif
module sig_combine #(
parameter integer D_WIDTH = 12,
parameter integer S_WIDTH = 16,
parameter integer S_FRAC = 14
)(
// Input
input wire [D_WIDTH-1:0] in_data_0,
input wire [S_WIDTH-1:0] in_scale_0,
input wire [D_WIDTH-1:0] in_chain_0,
// Output
output wire [D_WIDTH-1:0] out_3,
// Control
input wire clk,
input wire rst
);
localparam S = 25 - D_WIDTH + S_FRAC;
// Signals
reg [17:0] in_chain_1;
wire [47:0] pout_3;
wire [29:0] a_0;
wire [17:0] b_0;
wire [47:0] c_1;
// Align C
always @(posedge clk)
in_chain_1 <= in_chain_0;
// Map in/out
assign a_0 = { 5'd0, in_data_0, { (25-D_WIDTH){1'b0} } };
assign b_0 = { { (18-S_WIDTH){1'b0} }, in_scale_0 };
assign c_1 = { { (48-S-D_WIDTH){in_chain_1[D_WIDTH-1]} }, in_chain_1, { (S){1'b0} } };
assign out_3 = pout_3[S+:D_WIDTH];
// DSP
DSP48E1 #(
.A_INPUT("DIRECT"),
.B_INPUT("DIRECT"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.AUTORESET_PATDET("NO_RESET"),
.MASK(48'h3fffffffffff),
.PATTERN(48'h000000000000),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_PATTERN_DETECT("PATDET"),
.ACASCREG(1),
.ADREG(1),
.ALUMODEREG(1),
.AREG(1),
.BCASCREG(1),
.BREG(1),
.CARRYINREG(1),
.CARRYINSELREG(1),
.CREG(1),
.DREG(1),
.INMODEREG(1),
.MREG(1),
.OPMODEREG(1),
.PREG(1),
.USE_SIMD("ONE48")
) dsp_I (
.P(pout_3),
.ACIN(30'h0),
.BCIN(18'h0),
.CARRYCASCIN(1'h0),
.MULTSIGNIN(1'h0),
.PCIN(48'h000000000000),
.ALUMODE(4'b0000), // Z + X + Y + CIN
.CARRYINSEL(3'h0),
.CEINMODE(1'b1),
.CLK(clk),
.INMODE(5'b00000), // B=B2, A=A2
.OPMODE(7'b0110101), // X=M1, Y=M2, Z=C
.RSTINMODE(rst),
.A(a_0),
.B(b_0),
.C(c_1),
.CARRYIN(1'b0),
.D(25'd0),
.CEA1(1'b0),
.CEA2(1'b1),
.CEAD(1'b1),
.CEALUMODE(1'b1),
.CEB1(1'b0),
.CEB2(1'b1),
.CEC(1'b1),
.CECARRYIN(1'b1),
.CECTRL(1'b1),
.CED(1'b1),
.CEM(1'b1),
.CEP(1'b1),
.RSTA(rst),
.RSTALLCARRYIN(rst),
.RSTALUMODE(rst),
.RSTB(rst),
.RSTC(rst),
.RSTCTRL(rst),
.RSTD(rst),
.RSTM(rst),
.RSTP(rst)
);
endmodule // sig_combine

@ -0,0 +1,121 @@
/*
* sig_delay.c
*
* Signal delay line - runtime configurable length
*
* Copyright (C) 2018 sysmocom - systems for mobile communications GmbH
*
* vim: ts=4 sw=4
*/
`ifdef SIM
`default_nettype none
`endif
module sig_delay #(
parameter integer WIDTH = 12
)(
input wire data_valid,
input wire [WIDTH-1:0] data_in,
output wire [WIDTH-1:0] data_out,
input wire [14:0] delay,
input wire clk,
input wire rst
);
// Signals
// -------
reg [14:0] wr_addr;
reg [14:0] rd_addr;
wire ce;
// Control
// -------
assign ce = data_valid;
always @(posedge clk)
begin
if (rst) begin
wr_addr <= 0;
rd_addr <= 0;
end else if (ce) begin
wr_addr <= wr_addr + 1;
rd_addr <= wr_addr - delay;
end
end
// Storage
// -------
genvar i;
generate
for (i=0; i<WIDTH; i=i+1)
begin
// Signals
wire [31:0] ram_do;
wire [31:0] ram_di;
// Connections
assign data_out[i] = ram_do[0];
assign ram_di = { 31'd0, data_in[i] };
// Instantiate RAM Block
RAMB36E1 #(
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.SIM_COLLISION_CHECK("NONE"),
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.READ_WIDTH_A(1),
.READ_WIDTH_B(1),
.WRITE_WIDTH_A(1),
.WRITE_WIDTH_B(1),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST")
)
mem_elem_I (
.DOADO(ram_do),
.DOPADOP(),
.DOBDO(),
.DOPBDOP(),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.ADDRARDADDR({1'b1, rd_addr}),
.CLKARDCLK(clk),
.ENARDEN(ce),
.REGCEAREGCE(ce),
.RSTRAMARSTRAM(rst),
.RSTREGARSTREG(rst),
.WEA(4'd0),
.DIADI(32'd0),
.DIPADIP(4'd0),
.ADDRBWRADDR({1'b1, wr_addr}),
.CLKBWRCLK(clk),
.ENBWREN(1'b1),
.REGCEB(1'b0),
.RSTRAMB(rst),
.RSTREGB(rst),
.WEBWE({7'd0, ce}),
.DIBDI(ram_di),
.DIPBDIP(4'd0)
);
end
endgenerate
endmodule // sig_delay

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

@ -0,0 +1,66 @@
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.15 2011/08/25 22:54:30 fphillip Exp $
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
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