mirror of https://gerrit.osmocom.org/libusrp
101 lines
3.7 KiB
Verilog
101 lines
3.7 KiB
Verilog
// -*- verilog -*-
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//
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// USRP - Universal Software Radio Peripheral
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//
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// Copyright (C) 2003 Matt Ettus
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//
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// This program is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation; either version 2 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
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//
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// NOTE This only works for N=4, max decim rate of 128
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// NOTE signal "rate" is ONE LESS THAN the actual rate
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module cic_dec_shifter(rate,signal_in,signal_out);
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parameter bw = 16;
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parameter maxbitgain = 28;
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input [7:0] rate;
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input wire [bw+maxbitgain-1:0] signal_in;
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output reg [bw-1:0] signal_out;
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function [4:0] bitgain;
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input [7:0] rate;
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case(rate)
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// Exact Cases -- N*log2(rate)
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8'd4 : bitgain = 8;
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8'd8 : bitgain = 12;
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8'd16 : bitgain = 16;
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8'd32 : bitgain = 20;
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8'd64 : bitgain = 24;
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8'd128 : bitgain = 28;
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// Nearest without overflow -- ceil(N*log2(rate))
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8'd5 : bitgain = 10;
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8'd6 : bitgain = 11;
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8'd7 : bitgain = 12;
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8'd9 : bitgain = 13;
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8'd10,8'd11 : bitgain = 14;
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8'd12,8'd13 : bitgain = 15;
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8'd14,8'd15 : bitgain = 16;
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8'd17,8'd18,8'd19 : bitgain = 17;
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8'd20,8'd21,8'd22 : bitgain = 18;
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8'd23,8'd24,8'd25,8'd26 : bitgain = 19;
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8'd27,8'd28,8'd29,8'd30,8'd31 : bitgain = 20;
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8'd33,8'd34,8'd35,8'd36,8'd37,8'd38 : bitgain = 21;
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8'd39,8'd40,8'd41,8'd42,8'd43,8'd44,8'd45 : bitgain = 22;
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8'd46,8'd47,8'd48,8'd49,8'd50,8'd51,8'd52,8'd53 : bitgain = 23;
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8'd54,8'd55,8'd56,8'd57,8'd58,8'd59,8'd60,8'd61,8'd62,8'd63 : bitgain = 24;
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8'd65,8'd66,8'd67,8'd68,8'd69,8'd70,8'd71,8'd72,8'd73,8'd74,8'd75,8'd76 : bitgain = 25;
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8'd77,8'd78,8'd79,8'd80,8'd81,8'd82,8'd83,8'd84,8'd85,8'd86,8'd87,8'd88,8'd89,8'd90 : bitgain = 26;
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8'd91,8'd92,8'd93,8'd94,8'd95,8'd96,8'd97,8'd98,8'd99,8'd100,8'd101,8'd102,8'd103,8'd104,8'd105,8'd106,8'd107 : bitgain = 27;
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default : bitgain = 28;
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endcase // case(rate)
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endfunction // bitgain
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wire [4:0] shift = bitgain(rate+1);
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// We should be able to do this, but can't ....
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// assign signal_out = signal_in[shift+bw-1:shift];
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always @*
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case(shift)
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5'd8 : signal_out = signal_in[8+bw-1:8];
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5'd10 : signal_out = signal_in[10+bw-1:10];
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5'd11 : signal_out = signal_in[11+bw-1:11];
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5'd12 : signal_out = signal_in[12+bw-1:12];
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5'd13 : signal_out = signal_in[13+bw-1:13];
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5'd14 : signal_out = signal_in[14+bw-1:14];
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5'd15 : signal_out = signal_in[15+bw-1:15];
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5'd16 : signal_out = signal_in[16+bw-1:16];
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5'd17 : signal_out = signal_in[17+bw-1:17];
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5'd18 : signal_out = signal_in[18+bw-1:18];
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5'd19 : signal_out = signal_in[19+bw-1:19];
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5'd20 : signal_out = signal_in[20+bw-1:20];
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5'd21 : signal_out = signal_in[21+bw-1:21];
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5'd22 : signal_out = signal_in[22+bw-1:22];
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5'd23 : signal_out = signal_in[23+bw-1:23];
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5'd24 : signal_out = signal_in[24+bw-1:24];
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5'd25 : signal_out = signal_in[25+bw-1:25];
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5'd26 : signal_out = signal_in[26+bw-1:26];
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5'd27 : signal_out = signal_in[27+bw-1:27];
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5'd28 : signal_out = signal_in[28+bw-1:28];
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default : signal_out = signal_in[28+bw-1:28];
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endcase // case(shift)
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endmodule // cic_dec_shifter
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