mirror of https://gerrit.osmocom.org/libusrp
84 lines
2.0 KiB
Verilog
84 lines
2.0 KiB
Verilog
// -*- verilog -*-
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//
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// USRP - Universal Software Radio Peripheral
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//
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// Copyright (C) 2007 Corgan Enterprises LLC
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//
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// This program is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation; either version 2 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
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//
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module atr_delay(clk_i,rst_i,ena_i,tx_empty_i,tx_delay_i,rx_delay_i,atr_tx_o);
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input clk_i;
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input rst_i;
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input ena_i;
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input tx_empty_i;
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input [11:0] tx_delay_i;
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input [11:0] rx_delay_i;
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output atr_tx_o;
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reg [3:0] state;
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reg [11:0] count;
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`define ST_RX_DELAY 4'b0001
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`define ST_RX 4'b0010
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`define ST_TX_DELAY 4'b0100
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`define ST_TX 4'b1000
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always @(posedge clk_i)
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if (rst_i | ~ena_i)
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begin
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state <= `ST_RX;
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count <= 12'b0;
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end
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else
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case (state)
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`ST_RX:
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if (!tx_empty_i)
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begin
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state <= `ST_TX_DELAY;
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count <= tx_delay_i;
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end
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`ST_TX_DELAY:
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if (count == 0)
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state <= `ST_TX;
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else
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count <= count - 1;
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`ST_TX:
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if (tx_empty_i)
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begin
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state <= `ST_RX_DELAY;
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count <= rx_delay_i;
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end
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`ST_RX_DELAY:
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if (count == 0)
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state <= `ST_RX;
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else
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count <= count - 1;
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default: // Error
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begin
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state <= `ST_RX;
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count <= 0;
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end
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endcase
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assign atr_tx_o = (state == `ST_TX) | (state == `ST_RX_DELAY);
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endmodule // atr_delay
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