mirror of https://gerrit.osmocom.org/libusrp
25 lines
499 B
Verilog
25 lines
499 B
Verilog
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module fifo_1k
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( input [15:0] data,
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input wrreq,
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input rdreq,
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input rdclk,
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input wrclk,
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input aclr,
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output [15:0] q,
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output rdfull,
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output rdempty,
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output [9:0] rdusedw,
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output wrfull,
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output wrempty,
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output [9:0] wrusedw
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);
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fifo #(.width(16),.depth(1024),.addr_bits(10)) fifo_1k
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( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
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rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
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endmodule // fifo_1k
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