mirror of https://gerrit.osmocom.org/libusrp
77 lines
1.4 KiB
Verilog
77 lines
1.4 KiB
Verilog
// Model of FIFO in Altera
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module fifo_1c_4k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
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rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
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parameter width = 32;
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parameter depth = 4096;
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//`define rd_req 0; // Set this to 0 for rd_ack, 1 for rd_req
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input [31:0] data;
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input wrreq;
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input rdreq;
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input rdclk;
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input wrclk;
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input aclr;
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output [31:0] q;
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output rdfull;
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output rdempty;
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output [7:0] rdusedw;
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output wrfull;
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output wrempty;
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output [7:0] wrusedw;
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reg [width-1:0] mem [0:depth-1];
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reg [7:0] rdptr;
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reg [7:0] wrptr;
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`ifdef rd_req
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reg [width-1:0] q;
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`else
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wire [width-1:0] q;
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`endif
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reg [7:0] rdusedw;
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reg [7:0] wrusedw;
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integer i;
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always @( aclr)
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begin
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wrptr <= #1 0;
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rdptr <= #1 0;
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for(i=0;i<depth;i=i+1)
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mem[i] <= #1 0;
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end
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always @(posedge wrclk)
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if(wrreq)
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begin
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wrptr <= #1 wrptr+1;
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mem[wrptr] <= #1 data;
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end
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always @(posedge rdclk)
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if(rdreq)
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begin
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rdptr <= #1 rdptr+1;
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`ifdef rd_req
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q <= #1 mem[rdptr];
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`endif
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end
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`ifdef rd_req
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`else
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assign q = mem[rdptr];
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`endif
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// Fix these
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always @(posedge wrclk)
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wrusedw <= #1 wrptr - rdptr;
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always @(posedge rdclk)
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rdusedw <= #1 wrptr - rdptr;
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endmodule // fifo_1c_4k
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