mirror of https://gerrit.osmocom.org/libusrp
32 lines
1.2 KiB
Plaintext
Executable File
32 lines
1.2 KiB
Plaintext
Executable File
--Copyright (C) 1991-2006 Altera Corporation
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--Your use of Altera Corporation's design tools, logic functions
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--and other software and tools, and its AMPP partner logic
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--functions, and any output files any of the foregoing
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--(including device programming or simulation files), and any
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--associated documentation or information are expressly subject
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--to the terms and conditions of the Altera Program License
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--Subscription Agreement, Altera MegaCore Function License
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--Agreement, or other applicable license agreement, including,
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--without limitation, that your use is for the sole purpose of
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--programming logic devices manufactured by Altera and sold by
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--Altera or its authorized distributors. Please refer to the
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--applicable agreement for further details.
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component fifo_4kx16_dc
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PORT
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(
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aclr : IN STD_LOGIC := '0';
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data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
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rdclk : IN STD_LOGIC ;
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rdreq : IN STD_LOGIC ;
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wrclk : IN STD_LOGIC ;
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wrreq : IN STD_LOGIC ;
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q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
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rdempty : OUT STD_LOGIC ;
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rdusedw : OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
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wrfull : OUT STD_LOGIC ;
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wrusedw : OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
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);
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end component;
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