mirror of https://gerrit.osmocom.org/libusrp
176 lines
7.0 KiB
Verilog
Executable File
176 lines
7.0 KiB
Verilog
Executable File
// megafunction wizard: %FIFO%
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// GENERATION: STANDARD
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// VERSION: WM1.0
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// MODULE: scfifo
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// ============================================================
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// File Name: fifo_1kx16.v
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// Megafunction Name(s):
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// scfifo
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// ============================================================
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition
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// ************************************************************
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//Copyright (C) 1991-2006 Altera Corporation
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//Your use of Altera Corporation's design tools, logic functions
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//and other software and tools, and its AMPP partner logic
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//functions, and any output files any of the foregoing
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//(including device programming or simulation files), and any
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//associated documentation or information are expressly subject
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//to the terms and conditions of the Altera Program License
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//Subscription Agreement, Altera MegaCore Function License
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//Agreement, or other applicable license agreement, including,
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//without limitation, that your use is for the sole purpose of
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//programming logic devices manufactured by Altera and sold by
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//Altera or its authorized distributors. Please refer to the
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//applicable agreement for further details.
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// synopsys translate_off
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`timescale 1 ps / 1 ps
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// synopsys translate_on
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module fifo_1kx16 (
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aclr,
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clock,
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data,
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rdreq,
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wrreq,
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almost_empty,
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empty,
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full,
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q,
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usedw);
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input aclr;
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input clock;
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input [15:0] data;
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input rdreq;
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input wrreq;
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output almost_empty;
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output empty;
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output full;
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output [15:0] q;
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output [9:0] usedw;
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wire [9:0] sub_wire0;
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wire sub_wire1;
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wire sub_wire2;
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wire [15:0] sub_wire3;
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wire sub_wire4;
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wire [9:0] usedw = sub_wire0[9:0];
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wire empty = sub_wire1;
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wire almost_empty = sub_wire2;
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wire [15:0] q = sub_wire3[15:0];
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wire full = sub_wire4;
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scfifo scfifo_component (
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.rdreq (rdreq),
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.aclr (aclr),
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.clock (clock),
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.wrreq (wrreq),
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.data (data),
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.usedw (sub_wire0),
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.empty (sub_wire1),
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.almost_empty (sub_wire2),
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.q (sub_wire3),
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.full (sub_wire4)
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// synopsys translate_off
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,
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.sclr (),
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.almost_full ()
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// synopsys translate_on
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);
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defparam
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scfifo_component.add_ram_output_register = "OFF",
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scfifo_component.almost_empty_value = 504,
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scfifo_component.intended_device_family = "Cyclone",
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scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M4K",
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scfifo_component.lpm_numwords = 1024,
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scfifo_component.lpm_showahead = "OFF",
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scfifo_component.lpm_type = "scfifo",
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scfifo_component.lpm_width = 16,
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scfifo_component.lpm_widthu = 10,
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scfifo_component.overflow_checking = "ON",
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scfifo_component.underflow_checking = "ON",
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scfifo_component.use_eab = "ON";
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endmodule
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// ============================================================
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// CNX file retrieval info
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// ============================================================
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// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "1"
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// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "504"
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// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
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// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
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// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
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// Retrieval info: PRIVATE: Clock NUMERIC "0"
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// Retrieval info: PRIVATE: Depth NUMERIC "1024"
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// Retrieval info: PRIVATE: Empty NUMERIC "1"
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// Retrieval info: PRIVATE: Full NUMERIC "1"
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// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
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// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
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// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
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// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
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// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
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// Retrieval info: PRIVATE: Optimize NUMERIC "2"
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// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
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// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
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// Retrieval info: PRIVATE: UsedW NUMERIC "1"
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// Retrieval info: PRIVATE: Width NUMERIC "16"
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// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
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// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
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// Retrieval info: PRIVATE: rsFull NUMERIC "0"
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// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
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// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
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// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
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// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
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// Retrieval info: PRIVATE: wsFull NUMERIC "1"
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// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
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// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
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// Retrieval info: CONSTANT: ALMOST_EMPTY_VALUE NUMERIC "504"
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// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
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// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K"
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// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
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// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
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// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
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// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
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// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
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// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
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// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
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// Retrieval info: CONSTANT: USE_EAB STRING "ON"
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// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
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// Retrieval info: USED_PORT: almost_empty 0 0 0 0 OUTPUT NODEFVAL almost_empty
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// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
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// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
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// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
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// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
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// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
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// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
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// Retrieval info: USED_PORT: usedw 0 0 10 0 OUTPUT NODEFVAL usedw[9..0]
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// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
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// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
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// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
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// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
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// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
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// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
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// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
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// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
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// Retrieval info: CONNECT: usedw 0 0 10 0 @usedw 0 0 10 0
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// Retrieval info: CONNECT: almost_empty 0 0 0 0 @almost_empty 0 0 0 0
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// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
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// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
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// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.v TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.inc TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.cmp TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.bsf TRUE FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_inst.v TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_bb.v TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_waveforms.html FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_wave*.jpg FALSE
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