mirror of https://gerrit.osmocom.org/libusrp
40 lines
1.6 KiB
Verilog
Executable File
40 lines
1.6 KiB
Verilog
Executable File
//Copyright (C) 1991-2003 Altera Corporation
|
|
//Any megafunction design, and related netlist (encrypted or decrypted),
|
|
//support information, device programming or simulation file, and any other
|
|
//associated documentation or information provided by Altera or a partner
|
|
//under Altera's Megafunction Partnership Program may be used only
|
|
//to program PLD devices (but not masked PLD devices) from Altera. Any
|
|
//other use of such megafunction design, netlist, support information,
|
|
//device programming or simulation file, or any other related documentation
|
|
//or information is prohibited for any other purpose, including, but not
|
|
//limited to modification, reverse engineering, de-compiling, or use with
|
|
//any other silicon devices, unless such use is explicitly licensed under
|
|
//a separate agreement with Altera or a megafunction partner. Title to the
|
|
//intellectual property, including patents, copyrights, trademarks, trade
|
|
//secrets, or maskworks, embodied in any such megafunction design, netlist,
|
|
//support information, device programming or simulation file, or any other
|
|
//related documentation or information provided by Altera or a megafunction
|
|
//partner, remains with Altera, the megafunction partner, or their respective
|
|
//licensors. No other licenses, including any licenses needed under any third
|
|
//party's intellectual property, are provided herein.
|
|
|
|
module addsub16 (
|
|
add_sub,
|
|
dataa,
|
|
datab,
|
|
clock,
|
|
aclr,
|
|
clken,
|
|
result)/* synthesis synthesis_clearbox = 1 */;
|
|
|
|
input add_sub;
|
|
input [15:0] dataa;
|
|
input [15:0] datab;
|
|
input clock;
|
|
input aclr;
|
|
input clken;
|
|
output [15:0] result;
|
|
|
|
endmodule
|
|
|