mirror of https://gerrit.osmocom.org/libusrp
144 lines
5.7 KiB
Verilog
Executable File
144 lines
5.7 KiB
Verilog
Executable File
module tx_buffer_inband
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( //System
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input wire usbclk, input wire bus_reset, input wire reset,
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input wire [15:0] usbdata, output wire have_space, input wire [3:0] channels,
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//output transmit signals
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output wire [15:0] tx_i_0, output wire [15:0] tx_q_0,
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output wire [15:0] tx_i_1, output wire [15:0] tx_q_1,
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output wire [15:0] tx_i_2, output wire [15:0] tx_q_2,
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output wire [15:0] tx_i_3, output wire [15:0] tx_q_3,
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input wire txclk, input wire txstrobe, input wire WR,
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input wire clear_status, output wire tx_empty, output wire [15:0] debugbus,
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//command reader io
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output wire [15:0] rx_databus, output wire rx_WR, output wire rx_WR_done,
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input wire rx_WR_enabled,
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//register io
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output wire [1:0] reg_io_enable, output wire [31:0] reg_data_in, output wire [6:0] reg_addr,
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input wire [31:0] reg_data_out,
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//input characteristic signals
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input wire [31:0] rssi_0, input wire [31:0] rssi_1, input wire [31:0] rssi_2,
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input wire [31:0] rssi_3, input wire [31:0] rssi_wait, input wire [31:0] threshhold,
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output wire [1:0] tx_underrun,
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//system stop
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output wire stop, output wire [15:0] stop_time);
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parameter NUM_CHAN = 1 ;
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/* To generate channel readers */
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genvar i ;
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/* These will eventually be external register */
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reg [31:0] timestamp_clock ;
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wire [7:0] txstrobe_rate [NUM_CHAN-1:0] ;
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wire [31:0] rssi [3:0];
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assign rssi[0] = rssi_0;
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assign rssi[1] = rssi_1;
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assign rssi[2] = rssi_2;
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assign rssi[3] = rssi_3;
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always @(posedge txclk)
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if (reset)
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timestamp_clock <= 0;
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else
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timestamp_clock <= timestamp_clock + 1;
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/* Connections between tx_usb_fifo_reader and
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cnannel/command processing blocks */
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wire [31:0] tx_data_bus ;
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wire [NUM_CHAN:0] chan_WR ;
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wire [NUM_CHAN:0] chan_done ;
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/* Connections between data block and the
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FX2/TX chains */
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wire [NUM_CHAN:0] chan_underrun;
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wire [NUM_CHAN:0] chan_txempty;
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/* Conections between tx_data_packet_fifo and
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its reader + strobe generator */
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wire [31:0] chan_fifodata [NUM_CHAN:0] ;
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wire chan_pkt_waiting [NUM_CHAN:0] ;
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wire chan_rdreq [NUM_CHAN:0] ;
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wire chan_skip [NUM_CHAN:0] ;
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wire chan_have_space [NUM_CHAN:0] ;
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wire [14:0] debug [NUM_CHAN:0];
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/* Outputs to transmit chains */
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wire [15:0] tx_i [NUM_CHAN:0] ;
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wire [15:0] tx_q [NUM_CHAN:0] ;
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assign tx_i[NUM_CHAN] = 0;
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assign tx_q[NUM_CHAN] = 0;
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assign have_space = chan_have_space[0] & chan_have_space[1];
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assign tx_empty = chan_txempty[0] & chan_txempty[1] ;
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assign tx_i_0 = chan_txempty[0] ? 16'b0 : tx_i[0] ;
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assign tx_q_0 = chan_txempty[0] ? 16'b0 : tx_q[0] ;
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assign tx_i_1 = chan_txempty[1] ? 16'b0 : tx_i[1] ;
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assign tx_q_1 = chan_txempty[1] ? 16'b0 : tx_q[1] ;
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assign tx_q_2 = 16'b0 ;
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assign tx_i_2 = 16'b0 ;
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assign tx_q_3 = 16'b0 ;
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assign tx_i_3 = 16'b0 ;
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assign tx_i_3 = 16'b0 ;
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assign debugbus = {have_space, txclk, WR, WR_final, chan_WR, chan_done,
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chan_pkt_waiting[0], chan_pkt_waiting[1],
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chan_rdreq[0], chan_rdreq[1], chan_txempty[0], chan_txempty[1]};
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wire [31:0] usbdata_final;
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wire WR_final;
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tx_packer tx_usb_packer
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(.bus_reset(bus_reset), .usbclk(usbclk), .WR_fx2(WR),
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.usbdata(usbdata), .reset(reset), .txclk(txclk),
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.usbdata_final(usbdata_final), .WR_final(WR_final));
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channel_demux #(NUM_CHAN) channel_demuxer
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(.usbdata_final(usbdata_final), .WR_final(WR_final),
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.reset(reset), .txclk(txclk), .WR_channel(chan_WR),
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.WR_done_channel(chan_done), .ram_data(tx_data_bus));
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generate for (i = 0 ; i < NUM_CHAN; i = i + 1)
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begin : generate_channel_readers
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assign tx_underrun[i] = chan_underrun[i];
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channel_ram tx_data_packet_fifo
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(.reset(reset), .txclk(txclk), .datain(tx_data_bus),
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.WR(chan_WR[i]), .WR_done(chan_done[i]),
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.have_space(chan_have_space[i]), .dataout(chan_fifodata[i]),
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.packet_waiting(chan_pkt_waiting[i]), .RD(chan_rdreq[i]),
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.RD_done(chan_skip[i]));
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chan_fifo_reader tx_chan_reader
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(.reset(reset), .tx_clock(txclk), .tx_strobe(txstrobe),
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.timestamp_clock(timestamp_clock), .samples_format(4'b0),
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.tx_q(tx_q[i]), .tx_i(tx_i[i]), .underrun(chan_underrun[i]),
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.skip(chan_skip[i]), .rdreq(chan_rdreq[i]),
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.fifodata(chan_fifodata[i]), .pkt_waiting(chan_pkt_waiting[i]),
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.tx_empty(chan_txempty[i]), .rssi(rssi[i]), .debug(debug[i]),
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.threshhold(threshhold), .rssi_wait(rssi_wait));
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end
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endgenerate
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channel_ram tx_cmd_packet_fifo
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(.reset(reset), .txclk(txclk), .datain(tx_data_bus), .WR(chan_WR[NUM_CHAN]),
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.WR_done(chan_done[NUM_CHAN]), .have_space(chan_have_space[NUM_CHAN]),
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.dataout(chan_fifodata[NUM_CHAN]), .packet_waiting(chan_pkt_waiting[NUM_CHAN]),
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.RD(chan_rdreq[NUM_CHAN]), .RD_done(chan_skip[NUM_CHAN]));
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cmd_reader tx_cmd_reader
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(.reset(reset), .txclk(txclk), .timestamp_clock(timestamp_clock), .skip(chan_skip[NUM_CHAN]),
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.rdreq(chan_rdreq[NUM_CHAN]), .fifodata(chan_fifodata[NUM_CHAN]),
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.pkt_waiting(chan_pkt_waiting[NUM_CHAN]), .rx_databus(rx_databus),
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.rx_WR(rx_WR), .rx_WR_done(rx_WR_done), .rx_WR_enabled(rx_WR_enabled),
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.reg_data_in(reg_data_in), .reg_data_out(reg_data_out), .reg_addr(reg_addr),
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.reg_io_enable(reg_io_enable), .debug(debug[NUM_CHAN]), .stop(stop), .stop_time(stop_time));
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endmodule // tx_buffer
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