mirror of https://gerrit.osmocom.org/libusrp
83 lines
2.6 KiB
Verilog
Executable File
83 lines
2.6 KiB
Verilog
Executable File
module register_io
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(clk, reset, enable, addr, datain, dataout, debugbus, addr_wr, data_wr, strobe_wr,
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rssi_0, rssi_1, rssi_2, rssi_3, threshhold, rssi_wait, reg_0, reg_1, reg_2, reg_3,
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debug_en, misc, txmux);
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input clk;
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input reset;
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input wire [1:0] enable;
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input wire [6:0] addr;
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input wire [31:0] datain;
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output reg [31:0] dataout;
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output wire [15:0] debugbus;
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output reg [6:0] addr_wr;
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output reg [31:0] data_wr;
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output wire strobe_wr;
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input wire [31:0] rssi_0;
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input wire [31:0] rssi_1;
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input wire [31:0] rssi_2;
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input wire [31:0] rssi_3;
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output wire [31:0] threshhold;
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output wire [31:0] rssi_wait;
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input wire [15:0] reg_0;
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input wire [15:0] reg_1;
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input wire [15:0] reg_2;
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input wire [15:0] reg_3;
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input wire [3:0] debug_en;
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input wire [7:0] misc;
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input wire [31:0] txmux;
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reg strobe;
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wire [31:0] out[2:1];
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assign debugbus = {clk, enable, addr[2:0], datain[4:0], dataout[4:0]};
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assign threshhold = out[1];
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assign rssi_wait = out[2];
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assign strobe_wr = strobe;
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always @(*)
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if (reset | ~enable[1])
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begin
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strobe <= 0;
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dataout <= 0;
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end
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else
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begin
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if (enable[0])
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begin
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//read
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if (addr <= 7'd52 && addr > 7'd50)
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dataout <= out[addr-7'd50];
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else
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dataout <= 32'hFFFFFFFF;
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strobe <= 0;
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end
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else
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begin
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//write
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dataout <= dataout;
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strobe <= 1;
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data_wr <= datain;
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addr_wr <= addr;
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end
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end
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//register declarations
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/*setting_reg #(50) setting_reg0(.clock(clk),.reset(reset),
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.strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[0]));*/
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setting_reg #(51) setting_reg1(.clock(clk),.reset(reset),
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.strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[1]));
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setting_reg #(52) setting_reg2(.clock(clk),.reset(reset),
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.strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[2]));
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/*setting_reg #(53) setting_reg3(.clock(clk),.reset(reset),
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.strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[3]));
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setting_reg #(54) setting_reg4(.clock(clk),.reset(reset),
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.strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[4]));
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setting_reg #(55) setting_reg5(.clock(clk),.reset(reset),
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.strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[5]));
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setting_reg #(56) setting_reg6(.clock(clk),.reset(reset),
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.strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[6]));
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setting_reg #(57) setting_reg7(.clock(clk),.reset(reset),
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.strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[7]));*/
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endmodule
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