mirror of https://gerrit.osmocom.org/libusrp
61 lines
1.8 KiB
Verilog
Executable File
61 lines
1.8 KiB
Verilog
Executable File
// -*- verilog -*-
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//
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// USRP - Universal Software Radio Peripheral
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//
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// Copyright (C) 2003 Matt Ettus
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//
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// This program is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation; either version 2 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
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//
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module cordic_stage( clock, reset, enable, xi,yi,zi,constant,xo,yo,zo);
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parameter bitwidth = 16;
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parameter zwidth = 16;
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parameter shift = 1;
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input clock;
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input reset;
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input enable;
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input [bitwidth-1:0] xi,yi;
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input [zwidth-1:0] zi;
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input [zwidth-1:0] constant;
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output [bitwidth-1:0] xo,yo;
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output [zwidth-1:0] zo;
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wire z_is_pos = ~zi[zwidth-1];
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reg [bitwidth-1:0] xo,yo;
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reg [zwidth-1:0] zo;
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always @(posedge clock)
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if(reset)
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begin
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xo <= #1 0;
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yo <= #1 0;
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zo <= #1 0;
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end
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else if(enable)
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begin
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xo <= #1 z_is_pos ?
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xi - {{shift+1{yi[bitwidth-1]}},yi[bitwidth-2:shift]} :
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xi + {{shift+1{yi[bitwidth-1]}},yi[bitwidth-2:shift]};
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yo <= #1 z_is_pos ?
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yi + {{shift+1{xi[bitwidth-1]}},xi[bitwidth-2:shift]} :
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yi - {{shift+1{xi[bitwidth-1]}},xi[bitwidth-2:shift]};
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zo <= #1 z_is_pos ?
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zi - constant :
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zi + constant;
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end
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endmodule
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