mirror of https://gerrit.osmocom.org/libusrp
110 lines
3.9 KiB
Verilog
Executable File
110 lines
3.9 KiB
Verilog
Executable File
// -*- verilog -*-
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//
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// USRP - Universal Software Radio Peripheral
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//
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// Copyright (C) 2003 Matt Ettus
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//
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// This program is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation; either version 2 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
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//
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module cordic(clock, reset, enable, xi, yi, zi, xo, yo, zo );
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parameter bitwidth = 16;
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parameter zwidth = 16;
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input clock;
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input reset;
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input enable;
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input [bitwidth-1:0] xi, yi;
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output [bitwidth-1:0] xo, yo;
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input [zwidth-1:0] zi;
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output [zwidth-1:0] zo;
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reg [bitwidth+1:0] x0,y0;
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reg [zwidth-2:0] z0;
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wire [bitwidth+1:0] x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12;
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wire [bitwidth+1:0] y1,y2,y3,y4,y5,y6,y7,y8,y9,y10,y11,y12;
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wire [zwidth-2:0] z1,z2,z3,z4,z5,z6,z7,z8,z9,z10,z11,z12;
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wire [bitwidth+1:0] xi_ext = {{2{xi[bitwidth-1]}},xi};
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wire [bitwidth+1:0] yi_ext = {{2{yi[bitwidth-1]}},yi};
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// Compute consts. Would be easier if vlog had atan...
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// see gen_cordic_consts.py
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`define c00 16'd8192
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`define c01 16'd4836
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`define c02 16'd2555
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`define c03 16'd1297
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`define c04 16'd651
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`define c05 16'd326
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`define c06 16'd163
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`define c07 16'd81
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`define c08 16'd41
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`define c09 16'd20
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`define c10 16'd10
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`define c11 16'd5
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`define c12 16'd3
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`define c13 16'd1
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`define c14 16'd1
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`define c15 16'd0
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`define c16 16'd0
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always @(posedge clock)
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if(reset)
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begin
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x0 <= #1 0; y0 <= #1 0; z0 <= #1 0;
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end
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else if(enable)
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begin
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z0 <= #1 zi[zwidth-2:0];
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case (zi[zwidth-1:zwidth-2])
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2'b00, 2'b11 :
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begin
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x0 <= #1 xi_ext;
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y0 <= #1 yi_ext;
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end
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2'b01, 2'b10 :
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begin
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x0 <= #1 -xi_ext;
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y0 <= #1 -yi_ext;
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end
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endcase // case(zi[zwidth-1:zwidth-2])
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end // else: !if(reset)
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// FIXME need to handle variable number of stages
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// FIXME should be able to narrow zwidth but quartus makes it bigger...
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// This would be easier if arrays worked better in vlog...
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cordic_stage #(bitwidth+2,zwidth-1,0) cordic_stage0 (clock,reset,enable,x0,y0,z0,`c00,x1,y1,z1);
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cordic_stage #(bitwidth+2,zwidth-1,1) cordic_stage1 (clock,reset,enable,x1,y1,z1,`c01,x2,y2,z2);
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cordic_stage #(bitwidth+2,zwidth-1,2) cordic_stage2 (clock,reset,enable,x2,y2,z2,`c02,x3,y3,z3);
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cordic_stage #(bitwidth+2,zwidth-1,3) cordic_stage3 (clock,reset,enable,x3,y3,z3,`c03,x4,y4,z4);
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cordic_stage #(bitwidth+2,zwidth-1,4) cordic_stage4 (clock,reset,enable,x4,y4,z4,`c04,x5,y5,z5);
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cordic_stage #(bitwidth+2,zwidth-1,5) cordic_stage5 (clock,reset,enable,x5,y5,z5,`c05,x6,y6,z6);
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cordic_stage #(bitwidth+2,zwidth-1,6) cordic_stage6 (clock,reset,enable,x6,y6,z6,`c06,x7,y7,z7);
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cordic_stage #(bitwidth+2,zwidth-1,7) cordic_stage7 (clock,reset,enable,x7,y7,z7,`c07,x8,y8,z8);
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cordic_stage #(bitwidth+2,zwidth-1,8) cordic_stage8 (clock,reset,enable,x8,y8,z8,`c08,x9,y9,z9);
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cordic_stage #(bitwidth+2,zwidth-1,9) cordic_stage9 (clock,reset,enable,x9,y9,z9,`c09,x10,y10,z10);
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cordic_stage #(bitwidth+2,zwidth-1,10) cordic_stage10 (clock,reset,enable,x10,y10,z10,`c10,x11,y11,z11);
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cordic_stage #(bitwidth+2,zwidth-1,11) cordic_stage11 (clock,reset,enable,x11,y11,z11,`c11,x12,y12,z12);
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assign xo = x12[bitwidth:1];
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assign yo = y12[bitwidth:1];
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//assign xo = x12[bitwidth+1:2]; // CORDIC gain is ~1.6, plus gain from rotating vectors
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//assign yo = y12[bitwidth+1:2];
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assign zo = z12;
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endmodule // cordic
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