mirror of https://gerrit.osmocom.org/libusrp
115 lines
3.6 KiB
Verilog
115 lines
3.6 KiB
Verilog
//
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// This file is machine generated from fpga_regs_common.h
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// Do not edit by hand; your edits will be overwritten.
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//
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// This file defines registers common to all FPGA configurations.
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// Registers 0 to 31 are reserved for use in this file.
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// The FPGA needs to know the rate that samples are coming from and
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// going to the A/D's and D/A's. div = 128e6 / sample_rate
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`define FR_TX_SAMPLE_RATE_DIV 7'd0
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`define FR_RX_SAMPLE_RATE_DIV 7'd1
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// 2 is available.
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// 3 is available.
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`define FR_MASTER_CTRL 7'd4 // master enable and reset controls
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// i/o direction registers for pins that go to daughterboards.
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// Setting the bit makes it an output from the FPGA to the d'board.
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// top 16 is mask, low 16 is value
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`define FR_OE_0 7'd5 // slot 0
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`define FR_OE_1 7'd6
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`define FR_OE_2 7'd7
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`define FR_OE_3 7'd8
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// i/o registers for pins that go to daughterboards.
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// top 16 is a mask, low 16 is value
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`define FR_IO_0 7'd9 // slot 0
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`define FR_IO_1 7'd10
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`define FR_IO_2 7'd11
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`define FR_IO_3 7'd12
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`define FR_MODE 7'd13
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// If the corresponding bit is set, internal FPGA debug circuitry
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// controls the i/o pins for the associated bank of daughterboard
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// i/o pins. Typically used for debugging FPGA designs.
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`define FR_DEBUG_EN 7'd14
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// If the corresponding bit is set, enable the automatic DC
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// offset correction control loop.
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//
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// The 4 low bits are significant:
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//
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// ADC0 = (1 << 0)
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// ADC1 = (1 << 1)
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// ADC2 = (1 << 2)
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// ADC3 = (1 << 3)
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//
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// This control loop works if the attached daugherboard blocks DC.
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// Currently all daughterboards do block DC. This includes:
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// basic rx, dbs_rx, tv_rx, flex_xxx_rx.
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`define FR_DC_OFFSET_CL_EN 7'd15 // DC Offset Control Loop Enable
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// offset corrections for ADC's and DAC's (2's complement)
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`define FR_ADC_OFFSET_0 7'd16
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`define FR_ADC_OFFSET_1 7'd17
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`define FR_ADC_OFFSET_2 7'd18
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`define FR_ADC_OFFSET_3 7'd19
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// ------------------------------------------------------------------------
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// Automatic Transmit/Receive switching
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//
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// If automatic transmit/receive (ATR) switching is enabled in the
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// FR_ATR_CTL register, the presence or absence of data in the FPGA
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// transmit fifo selects between two sets of values for each of the 4
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// banks of daughterboard i/o pins.
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//
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// Each daughterboard slot has 3 16-bit registers associated with it:
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// FR_ATR_MASK_*, FR_ATR_TXVAL_* and FR_ATR_RXVAL_*
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//
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// FR_ATR_MASK_{0,1,2,3}:
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//
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// These registers determine which of the daugherboard i/o pins are
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// affected by ATR switching. If a bit in the mask is set, the
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// corresponding i/o bit is controlled by ATR, else it's output
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// value comes from the normal i/o pin output register:
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// FR_IO_{0,1,2,3}.
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//
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// FR_ATR_TXVAL_{0,1,2,3}:
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// FR_ATR_RXVAL_{0,1,2,3}:
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//
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// If the Tx fifo contains data, then the bits from TXVAL that are
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// selected by MASK are output. Otherwise, the bits from RXVAL that
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// are selected by MASK are output.
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`define FR_ATR_MASK_0 7'd20 // slot 0
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`define FR_ATR_TXVAL_0 7'd21
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`define FR_ATR_RXVAL_0 7'd22
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`define FR_ATR_MASK_1 7'd23 // slot 1
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`define FR_ATR_TXVAL_1 7'd24
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`define FR_ATR_RXVAL_1 7'd25
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`define FR_ATR_MASK_2 7'd26 // slot 2
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`define FR_ATR_TXVAL_2 7'd27
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`define FR_ATR_RXVAL_2 7'd28
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`define FR_ATR_MASK_3 7'd29 // slot 3
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`define FR_ATR_TXVAL_3 7'd30
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`define FR_ATR_RXVAL_3 7'd31
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