mirror of https://gerrit.osmocom.org/libusrp
107 lines
3.1 KiB
Verilog
107 lines
3.1 KiB
Verilog
// -*- verilog -*-
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//
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// USRP - Universal Software Radio Peripheral
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//
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// Copyright (C) 2003 Matt Ettus
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//
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// This program is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation; either version 2 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
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//
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// Following defines conditionally include RX path circuitry
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`include "config.vh" // resolved relative to project root
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module rx_chain
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(input clock,
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input reset,
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input enable,
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input wire [7:0] decim_rate,
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input sample_strobe,
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input decimator_strobe,
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output wire hb_strobe,
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input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe,
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input wire [15:0] i_in,
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input wire [15:0] q_in,
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output wire [15:0] i_out,
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output wire [15:0] q_out,
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output wire [15:0] debugdata,output wire [15:0] debugctrl
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);
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parameter FREQADDR = 0;
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parameter PHASEADDR = 0;
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wire [31:0] phase;
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wire [15:0] bb_i, bb_q;
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wire [15:0] hb_in_i, hb_in_q;
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assign debugdata = hb_in_i;
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`ifdef RX_NCO_ON
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phase_acc #(FREQADDR,PHASEADDR,32) rx_phase_acc
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(.clk(clock),.reset(reset),.enable(enable),
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.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
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.strobe(sample_strobe),.phase(phase) );
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cordic rx_cordic
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( .clock(clock),.reset(reset),.enable(enable),
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.xi(i_in),.yi(q_in),.zi(phase[31:16]),
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.xo(bb_i),.yo(bb_q),.zo() );
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`else
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assign bb_i = i_in;
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assign bb_q = q_in;
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assign sample_strobe = 1;
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`endif // !`ifdef RX_NCO_ON
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`ifdef RX_CIC_ON
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cic_decim cic_decim_i_0
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( .clock(clock),.reset(reset),.enable(enable),
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.rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
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.signal_in(bb_i),.signal_out(hb_in_i) );
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`else
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assign hb_in_i = bb_i;
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assign decimator_strobe = sample_strobe;
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`endif
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`ifdef RX_HB_ON
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halfband_decim hbd_i_0
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( .clock(clock),.reset(reset),.enable(enable),
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.strobe_in(decimator_strobe),.strobe_out(hb_strobe),
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.data_in(hb_in_i),.data_out(i_out),.debugctrl(debugctrl) );
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`else
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assign i_out = hb_in_i;
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assign hb_strobe = decimator_strobe;
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`endif
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`ifdef RX_CIC_ON
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cic_decim cic_decim_q_0
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( .clock(clock),.reset(reset),.enable(enable),
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.rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
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.signal_in(bb_q),.signal_out(hb_in_q) );
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`else
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assign hb_in_q = bb_q;
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`endif
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`ifdef RX_HB_ON
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halfband_decim hbd_q_0
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( .clock(clock),.reset(reset),.enable(enable),
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.strobe_in(decimator_strobe),.strobe_out(),
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.data_in(hb_in_q),.data_out(q_out) );
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`else
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assign q_out = hb_in_q;
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`endif
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endmodule // rx_chain
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