mirror of https://gerrit.osmocom.org/libusrp
74 lines
3.6 KiB
Verilog
74 lines
3.6 KiB
Verilog
// -*- verilog -*-
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//
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// USRP - Universal Software Radio Peripheral
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//
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// Copyright (C) 2006 Martin Dudok van Heel
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//
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// This program is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation; either version 2 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
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//
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`include "config.vh"
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`include "../../../firmware/include/fpga_regs_common.v"
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`include "../../../firmware/include/fpga_regs_standard.v"
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// Clock, enable, and reset controls for whole system
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// Modified version to enable multi_usrp synchronisation
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module master_control_multi
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( input master_clk, input usbclk,
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input wire [6:0] serial_addr, input wire [31:0] serial_data, input wire serial_strobe,
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input wire rx_slave_sync,
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output tx_bus_reset, output rx_bus_reset,
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output wire tx_dsp_reset, output wire rx_dsp_reset,
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output wire enable_tx, output wire enable_rx,
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output wire sync_rx,
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output wire [7:0] interp_rate, output wire [7:0] decim_rate,
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output tx_sample_strobe, output strobe_interp,
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output rx_sample_strobe, output strobe_decim,
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input tx_empty,
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input wire [15:0] debug_0,input wire [15:0] debug_1,input wire [15:0] debug_2,input wire [15:0] debug_3,
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output wire [15:0] reg_0, output wire [15:0] reg_1, output wire [15:0] reg_2, output wire [15:0] reg_3
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);
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wire [15:0] reg_1_std;
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master_control master_control_standard
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( .master_clk(master_clk),.usbclk(usbclk),
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.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
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.tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset),
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.tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset),
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.enable_tx(enable_tx),.enable_rx(enable_rx),
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.interp_rate(interp_rate),.decim_rate(decim_rate),
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.tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp),
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.rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim),
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.tx_empty(tx_empty),
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.debug_0(debug_0),.debug_1(debug_1),
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.debug_2(debug_2),.debug_3(debug_3),
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.reg_0(reg_0),.reg_1(reg_1_std),.reg_2(reg_2),.reg_3(reg_3) );
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// FIXME need a separate reset for all control settings
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// Master/slave Controls assignments
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wire [7:0] rx_master_slave_controls;
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setting_reg_masked #(`FR_RX_MASTER_SLAVE) sr_rx_mstr_slv_ctrl(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(rx_master_slave_controls));
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assign sync_rx = rx_master_slave_controls[`bitnoFR_RX_SYNC] | (rx_master_slave_controls[`bitnoFR_RX_SYNC_SLAVE] & rx_slave_sync);
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//sync if we are told by master_control or if we get a hardware slave sync
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//TODO There can be a one sample difference between master and slave sync.
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// Maybe use a register for sync_rx which uses the (neg or pos) edge of master_clock and/or rx_slave_sync to trigger
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// Or even use a seperate sync_rx_out and sync_rx_internal (which lags behind)
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//TODO make output pin not hardwired
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assign reg_1 ={(rx_master_slave_controls[`bitnoFR_RX_SYNC_MASTER])? sync_rx:reg_1_std[15],reg_1_std[14:0]};
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endmodule // master_control
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