mirror of https://gerrit.osmocom.org/libusrp
146 lines
2.9 KiB
Verilog
Executable File
146 lines
2.9 KiB
Verilog
Executable File
// -*- verilog -*-
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//
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// USRP - Universal Software Radio Peripheral
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//
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// Copyright (C) 2003 Matt Ettus
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//
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// This program is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation; either version 2 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
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//
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// Tasks
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/////////////////////////////////////////////////
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// USB interface
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task initialize_usb;
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begin
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OE = 0;WE = 0;RD = 0;
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usbdatareg <= 16'h0;
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end
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endtask
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task write_from_usb;
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begin
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tb_oe <= 1'b1;
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@(posedge usbclk);
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usbdatareg <= #1 $random % 65536;
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WE <= #1 1'b1;
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@(posedge usbclk)
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WE <= #1 1'b0;
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tb_oe <= #1 1'b0;
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end
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endtask
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task burst_usb_write;
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input [31:0] repeat_count;
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begin
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tb_oe <= 1'b1;
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repeat(repeat_count)
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begin
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@(posedge usbclk)
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usbdatareg <= #1 usbdatareg + 1; //$random % 65536;
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WE <= #1 1'b1;
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end
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@(posedge usbclk)
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WE <= #1 1'b0;
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tb_oe <= 1'b0;
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end
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endtask // burst_usb_write
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task read_from_usb;
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begin
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@(posedge usbclk);
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RD <= #1 1'b1;
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@(posedge usbclk);
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RD <= #1 1'b0;
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OE <= #1 1'b1;
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@(posedge usbclk);
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OE <= #1 1'b0;
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end
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endtask
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task burst_usb_read;
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input [31:0] repeat_count;
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begin
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while (~have_packet_rdy) begin
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@(posedge usbclk);
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end
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@(posedge usbclk)
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RD <= #1 1'b1;
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repeat(repeat_count)
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begin
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@(posedge usbclk)
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OE <= #1 1'b1;
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end
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RD <= #1 1'b0;
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@(posedge usbclk);
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OE <= #1 1'b0;
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end
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endtask // burst_usb_read
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/////////////////////////////////////////////////
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// TX and RX enable
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//////////////////////////////////////////////////
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// Set up control bus
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`define ch1in_freq 0
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`define ch2in_freq 1
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`define ch3in_freq 2
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`define ch4in_freq 3
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`define ch1out_freq 4
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`define ch2out_freq 5
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`define ch3out_freq 6
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`define ch4out_freq 7
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`define rates 8
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`define misc 9
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task send_config_word;
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input [7:0] addr;
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input [31:0] data;
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integer i;
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begin
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#10 serenable = 1;
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for(i=7;i>=0;i=i-1)
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begin
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#10 serdata = addr[i];
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#10 serclk = 0;
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#10 serclk = 1;
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#10 serclk = 0;
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end
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for(i=31;i>=0;i=i-1)
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begin
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#10 serdata = data[i];
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#10 serclk = 0;
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#10 serclk = 1;
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#10 serclk = 0;
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end
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#10 serenable = 0;
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// #10 serload = 0;
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// #10 serload = 1;
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#10 serclk = 1;
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#10 serclk = 0;
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//#10 serload = 0;
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end
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endtask // send_config_word
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/////////////////////////////////////////////////////////
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