mirror of https://gerrit.osmocom.org/libusrp
77 lines
2.4 KiB
Verilog
77 lines
2.4 KiB
Verilog
// -*- verilog -*-
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//
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// USRP - Universal Software Radio Peripheral
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//
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// Copyright (C) 2003 Matt Ettus
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//
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// This program is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation; either version 2 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
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//
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module tx_chain_hb
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(input clock,
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input reset,
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input enable,
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input wire [7:0] interp_rate,
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input sample_strobe,
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input interpolator_strobe,
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input hb_strobe,
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input wire [31:0] freq,
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input wire [15:0] i_in,
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input wire [15:0] q_in,
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output wire [15:0] i_out,
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output wire [15:0] q_out,
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output wire [15:0] debug, output [15:0] hb_i_out
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);
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assign debug[15:13] = {sample_strobe,hb_strobe,interpolator_strobe};
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wire [15:0] bb_i, bb_q;
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wire [15:0] hb_i_out, hb_q_out;
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halfband_interp hb
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(.clock(clock),.reset(reset),.enable(enable),
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.strobe_in(interpolator_strobe),.strobe_out(hb_strobe),
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.signal_in_i(i_in),.signal_in_q(q_in),
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.signal_out_i(hb_i_out),.signal_out_q(hb_q_out),
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.debug(debug[12:0]));
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cic_interp cic_interp_i
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( .clock(clock),.reset(reset),.enable(enable),
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.rate(interp_rate),.strobe_in(hb_strobe),.strobe_out(sample_strobe),
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.signal_in(hb_i_out),.signal_out(bb_i) );
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cic_interp cic_interp_q
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( .clock(clock),.reset(reset),.enable(enable),
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.rate(interp_rate),.strobe_in(hb_strobe),.strobe_out(sample_strobe),
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.signal_in(hb_q_out),.signal_out(bb_q) );
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`define NOCORDIC_TX
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`ifdef NOCORDIC_TX
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assign i_out = bb_i;
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assign q_out = bb_q;
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`else
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wire [31:0] phase;
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phase_acc phase_acc_tx
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(.clk(clock),.reset(reset),.enable(enable),
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.strobe(sample_strobe),.freq(freq),.phase(phase) );
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cordic tx_cordic_0
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( .clock(clock),.reset(reset),.enable(sample_strobe),
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.xi(bb_i),.yi(bb_q),.zi(phase[31:16]),
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.xo(i_out),.yo(q_out),.zo() );
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`endif
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endmodule // tx_chain
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