mirror of https://gerrit.osmocom.org/libusrp
104 lines
3.2 KiB
Verilog
104 lines
3.2 KiB
Verilog
// -*- verilog -*-
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//
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// USRP - Universal Software Radio Peripheral
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//
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// Copyright (C) 2003 Matt Ettus
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//
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// This program is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation; either version 2 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
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//
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module rx_chain_dual
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(input clock,
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input clock_2x,
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input reset,
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input enable,
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input wire [7:0] decim_rate,
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input sample_strobe,
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input decimator_strobe,
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input wire [31:0] freq0,
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input wire [15:0] i_in0,
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input wire [15:0] q_in0,
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output wire [15:0] i_out0,
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output wire [15:0] q_out0,
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input wire [31:0] freq1,
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input wire [15:0] i_in1,
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input wire [15:0] q_in1,
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output wire [15:0] i_out1,
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output wire [15:0] q_out1
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);
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wire [15:0] phase;
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wire [15:0] bb_i, bb_q;
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wire [15:0] i_in, q_in;
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wire [31:0] phase0;
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wire [31:0] phase1;
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reg [15:0] bb_i0, bb_q0;
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reg [15:0] bb_i1, bb_q1;
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// We want to time-share the CORDIC by double-clocking it
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phase_acc rx_phase_acc_0
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(.clk(clock),.reset(reset),.enable(enable),
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.strobe(sample_strobe),.freq(freq0),.phase(phase0) );
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phase_acc rx_phase_acc_1
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(.clk(clock),.reset(reset),.enable(enable),
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.strobe(sample_strobe),.freq(freq1),.phase(phase1) );
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assign phase = clock ? phase0[31:16] : phase1[31:16];
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assign i_in = clock ? i_in0 : i_in1;
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assign q_in = clock ? q_in0 : q_in1;
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// This appears reversed because of the number of CORDIC stages
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always @(posedge clock_2x)
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if(clock)
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begin
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bb_i1 <= #1 bb_i;
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bb_q1 <= #1 bb_q;
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end
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else
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begin
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bb_i0 <= #1 bb_i;
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bb_q0 <= #1 bb_q;
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end
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cordic rx_cordic
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( .clock(clock_2x),.reset(reset),.enable(enable),
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.xi(i_in),.yi(q_in),.zi(phase),
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.xo(bb_i),.yo(bb_q),.zo() );
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cic_decim cic_decim_i_0
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( .clock(clock),.reset(reset),.enable(enable),
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.rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
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.signal_in(bb_i0),.signal_out(i_out0) );
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cic_decim cic_decim_q_0
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( .clock(clock),.reset(reset),.enable(enable),
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.rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
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.signal_in(bb_q0),.signal_out(q_out0) );
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cic_decim cic_decim_i_1
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( .clock(clock),.reset(reset),.enable(enable),
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.rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
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.signal_in(bb_i1),.signal_out(i_out1) );
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cic_decim cic_decim_q_1
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( .clock(clock),.reset(reset),.enable(enable),
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.rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
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.signal_in(bb_q1),.signal_out(q_out1) );
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endmodule // rx_chain
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