mirror of https://gerrit.osmocom.org/libusrp
53 lines
1.6 KiB
Verilog
Executable File
53 lines
1.6 KiB
Verilog
Executable File
// -*- verilog -*-
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//
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// USRP - Universal Software Radio Peripheral
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//
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// Copyright (C) 2003 Matt Ettus
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//
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// This program is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation; either version 2 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
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//
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// Basic Phase accumulator for DDS
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module phase_acc (clk,reset,enable,strobe,serial_addr,serial_data,serial_strobe,phase);
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parameter FREQADDR = 0;
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parameter PHASEADDR = 0;
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parameter resolution = 32;
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input clk, reset, enable, strobe;
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input [6:0] serial_addr;
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input [31:0] serial_data;
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input serial_strobe;
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output reg [resolution-1:0] phase;
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wire [resolution-1:0] freq;
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setting_reg #(FREQADDR) sr_rxfreq0(.clock(clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(freq));
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always @(posedge clk)
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if(reset)
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phase <= #1 32'b0;
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else if(serial_strobe & (serial_addr == PHASEADDR))
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phase <= #1 serial_data;
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else if(enable & strobe)
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phase <= #1 phase + freq;
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endmodule // phase_acc
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