mirror of https://gerrit.osmocom.org/libusrp
53 lines
2.2 KiB
Verilog
53 lines
2.2 KiB
Verilog
// -*- verilog -*-
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//
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// USRP - Universal Software Radio Peripheral
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//
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// Copyright (C) 2005,2006 Matt Ettus
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//
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// This program is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation; either version 2 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
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//
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`include "../../firmware/include/fpga_regs_common.v"
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`include "../../firmware/include/fpga_regs_standard.v"
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module io_pins
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( inout wire [15:0] io_0, inout wire [15:0] io_1, inout wire [15:0] io_2, inout wire [15:0] io_3,
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input wire [15:0] reg_0, input wire [15:0] reg_1, input wire [15:0] reg_2, input wire [15:0] reg_3,
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input clock, input rx_reset, input tx_reset,
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input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe);
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reg [15:0] io_0_oe,io_1_oe,io_2_oe,io_3_oe;
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bidir_reg bidir_reg_0 (.tristate(io_0),.oe(io_0_oe),.reg_val(reg_0));
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bidir_reg bidir_reg_1 (.tristate(io_1),.oe(io_1_oe),.reg_val(reg_1));
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bidir_reg bidir_reg_2 (.tristate(io_2),.oe(io_2_oe),.reg_val(reg_2));
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bidir_reg bidir_reg_3 (.tristate(io_3),.oe(io_3_oe),.reg_val(reg_3));
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// Upper 16 bits are mask for lower 16
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always @(posedge clock)
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if(serial_strobe)
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case(serial_addr)
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`FR_OE_0 : io_0_oe
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<= #1 (io_0_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
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`FR_OE_1 : io_1_oe
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<= #1 (io_1_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
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`FR_OE_2 : io_2_oe
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<= #1 (io_2_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
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`FR_OE_3 : io_3_oe
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<= #1 (io_3_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
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endcase // case(serial_addr)
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endmodule // io_pins
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