mirror of https://gerrit.osmocom.org/libusrp
127 lines
3.8 KiB
Verilog
127 lines
3.8 KiB
Verilog
// -*- verilog -*-
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//
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// USRP - Universal Software Radio Peripheral
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//
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// Copyright (C) 2003 Matt Ettus
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//
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// This program is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation; either version 2 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
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//
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// Vendor Independent FIFO module
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// Width and Depth should be parameterizable
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// Asynchronous clocks for each side
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// Read side is read-acknowledge, not read-request
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// FIFO does not enforce "don't write when full, don't read when empty"
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// That is up to the connecting modules
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// The FIFO only holds 2^N-1 entries, not 2^N
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module fifo (reset,data,write,wrclk,wr_used,q,read_ack,rdclk,rd_used);
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parameter width=32;
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parameter depth=10;
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input reset; // Asynchronous
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input [width-1:0] data;
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input write;
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input wrclk;
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output [depth-1:0] wr_used;
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output [width-1:0] q;
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input read_ack;
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input rdclk;
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output [depth-1:0] rd_used;
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reg [depth-1:0] read_addr, write_addr,
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read_addr_gray, read_addr_gray_sync,
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write_addr_gray, write_addr_gray_sync;
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// Pseudo-dual-port RAM
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dpram #(.depth(10),.width(width),.size(1024))
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fifo_ram (.wclk(wrclk),.wdata(data),.waddr(write_addr),.wen(write),
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.rclk(rdclk), .rdata(q),.raddr(read_addr) );
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wire [depth-1:0] wag,rag;
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// Keep track of own side's pointer
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always @(posedge wrclk or posedge reset)
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if(reset) write_addr <= #1 0;
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else if(write) write_addr <= #1 write_addr + 1;
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always @(posedge rdclk or posedge reset)
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if(reset) read_addr <= #1 0;
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else if(read_ack) read_addr <= #1 read_addr + 1;
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// Convert own side pointer to gray
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bin2gray #(depth) write_b2g (write_addr,wag);
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bin2gray #(depth) read_b2g (read_addr,rag);
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// Latch it
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always @(posedge wrclk or posedge reset)
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if(reset) write_addr_gray <= #1 0;
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else write_addr_gray <= #1 wag;
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always @(posedge rdclk or posedge reset)
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if(reset) read_addr_gray <= #1 0;
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else read_addr_gray <= #1 rag;
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// Send it to other side and latch
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always @(posedge wrclk or posedge reset)
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if(reset) read_addr_gray_sync <= #1 0;
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else read_addr_gray_sync <= #1 read_addr_gray;
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always @(posedge rdclk or posedge reset)
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if(reset) write_addr_gray_sync <= #1 0;
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else write_addr_gray_sync <= #1 write_addr_gray;
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wire [depth-1:0] write_addr_sync, read_addr_sync;
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// Convert back to binary
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gray2bin #(depth) write_g2b (write_addr_gray_sync, write_addr_sync);
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gray2bin #(depth) read_g2b (read_addr_gray_sync, read_addr_sync);
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assign rd_used = write_addr_sync - read_addr;
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assign wr_used = write_addr - read_addr_sync;
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endmodule // fifo
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module bin2gray(bin_val,gray_val);
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parameter width = 8;
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input [width-1:0] bin_val;
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output reg [width-1:0] gray_val;
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integer i;
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always @*
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begin
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gray_val[width-1] = bin_val[width-1];
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for(i=0;i<width-1;i=i+1)
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gray_val[i] = bin_val[i] ^ bin_val[i+1];
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end
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endmodule // bin2gray
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module gray2bin(gray_val,bin_val);
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parameter width = 8;
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input [width-1:0] gray_val;
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output reg [width-1:0] bin_val;
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integer i;
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always @*
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begin
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bin_val[width-1] = gray_val[width-1];
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for(i=width-2;i>=0;i=i-1)
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bin_val[i] = bin_val[i+1] ^ gray_val[i];
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end
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endmodule // gray2bin
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