mirror of https://gerrit.osmocom.org/libusrp
74 lines
1.8 KiB
Verilog
74 lines
1.8 KiB
Verilog
// -*- verilog -*-
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//
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// USRP - Universal Software Radio Peripheral
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//
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// Copyright (C) 2003 Matt Ettus
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//
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// This program is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation; either version 2 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
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//
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module cic_decim_tb;
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cic_decim #(.bitwidth(16),.stages(4))
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decim(clock,reset,enable,strobe_in,strobe_out,signal_in,signal_out);
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reg clock;
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reg reset;
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reg enable;
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wire strobe;
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reg [15:0] signal_in;
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wire [15:0] signal_out;
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assign strobe_in = 1'b1;
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reg strobe_out;
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always @(posedge clock)
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while(1)
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begin
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@(posedge clock);
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@(posedge clock);
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@(posedge clock);
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@(posedge clock);
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strobe_out <= 1'b1;
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@(posedge clock);
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@(posedge clock);
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@(posedge clock);
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@(posedge clock);
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strobe_out <= 1'b0;
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end
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initial clock = 0;
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always #50 clock = ~clock;
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initial reset = 1;
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initial #1000 reset = 0;
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initial enable = 0;
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initial #2000 enable = 1;
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initial signal_in = 16'h1;
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initial #500000 signal_in = 16'h7fff;
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initial #1000000 signal_in = 16'h8000;
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initial #1500000 signal_in = 16'hffff;
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initial $dumpfile("decim.vcd");
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initial $dumpvars(0,cic_decim_tb);
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initial #10000000 $finish;
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endmodule // cic_decim_tb
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