mirror of https://gerrit.osmocom.org/libusrp
109 lines
2.7 KiB
Verilog
Executable File
109 lines
2.7 KiB
Verilog
Executable File
// -*- verilog -*-
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//
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// USRP - Universal Software Radio Peripheral
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//
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// Copyright (C) 2003 Matt Ettus
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//
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// This program is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation; either version 2 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
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//
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// testbench for fullchip
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module interp_tb();
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`include "usrp_tasks.v"
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reg clk_120mhz;
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reg usbclk;
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reg reset;
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reg [11:0] adc1_data, adc2_data;
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wire [13:0] dac1_data, dac2_data;
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wire [5:0] usbctl;
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wire [5:0] usbrdy;
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wire [15:0] usbdata;
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reg WE, RD, OE;
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assign usbctl[0] = WE;
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assign usbctl[1] = RD;
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assign usbctl[2] = OE;
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assign usbctl[5:3] = 0;
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reg tb_oe;
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assign usbdata = tb_oe ? usbdatareg : 16'hxxxx;
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reg serload, serenable, serclk, serdata;
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reg enable_tx, enable_rx;
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reg [15:0] usbdatareg;
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///////////////////////////////////////////////
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// Simulation Control
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initial
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begin
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$dumpfile("interp_tb.vcd");
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$dumpvars(0, fc_tb);
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end
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initial #100000 $finish;
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///////////////////////////////////////////////
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// Monitors
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reg [7:0] counter_interp;
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wire [7:0] interp_rate;
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assign interp_rate = 32;
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initial $monitor(dac1_data);
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always @(posedge clk_120mhz)
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begin
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if(reset | ~enable_tx)
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counter_interp <= #1 0;
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else if(counter_interp == 0)
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counter_interp <= #1 interp_rate - 8'b1;
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else
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counter_interp <= #1 counter_interp - 8'b1;
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end
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///////////////////////////////////////////////
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// Clock and reset
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initial clk_120mhz = 0;
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initial usbclk = 0;
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always #48 clk_120mhz = ~clk_120mhz;
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always #120 usbclk = ~usbclk;
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initial reset = 1'b1;
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initial #500 reset = 1'b0;
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initial enable_tx = 1'b1;
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wire [31:0] interp_out, q_interp_out;
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wire [31:0] decim_out;
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wire [31:0] phase;
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cic_interp #(.bitwidth(32),.stages(4))
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interp_i(.clock(clk_120mhz),.reset(reset),.enable(enable_tx),
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.strobe(counter_interp == 8'b0),.signal_in(32'h1),.signal_out(interp_out));
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cic_decim #(.bitwidth(32),.stages(4))
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decim(.clock(clk_120mhz),.reset(reset),.enable(enable_tx),
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.strobe(counter_interp == 8'b0),.signal_in(32'h1),.signal_out(decim_out));
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endmodule
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