mirror of https://gerrit.osmocom.org/libusrp
175 lines
3.8 KiB
Verilog
Executable File
175 lines
3.8 KiB
Verilog
Executable File
// -*- verilog -*-
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//
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// USRP - Universal Software Radio Peripheral
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//
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// Copyright (C) 2003 Matt Ettus
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//
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// This program is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation; either version 2 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
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//
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// testbench for fullchip
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`timescale 1ns/1ns
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module fullchip_tb();
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`include "usrp_tasks.v"
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fullchip fullchip
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(
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.clk_120mhz(clk_120mhz),
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.reset(reset),
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.enable_rx(enable_rx),
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.enable_tx(enable_tx),
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.SLD(serload),
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.SEN(serenable),
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.clear_status(),
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.SDI(serdata),
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.SCLK(serclk),
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.adc1_data(adc1_data),
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.adc2_data(adc2_data),
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.adc3_data(adc1_data),
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.adc4_data(adc2_data),
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.dac1_data(dac1_data),
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.dac2_data(dac2_data),
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.dac3_data(),.dac4_data(),
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.adclk0(adclk),.adclk1(),
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.adc_oeb(),.adc_otr(4'b0),
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.clk_out(clk_out),
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.misc_pins(),
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// USB interface
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.usbclk(usbclk),.usbctl(usbctl),
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.usbrdy(usbrdy),.usbdata(usbdata)
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);
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reg clk_120mhz;
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reg usbclk;
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reg reset;
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reg [11:0] adc1_data, adc2_data;
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wire [13:0] dac1_data, dac2_data;
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wire [5:0] usbctl;
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wire [5:0] usbrdy;
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wire [15:0] usbdata;
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reg WE, RD, OE;
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assign usbctl[0] = WE;
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assign usbctl[1] = RD;
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assign usbctl[2] = OE;
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assign usbctl[5:3] = 0;
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wire have_packet_rdy = usbrdy[1];
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reg tb_oe;
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initial tb_oe=1'b1;
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assign usbdata = tb_oe ? usbdatareg : 16'hxxxx;
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reg serload, serenable, serclk, serdata;
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reg enable_tx, enable_rx;
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reg [15:0] usbdatareg;
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///////////////////////////////////////////////
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// Simulation Control
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initial
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begin
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$dumpfile("fullchip_tb.vcd");
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$dumpvars(0, fullchip_tb);
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end
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//initial #1000000 $finish;
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///////////////////////////////////////////////
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// Monitors
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//initial $monitor(dac1_data);
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///////////////////////////////////////////////
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// Clock and reset
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initial clk_120mhz = 0;
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initial usbclk = 0;
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always #24 clk_120mhz = ~clk_120mhz;
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always #60 usbclk = ~usbclk;
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initial reset = 1'b1;
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initial #500 reset = 1'b0;
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/////////////////////////////////////////////////
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// Run AD input
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always @(posedge adclk) adc1_data <= #1 12'd1234;
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always @(posedge adclk) adc2_data <= #1 12'd1234;
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/////////////////////////////////////////////////
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// USB interface
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initial
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begin
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initialize_usb;
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#30000 @(posedge usbclk);
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burst_usb_write(257);
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#30000 burst_usb_read(256);
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#10000 $finish;
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// repeat(30)
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// begin
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// write_from_usb;
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// read_from_usb;
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// end
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end
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/////////////////////////////////////////////////
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// TX and RX enable
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initial enable_tx = 1'b0;
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initial #40000 enable_tx = 1'b1;
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initial enable_rx = 1'b0;
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initial #40000 enable_rx = 1'b1;
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//////////////////////////////////////////////////
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// Set up control bus
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initial
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begin
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#1000 send_config_word(`ch1in_freq,32'h0); // 1 MHz on 60 MHz clock
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send_config_word(`ch2in_freq,32'h0);
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send_config_word(`ch3in_freq,32'h0);
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send_config_word(`ch4in_freq,32'h0);
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send_config_word(`ch1out_freq,32'h01234567);
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send_config_word(`ch2out_freq,32'h0);
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send_config_word(`ch3out_freq,32'h0);
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send_config_word(`ch4out_freq,32'h0);
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send_config_word(`misc,32'h0);
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send_config_word(`rates,{8'd2,8'd12,8'h0f,8'h07});
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// adc, ext, interp, decim
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end
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/////////////////////////////////////////////////////////
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endmodule
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