mirror of https://gerrit.osmocom.org/libusrp
62 lines
1.6 KiB
Verilog
62 lines
1.6 KiB
Verilog
// -*- verilog -*-
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//
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// USRP - Universal Software Radio Peripheral
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//
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// Copyright (C) 2003 Matt Ettus
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//
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// This program is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation; either version 2 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
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//
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module cordic_tb();
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cordic cordic(clk, reset, enable, xi, yi, zi, xo, yo, zo );
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reg reset;
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reg clk;
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reg enable;
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reg [15:0] xi, yi, zi;
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initial reset = 1'b1;
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initial #1000 reset = 1'b0;
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initial clk = 1'b0;
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always #50 clk <= ~clk;
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initial enable = 1'b1;
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initial zi = 16'b0;
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always @(posedge clk)
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zi <= #1 zi + 16'd0;
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wire [15:0] xo,yo,zo;
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initial $dumpfile("cordic.vcd");
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initial $dumpvars(0,cordic_tb);
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initial
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begin
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`include "sine.txt"
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end
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wire [15:0] xiu = {~xi[15],xi[14:0]};
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wire [15:0] yiu = {~yi[15],yi[14:0]};
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wire [15:0] xou = {~xo[15],xo[14:0]};
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wire [15:0] you = {~yo[15],yo[14:0]};
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initial $monitor("%d\t%d\t%d\t%d\t%d",$time,xiu,yiu,xou,you);
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endmodule // cordic_tb
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