mirror of https://gerrit.osmocom.org/libusrp
72 lines
1.4 KiB
Verilog
72 lines
1.4 KiB
Verilog
module cbus_tb;
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`define ch1in_freq 0
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`define ch2in_freq 1
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`define ch3in_freq 2
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`define ch4in_freq 3
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`define ch1out_freq 4
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`define ch2out_freq 5
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`define ch3out_freq 6
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`define ch4out_freq 7
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`define rates 8
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`define misc 9
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task send_config_word;
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input [7:0] addr;
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input [31:0] data;
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integer i;
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begin
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#10 serenable = 1;
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for(i=7;i>=0;i=i-1)
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begin
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#10 serdata = addr[i];
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#10 serclk = 0;
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#10 serclk = 1;
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#10 serclk = 0;
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end
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for(i=31;i>=0;i=i-1)
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begin
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#10 serdata = data[i];
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#10 serclk = 0;
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#10 serclk = 1;
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#10 serclk = 0;
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end
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#10 serenable = 0;
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// #10 serclk = 1;
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// #10 serclk = 0;
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end
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endtask // send_config_word
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initial $dumpfile("cbus_tb.vcd");
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initial $dumpvars(0,cbus_tb);
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initial reset = 1;
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initial #500 reset = 0;
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reg serclk, serdata, serenable, reset;
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wire SDO;
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control_bus control_bus
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( .serial_clock(serclk),
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.serial_data_in(serdata),
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.enable(serenable),
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.reset(reset),
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.serial_data_out(SDO) );
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initial
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begin
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#1000 send_config_word(8'd1,32'hDEAD_BEEF);
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#1000 send_config_word(8'd3,32'hDDEE_FF01);
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#1000 send_config_word(8'd19,32'hFFFF_FFFF);
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#1000 send_config_word(8'd23,32'h1234_FEDC);
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#1000 send_config_word(8'h80,32'h0);
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#1000 send_config_word(8'h81,32'h0);
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#1000 send_config_word(8'h82,32'h0);
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#1000 reset = 1;
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#1 $finish;
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end
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endmodule // cbus_tb
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