mirror of https://gerrit.osmocom.org/libusrp
119 lines
3.3 KiB
Verilog
119 lines
3.3 KiB
Verilog
// -*- verilog -*-
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//
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// USRP - Universal Software Radio Peripheral
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//
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// Copyright (C) 2003,2004 Matt Ettus
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//
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// This program is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation; either version 2 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
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//
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// Serial Control Bus from Cypress chip
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module serial_io
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( input master_clk,
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input serial_clock,
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input serial_data_in,
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input enable,
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input reset,
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inout wire serial_data_out,
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output reg [6:0] serial_addr,
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output reg [31:0] serial_data,
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output wire serial_strobe,
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input wire [31:0] readback_0,
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input wire [31:0] readback_1,
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input wire [31:0] readback_2,
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input wire [31:0] readback_3,
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input wire [31:0] readback_4,
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input wire [31:0] readback_5,
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input wire [31:0] readback_6,
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input wire [31:0] readback_7
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);
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reg is_read;
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reg [7:0] ser_ctr;
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reg write_done;
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assign serial_data_out = is_read ? serial_data[31] : 1'bz;
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always @(posedge serial_clock, posedge reset, negedge enable)
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if(reset)
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ser_ctr <= #1 8'd0;
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else if(~enable)
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ser_ctr <= #1 8'd0;
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else if(ser_ctr == 39)
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ser_ctr <= #1 8'd0;
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else
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ser_ctr <= #1 ser_ctr + 8'd1;
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always @(posedge serial_clock, posedge reset, negedge enable)
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if(reset)
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is_read <= #1 1'b0;
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else if(~enable)
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is_read <= #1 1'b0;
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else if((ser_ctr == 7)&&(serial_addr[6]==1))
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is_read <= #1 1'b1;
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always @(posedge serial_clock, posedge reset)
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if(reset)
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begin
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serial_addr <= #1 7'b0;
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serial_data <= #1 32'b0;
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write_done <= #1 1'b0;
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end
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else if(~enable)
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begin
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//serial_addr <= #1 7'b0;
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//serial_data <= #1 32'b0;
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write_done <= #1 1'b0;
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end
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else
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begin
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if(~is_read && (ser_ctr == 39))
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write_done <= #1 1'b1;
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else
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write_done <= #1 1'b0;
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if(is_read & (ser_ctr==8))
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case (serial_addr)
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7'd1: serial_data <= #1 readback_0;
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7'd2: serial_data <= #1 readback_1;
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7'd3: serial_data <= #1 readback_2;
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7'd4: serial_data <= #1 readback_3;
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7'd5: serial_data <= #1 readback_4;
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7'd6: serial_data <= #1 readback_5;
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7'd7: serial_data <= #1 readback_6;
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7'd8: serial_data <= #1 readback_7;
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default: serial_data <= #1 32'd0;
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endcase // case(serial_addr)
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else if(ser_ctr >= 8)
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serial_data <= #1 {serial_data[30:0],serial_data_in};
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else if(ser_ctr < 8)
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serial_addr <= #1 {serial_addr[5:0],serial_data_in};
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end // else: !if(~enable)
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reg enable_d1, enable_d2;
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always @(posedge master_clk)
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begin
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enable_d1 <= #1 enable;
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enable_d2 <= #1 enable_d1;
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end
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assign serial_strobe = enable_d2 & ~enable_d1;
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endmodule // serial_io
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