mirror of https://gerrit.osmocom.org/libusrp
411 lines
19 KiB
Plaintext
411 lines
19 KiB
Plaintext
# Copyright (C) 1991-2005 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, Altera MegaCore Function License
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# Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors. Please refer to the
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# applicable agreement for further details.
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# The default values for assignments are stored in the file
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# mrfm_assignment_defaults.qdf
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# If this file doesn't exist, and for assignments not listed, see file
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# assignment_defaults.qdf
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# Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus II software
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# and any changes you make may be lost or overwritten.
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# Project-Wide Assignments
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# ========================
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04 JULY 13, 2003"
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set_global_assignment -name LAST_QUARTUS_VERSION "5.1 SP2"
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# Pin & Location Assignments
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# ==========================
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set_global_assignment -name RESERVE_PIN "AS INPUT TRI-STATED"
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set_location_assignment PIN_29 -to SCLK
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set_location_assignment PIN_117 -to SDI
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set_location_assignment PIN_28 -to usbclk
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set_location_assignment PIN_107 -to usbctl[0]
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set_location_assignment PIN_106 -to usbctl[1]
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set_location_assignment PIN_105 -to usbctl[2]
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set_location_assignment PIN_100 -to usbdata[0]
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set_location_assignment PIN_84 -to usbdata[10]
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set_location_assignment PIN_83 -to usbdata[11]
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set_location_assignment PIN_82 -to usbdata[12]
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set_location_assignment PIN_79 -to usbdata[13]
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set_location_assignment PIN_78 -to usbdata[14]
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set_location_assignment PIN_77 -to usbdata[15]
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set_location_assignment PIN_99 -to usbdata[1]
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set_location_assignment PIN_98 -to usbdata[2]
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set_location_assignment PIN_95 -to usbdata[3]
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set_location_assignment PIN_94 -to usbdata[4]
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set_location_assignment PIN_93 -to usbdata[5]
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set_location_assignment PIN_88 -to usbdata[6]
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set_location_assignment PIN_87 -to usbdata[7]
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set_location_assignment PIN_86 -to usbdata[8]
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set_location_assignment PIN_85 -to usbdata[9]
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set_location_assignment PIN_104 -to usbrdy[0]
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set_location_assignment PIN_101 -to usbrdy[1]
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set_location_assignment PIN_76 -to FX2_1
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set_location_assignment PIN_75 -to FX2_2
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set_location_assignment PIN_74 -to FX2_3
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set_location_assignment PIN_116 -to io_rx_a[0]
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set_location_assignment PIN_115 -to io_rx_a[1]
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set_location_assignment PIN_114 -to io_rx_a[2]
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set_location_assignment PIN_113 -to io_rx_a[3]
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set_location_assignment PIN_108 -to io_rx_a[4]
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set_location_assignment PIN_195 -to io_rx_a[5]
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set_location_assignment PIN_196 -to io_rx_a[6]
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set_location_assignment PIN_197 -to io_rx_a[7]
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set_location_assignment PIN_200 -to io_rx_a[8]
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set_location_assignment PIN_201 -to io_rx_a[9]
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set_location_assignment PIN_202 -to io_rx_a[10]
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set_location_assignment PIN_203 -to io_rx_a[11]
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set_location_assignment PIN_206 -to io_rx_a[12]
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set_location_assignment PIN_207 -to io_rx_a[13]
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set_location_assignment PIN_208 -to io_rx_a[14]
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set_location_assignment PIN_214 -to io_rx_b[0]
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set_location_assignment PIN_215 -to io_rx_b[1]
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set_location_assignment PIN_216 -to io_rx_b[2]
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set_location_assignment PIN_217 -to io_rx_b[3]
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set_location_assignment PIN_218 -to io_rx_b[4]
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set_location_assignment PIN_219 -to io_rx_b[5]
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set_location_assignment PIN_222 -to io_rx_b[6]
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set_location_assignment PIN_223 -to io_rx_b[7]
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set_location_assignment PIN_224 -to io_rx_b[8]
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set_location_assignment PIN_225 -to io_rx_b[9]
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set_location_assignment PIN_226 -to io_rx_b[10]
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set_location_assignment PIN_227 -to io_rx_b[11]
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set_location_assignment PIN_228 -to io_rx_b[12]
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set_location_assignment PIN_233 -to io_rx_b[13]
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set_location_assignment PIN_234 -to io_rx_b[14]
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set_location_assignment PIN_175 -to io_tx_a[0]
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set_location_assignment PIN_176 -to io_tx_a[1]
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set_location_assignment PIN_177 -to io_tx_a[2]
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set_location_assignment PIN_178 -to io_tx_a[3]
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set_location_assignment PIN_179 -to io_tx_a[4]
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set_location_assignment PIN_180 -to io_tx_a[5]
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set_location_assignment PIN_181 -to io_tx_a[6]
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set_location_assignment PIN_182 -to io_tx_a[7]
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set_location_assignment PIN_183 -to io_tx_a[8]
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set_location_assignment PIN_184 -to io_tx_a[9]
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set_location_assignment PIN_185 -to io_tx_a[10]
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set_location_assignment PIN_186 -to io_tx_a[11]
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set_location_assignment PIN_187 -to io_tx_a[12]
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set_location_assignment PIN_188 -to io_tx_a[13]
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set_location_assignment PIN_193 -to io_tx_a[14]
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set_location_assignment PIN_73 -to io_tx_b[0]
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set_location_assignment PIN_68 -to io_tx_b[1]
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set_location_assignment PIN_67 -to io_tx_b[2]
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set_location_assignment PIN_66 -to io_tx_b[3]
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set_location_assignment PIN_65 -to io_tx_b[4]
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set_location_assignment PIN_64 -to io_tx_b[5]
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set_location_assignment PIN_63 -to io_tx_b[6]
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set_location_assignment PIN_62 -to io_tx_b[7]
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set_location_assignment PIN_61 -to io_tx_b[8]
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set_location_assignment PIN_60 -to io_tx_b[9]
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set_location_assignment PIN_59 -to io_tx_b[10]
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set_location_assignment PIN_58 -to io_tx_b[11]
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set_location_assignment PIN_57 -to io_tx_b[12]
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set_location_assignment PIN_56 -to io_tx_b[13]
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set_location_assignment PIN_55 -to io_tx_b[14]
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set_location_assignment PIN_152 -to master_clk
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set_location_assignment PIN_144 -to rx_a_a[0]
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set_location_assignment PIN_143 -to rx_a_a[1]
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set_location_assignment PIN_141 -to rx_a_a[2]
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set_location_assignment PIN_140 -to rx_a_a[3]
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set_location_assignment PIN_139 -to rx_a_a[4]
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set_location_assignment PIN_138 -to rx_a_a[5]
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set_location_assignment PIN_137 -to rx_a_a[6]
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set_location_assignment PIN_136 -to rx_a_a[7]
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set_location_assignment PIN_135 -to rx_a_a[8]
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set_location_assignment PIN_134 -to rx_a_a[9]
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set_location_assignment PIN_133 -to rx_a_a[10]
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set_location_assignment PIN_132 -to rx_a_a[11]
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set_location_assignment PIN_23 -to rx_a_b[0]
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set_location_assignment PIN_21 -to rx_a_b[1]
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set_location_assignment PIN_20 -to rx_a_b[2]
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set_location_assignment PIN_19 -to rx_a_b[3]
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set_location_assignment PIN_18 -to rx_a_b[4]
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set_location_assignment PIN_17 -to rx_a_b[5]
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set_location_assignment PIN_16 -to rx_a_b[6]
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set_location_assignment PIN_15 -to rx_a_b[7]
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set_location_assignment PIN_14 -to rx_a_b[8]
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set_location_assignment PIN_13 -to rx_a_b[9]
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set_location_assignment PIN_12 -to rx_a_b[10]
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set_location_assignment PIN_11 -to rx_a_b[11]
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set_location_assignment PIN_131 -to rx_b_a[0]
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set_location_assignment PIN_128 -to rx_b_a[1]
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set_location_assignment PIN_127 -to rx_b_a[2]
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set_location_assignment PIN_126 -to rx_b_a[3]
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set_location_assignment PIN_125 -to rx_b_a[4]
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set_location_assignment PIN_124 -to rx_b_a[5]
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set_location_assignment PIN_123 -to rx_b_a[6]
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set_location_assignment PIN_122 -to rx_b_a[7]
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set_location_assignment PIN_121 -to rx_b_a[8]
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set_location_assignment PIN_120 -to rx_b_a[9]
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set_location_assignment PIN_119 -to rx_b_a[10]
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set_location_assignment PIN_118 -to rx_b_a[11]
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set_location_assignment PIN_8 -to rx_b_b[0]
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set_location_assignment PIN_7 -to rx_b_b[1]
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set_location_assignment PIN_6 -to rx_b_b[2]
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set_location_assignment PIN_5 -to rx_b_b[3]
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set_location_assignment PIN_4 -to rx_b_b[4]
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set_location_assignment PIN_3 -to rx_b_b[5]
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set_location_assignment PIN_2 -to rx_b_b[6]
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set_location_assignment PIN_240 -to rx_b_b[7]
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set_location_assignment PIN_239 -to rx_b_b[8]
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set_location_assignment PIN_238 -to rx_b_b[9]
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set_location_assignment PIN_237 -to rx_b_b[10]
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set_location_assignment PIN_236 -to rx_b_b[11]
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set_location_assignment PIN_156 -to SDO
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set_location_assignment PIN_153 -to SEN_FPGA
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set_location_assignment PIN_159 -to tx_a[0]
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set_location_assignment PIN_160 -to tx_a[1]
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set_location_assignment PIN_161 -to tx_a[2]
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set_location_assignment PIN_162 -to tx_a[3]
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set_location_assignment PIN_163 -to tx_a[4]
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set_location_assignment PIN_164 -to tx_a[5]
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set_location_assignment PIN_165 -to tx_a[6]
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set_location_assignment PIN_166 -to tx_a[7]
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set_location_assignment PIN_167 -to tx_a[8]
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set_location_assignment PIN_168 -to tx_a[9]
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set_location_assignment PIN_169 -to tx_a[10]
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set_location_assignment PIN_170 -to tx_a[11]
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set_location_assignment PIN_173 -to tx_a[12]
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set_location_assignment PIN_174 -to tx_a[13]
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set_location_assignment PIN_38 -to tx_b[0]
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set_location_assignment PIN_39 -to tx_b[1]
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set_location_assignment PIN_41 -to tx_b[2]
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set_location_assignment PIN_42 -to tx_b[3]
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set_location_assignment PIN_43 -to tx_b[4]
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set_location_assignment PIN_44 -to tx_b[5]
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set_location_assignment PIN_45 -to tx_b[6]
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set_location_assignment PIN_46 -to tx_b[7]
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set_location_assignment PIN_47 -to tx_b[8]
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set_location_assignment PIN_48 -to tx_b[9]
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set_location_assignment PIN_49 -to tx_b[10]
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set_location_assignment PIN_50 -to tx_b[11]
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set_location_assignment PIN_53 -to tx_b[12]
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set_location_assignment PIN_54 -to tx_b[13]
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set_location_assignment PIN_158 -to TXSYNC_A
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set_location_assignment PIN_37 -to TXSYNC_B
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set_location_assignment PIN_235 -to io_rx_b[15]
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set_location_assignment PIN_24 -to io_tx_b[15]
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set_location_assignment PIN_213 -to io_rx_a[15]
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set_location_assignment PIN_194 -to io_tx_a[15]
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set_location_assignment PIN_1 -to MYSTERY_SIGNAL
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# Timing Assignments
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# ==================
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set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF
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# Analysis & Synthesis Assignments
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# ================================
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set_global_assignment -name SAVE_DISK_SPACE OFF
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set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP"
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set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240
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set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
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set_global_assignment -name FAMILY Cyclone
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set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED
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set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED
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set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED
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set_global_assignment -name TOP_LEVEL_ENTITY mrfm
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set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
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set_global_assignment -name USER_LIBRARIES "e:\\usrp\\fpga\\megacells"
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set_global_assignment -name AUTO_ENABLE_SMART_COMPILE ON
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# Fitter Assignments
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# ==================
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set_global_assignment -name DEVICE EP1C12Q240C8
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set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "PASSIVE SERIAL"
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set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
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set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
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set_global_assignment -name OPTIMIZE_TIMING "NORMAL COMPILATION"
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set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
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set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
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set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
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set_global_assignment -name IO_PLACEMENT_OPTIMIZATION OFF
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set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
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set_global_assignment -name INC_PLC_MODE OFF
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set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE OFF
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set_instance_assignment -name IO_STANDARD LVTTL -to usbdata[12]
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set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVTTL
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set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
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# Timing Analysis Assignments
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# ===========================
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set_global_assignment -name MAX_SCC_SIZE 50
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# EDA Netlist Writer Assignments
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# ==============================
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set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
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set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<NONE>"
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set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<NONE>"
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set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<NONE>"
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set_global_assignment -name EDA_RESYNTHESIS_TOOL "<NONE>"
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# Assembler Assignments
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# =====================
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set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
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set_global_assignment -name GENERATE_RBF_FILE ON
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set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
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set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
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# Simulator Assignments
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# =====================
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set_global_assignment -name START_TIME "0 ns"
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set_global_assignment -name GLITCH_INTERVAL "1 ns"
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# Design Assistant Assignments
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# ============================
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set_global_assignment -name DRC_REPORT_TOP_FANOUT OFF
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set_global_assignment -name DRC_REPORT_FANOUT_EXCEEDING OFF
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set_global_assignment -name ASSG_CAT OFF
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set_global_assignment -name ASSG_RULE_MISSING_FMAX OFF
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set_global_assignment -name ASSG_RULE_MISSING_TIMING OFF
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set_global_assignment -name NONSYNCHSTRUCT_RULE_ASYN_RAM OFF
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set_global_assignment -name CLK_CAT OFF
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set_global_assignment -name CLK_RULE_COMB_CLOCK OFF
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set_global_assignment -name CLK_RULE_INV_CLOCK OFF
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set_global_assignment -name CLK_RULE_GATING_SCHEME OFF
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set_global_assignment -name CLK_RULE_INPINS_CLKNET OFF
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set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES OFF
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set_global_assignment -name CLK_RULE_MIX_EDGES OFF
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set_global_assignment -name RESET_CAT OFF
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set_global_assignment -name RESET_RULE_INPINS_RESETNET OFF
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set_global_assignment -name RESET_RULE_UNSYNCH_EXRESET OFF
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set_global_assignment -name RESET_RULE_IMSYNCH_EXRESET OFF
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set_global_assignment -name RESET_RULE_COMB_ASYNCH_RESET OFF
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set_global_assignment -name RESET_RULE_UNSYNCH_ASYNCH_DOMAIN OFF
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set_global_assignment -name RESET_RULE_IMSYNCH_ASYNCH_DOMAIN OFF
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set_global_assignment -name TIMING_CAT OFF
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set_global_assignment -name TIMING_RULE_SHIFT_REG OFF
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set_global_assignment -name TIMING_RULE_COIN_CLKEDGE OFF
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set_global_assignment -name NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE OFF
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set_global_assignment -name NONSYNCHSTRUCT_CAT OFF
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set_global_assignment -name NONSYNCHSTRUCT_RULE_COMBLOOP OFF
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set_global_assignment -name NONSYNCHSTRUCT_RULE_REG_LOOP OFF
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set_global_assignment -name NONSYNCHSTRUCT_RULE_DELAY_CHAIN OFF
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set_global_assignment -name NONSYNCHSTRUCT_RULE_RIPPLE_CLK OFF
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set_global_assignment -name NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN OFF
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set_global_assignment -name NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR OFF
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set_global_assignment -name NONSYNCHSTRUCT_RULE_SRLATCH OFF
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set_global_assignment -name NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED OFF
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set_global_assignment -name SIGNALRACE_CAT OFF
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set_global_assignment -name ACLK_CAT OFF
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set_global_assignment -name ACLK_RULE_NO_SZER_ACLK_DOMAIN OFF
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set_global_assignment -name ACLK_RULE_SZER_BTW_ACLK_DOMAIN OFF
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set_global_assignment -name ACLK_RULE_IMSZER_ADOMAIN OFF
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set_global_assignment -name HCPY_CAT OFF
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set_global_assignment -name HCPY_VREF_PINS OFF
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# SignalTap II Assignments
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# ========================
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set_global_assignment -name HUB_ENTITY_NAME SLD_HUB
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set_global_assignment -name HUB_INSTANCE_NAME SLD_HUB_INST
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set_global_assignment -name ENABLE_SIGNALTAP OFF
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# LogicLock Region Assignments
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# ============================
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set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF
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# -----------------
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# start CLOCK(SCLK)
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# Timing Assignments
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# ==================
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set_global_assignment -name DUTY_CYCLE 50 -section_id SCLK
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set_global_assignment -name FMAX_REQUIREMENT "1 MHz" -section_id SCLK
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set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id SCLK
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# end CLOCK(SCLK)
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# ---------------
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# -----------------------
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# start CLOCK(master_clk)
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# Timing Assignments
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# ==================
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set_global_assignment -name DUTY_CYCLE 50 -section_id master_clk
|
|
set_global_assignment -name FMAX_REQUIREMENT "64 MHz" -section_id master_clk
|
|
set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id master_clk
|
|
|
|
# end CLOCK(master_clk)
|
|
# ---------------------
|
|
|
|
# -------------------
|
|
# start CLOCK(usbclk)
|
|
|
|
# Timing Assignments
|
|
# ==================
|
|
set_global_assignment -name DUTY_CYCLE 50 -section_id usbclk
|
|
set_global_assignment -name FMAX_REQUIREMENT "48 MHz" -section_id usbclk
|
|
set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id usbclk
|
|
|
|
# end CLOCK(usbclk)
|
|
# -----------------
|
|
|
|
# ----------------------
|
|
# start ENTITY(mrfm)
|
|
|
|
# Timing Assignments
|
|
# ==================
|
|
set_instance_assignment -name CLOCK_SETTINGS SCLK -to SCLK
|
|
set_instance_assignment -name CLOCK_SETTINGS usbclk -to usbclk
|
|
set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk
|
|
|
|
# end ENTITY(mrfm)
|
|
# --------------------
|
|
|
|
|
|
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
|
|
set_global_assignment -name SMART_RECOMPILE ON
|
|
set_global_assignment -name VERILOG_FILE mrfm.vh
|
|
set_global_assignment -name VERILOG_FILE biquad_2stage.v
|
|
set_global_assignment -name VERILOG_FILE mrfm_compensator.v
|
|
set_global_assignment -name VERILOG_FILE ../../sdr_lib/ram16.v
|
|
set_global_assignment -name VERILOG_FILE mrfm_proc.v
|
|
set_global_assignment -name VERILOG_FILE ../../megacells/fifo_4k.v
|
|
set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/acc.v
|
|
set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mult.v
|
|
set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/ram16_2sum.v
|
|
set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/coeff_rom.v
|
|
set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/halfband_decim.v
|
|
set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mac.v
|
|
set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/coeff_ram.v
|
|
set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_chain.v
|
|
set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_dcoffset.v
|
|
set_global_assignment -name VERILOG_FILE ../../sdr_lib/adc_interface.v
|
|
set_global_assignment -name VERILOG_FILE ../../sdr_lib/io_pins.v
|
|
set_global_assignment -name VERILOG_FILE ../../sdr_lib/setting_reg.v
|
|
set_global_assignment -name VERILOG_FILE ../../sdr_lib/bidir_reg.v
|
|
set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_int_shifter.v
|
|
set_global_assignment -name VERILOG_FILE ../../megacells/clk_doubler.v
|
|
set_global_assignment -name VERILOG_FILE ../../sdr_lib/gen_sync.v
|
|
set_global_assignment -name VERILOG_FILE ../../sdr_lib/master_control.v
|
|
set_global_assignment -name VERILOG_FILE ../../megacells/fifo_2k.v
|
|
set_global_assignment -name VERILOG_FILE ../../megacells/bustri.v
|
|
set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_buffer.v
|
|
set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_buffer.v
|
|
set_global_assignment -name VERILOG_FILE ../../sdr_lib/phase_acc.v
|
|
set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_interp.v
|
|
set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_decim.v
|
|
set_global_assignment -name VERILOG_FILE ../../sdr_lib/cordic_stage.v
|
|
set_global_assignment -name VERILOG_FILE ../../sdr_lib/cordic.v
|
|
set_global_assignment -name VERILOG_FILE mrfm.v
|
|
set_global_assignment -name VERILOG_FILE ../../sdr_lib/clk_divider.v
|
|
set_global_assignment -name VERILOG_FILE ../../sdr_lib/serial_io.v
|
|
set_global_assignment -name VERILOG_FILE ../../sdr_lib/strobe_gen.v
|
|
set_global_assignment -name VERILOG_FILE ../../sdr_lib/sign_extend.v
|
|
set_global_assignment -name FITTER_EFFORT "STANDARD FIT" |