mirror of https://gerrit.osmocom.org/libusrp
23 lines
784 B
Verilog
23 lines
784 B
Verilog
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module rx_dcoffset (input clock, input enable, input reset,
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input signed [15:0] adc_in, output signed [15:0] adc_out,
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input wire [6:0] serial_addr, input wire [31:0] serial_data, input serial_strobe);
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parameter MYADDR = 0;
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reg signed [31:0] integrator;
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wire signed [15:0] scaled_integrator = integrator[31:16] + (integrator[31] & |integrator[15:0]);
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assign adc_out = adc_in - scaled_integrator;
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// FIXME do we need signed?
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//FIXME What do we do when clipping?
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always @(posedge clock)
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if(reset)
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integrator <= #1 32'd0;
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else if(serial_strobe & (MYADDR == serial_addr))
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integrator <= #1 {serial_data[15:0],16'd0};
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else if(enable)
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integrator <= #1 integrator + adc_out;
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endmodule // rx_dcoffset
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