mirror of https://gerrit.osmocom.org/libusrp
18 lines
356 B
Verilog
18 lines
356 B
Verilog
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module ram32 (input clock, input write,
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input [4:0] wr_addr, input [15:0] wr_data,
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input [4:0] rd_addr, output reg [15:0] rd_data);
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reg [15:0] ram_array [0:31];
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always @(posedge clock)
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rd_data <= #1 ram_array[rd_addr];
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always @(posedge clock)
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if(write)
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ram_array[wr_addr] <= #1 wr_data;
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endmodule // ram32
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