mirror of https://gerrit.osmocom.org/libusrp
44 lines
1.2 KiB
Verilog
44 lines
1.2 KiB
Verilog
// -*- verilog -*-
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//
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// USRP - Universal Software Radio Peripheral
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//
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// Copyright (C) 2003 Matt Ettus
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//
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// This program is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation; either version 2 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
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//
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module gen_sync
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( input clock,
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input reset,
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input enable,
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input [7:0] rate,
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output wire sync );
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// parameter width = 8;
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reg [7:0] counter;
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assign sync = |(((rate+1)>>1)& counter);
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always @(posedge clock)
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if(reset || ~enable)
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counter <= #1 0;
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else if(counter == rate)
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counter <= #1 0;
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else
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counter <= #1 counter + 8'd1;
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endmodule // gen_sync
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