libusrp/fpga/megacells/addsub16_inst.v

10 lines
193 B
Verilog
Executable File

addsub16 addsub16_inst (
.add_sub ( add_sub_sig ),
.dataa ( dataa_sig ),
.datab ( datab_sig ),
.clock ( clock_sig ),
.aclr ( aclr_sig ),
.clken ( clken_sig ),
.result ( result_sig )
);