200 lines
4.0 KiB
Verilog
200 lines
4.0 KiB
Verilog
/*
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* top.v
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*
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* vim: ts=4 sw=4
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*
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* Top-level for the icE1usb icebreaker/bitsy based prototypes
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*
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* Copyright (C) 2019-2020 Sylvain Munaut <tnt@246tNt.com>
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* SPDX-License-Identifier: CERN-OHL-S-2.0
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*/
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`default_nettype none
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module top (
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// E1 PHY
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input wire e1_rx_hi_p,
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// input wire e1_rx_hi_n,
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input wire e1_rx_lo_p,
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// input wire e1_rx_lo_n,
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output wire e1_tx_hi,
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output wire e1_tx_lo,
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output wire e1_vref_ct_pdm,
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output wire e1_vref_p_pdm,
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output wire e1_vref_n_pdm,
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// USB
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inout wire usb_dp,
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inout wire usb_dn,
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output wire usb_pu,
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// Flash
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inout wire flash_mosi,
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inout wire flash_miso,
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inout wire flash_clk,
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inout wire flash_cs_n,
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// Button
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input wire btn,
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// Clock (30.72 MHz)
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input wire clk_in,
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output wire clk_tune_hi,
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output wire clk_tune_lo,
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// Debug UART
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input wire dbg_rx,
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output wire dbg_tx,
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// RGB LEDs
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output wire [2:0] rgb
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);
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localparam integer WB_N = 1;
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genvar i;
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// Signals
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// -------
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// Flash SPI internal signals
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wire flash_mosi_i, flash_miso_i, flash_clk_i;
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wire flash_mosi_o, flash_miso_o, flash_clk_o;
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wire flash_mosi_oe, flash_miso_oe, flash_clk_oe;
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wire flash_csn_o;
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// Peripheral wishbone
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wire [15:0] wb_addr;
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wire [31:0] wb_rdata [0:WB_N-1];
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wire [31:0] wb_wdata;
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wire [ 3:0] wb_wmsk;
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wire wb_we;
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wire [WB_N-1:0] wb_cyc;
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wire [WB_N-1:0] wb_ack;
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wire [(WB_N*32)-1:0] wb_rdata_flat;
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// Ticks
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wire [3:0] tick_e1;
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wire tick_usb_sof;
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// Clocks / Reset
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wire rst_req;
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wire clk_sys;
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wire rst_sys;
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wire clk_48m;
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wire rst_48m;
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// SoC base
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// --------
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// Instance
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soc_base #(
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.WB_N(WB_N),
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.E1_N(1),
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.E1_UNIT_HAS_RX(1'b1),
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.E1_UNIT_HAS_TX(1'b1),
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.E1_LIU(0)
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) soc_I (
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.e1_rx_hi_p (e1_rx_hi_p),
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// .e1_rx_hi_n (e1_rx_hi_n),
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.e1_rx_lo_p (e1_rx_lo_p),
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// .e1_rx_lo_n (e1_rx_lo_n),
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.e1_tx_hi (e1_tx_hi),
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.e1_tx_lo (e1_tx_lo),
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.e1_rx_data (),
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.e1_rx_clk (),
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.e1_tx_data (),
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.e1_tx_clk (),
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.usb_dp (usb_dp),
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.usb_dn (usb_dn),
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.usb_pu (usb_pu),
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.flash_mosi_i (flash_mosi_i),
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.flash_mosi_o (flash_mosi_o),
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.flash_mosi_oe(flash_mosi_oe),
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.flash_miso_i (flash_miso_i),
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.flash_miso_o (flash_miso_o),
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.flash_miso_oe(flash_miso_oe),
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.flash_clk_i (flash_clk_i),
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.flash_clk_o (flash_clk_o),
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.flash_clk_oe (flash_clk_oe),
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.flash_csn_o (flash_csn_o),
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.dbg_rx (dbg_rx),
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.dbg_tx (dbg_tx),
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.rgb (rgb),
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.wb_m_addr (wb_addr),
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.wb_m_rdata (wb_rdata_flat),
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.wb_m_wdata (wb_wdata),
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.wb_m_wmsk (wb_wmsk),
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.wb_m_we (wb_we),
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.wb_m_cyc (wb_cyc),
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.wb_m_ack (wb_ack),
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.tick_e1 (tick_e1),
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.tick_usb_sof (tick_usb_sof),
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.clk_sys (clk_sys),
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.rst_sys (rst_sys),
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.clk_48m (clk_48m),
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.rst_48m (rst_48m)
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);
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// WB read data flattening
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for (i=0; i<WB_N; i=i+1)
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assign wb_rdata_flat[i*32+:32] = wb_rdata[i];
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// SPI IO
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SB_IO #(
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.PIN_TYPE(6'b101001),
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.PULLUP(1'b1)
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) spi_io_I[2:0] (
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.PACKAGE_PIN ({flash_mosi, flash_miso, flash_clk }),
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.OUTPUT_ENABLE({flash_mosi_oe, flash_miso_oe, flash_clk_oe}),
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.D_OUT_0 ({flash_mosi_o, flash_miso_o, flash_clk_o }),
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.D_IN_0 ({flash_mosi_i, flash_miso_i, flash_clk_i })
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);
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assign flash_cs_n = flash_csn_o;
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// Misc [0]
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// ----
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misc misc_I (
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.e1_vref_ct_pdm(e1_vref_ct_pdm),
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.e1_vref_p_pdm (e1_vref_p_pdm),
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.e1_vref_n_pdm (e1_vref_n_pdm),
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.clk_tune_hi (clk_tune_hi),
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.clk_tune_lo (clk_tune_lo),
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.btn (btn),
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.tick_e1 (tick_e1),
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.tick_usb_sof (tick_usb_sof),
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.rst_req (rst_req),
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.wb_addr (wb_addr[7:0]),
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.wb_rdata (wb_rdata[0]),
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.wb_wdata (wb_wdata),
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.wb_we (wb_we),
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.wb_cyc (wb_cyc[0]),
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.wb_ack (wb_ack[0]),
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.clk (clk_sys),
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.rst (rst_sys)
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);
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// Clock / Reset
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// -------------
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sysmgr sys_mgr_I (
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.clk_in (clk_in),
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.rst_in (rst_req),
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.clk_sys(clk_sys),
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.rst_sys(rst_sys),
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.clk_48m(clk_48m),
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.rst_48m(rst_48m)
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);
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endmodule // top
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