228 lines
4.7 KiB
Verilog
228 lines
4.7 KiB
Verilog
/*
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* misc.v
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*
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* vim: ts=4 sw=4
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*
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* Misc peripheral functions
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*
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* Copyright (C) 2019-2020 Sylvain Munaut <tnt@246tNt.com>
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* SPDX-License-Identifier: CERN-OHL-S-2.0
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*/
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`default_nettype none
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// `define WITH_PDM_READBACK
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module misc (
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// PDM outputs
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output wire e1_vref_ct_pdm,
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output wire e1_vref_p_pdm,
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output wire e1_vref_n_pdm,
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output wire clk_tune_hi,
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output wire clk_tune_lo,
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// Button
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input wire btn,
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// Ticks
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input wire [3:0] tick_e1,
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input wire tick_usb_sof,
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// Reset request
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output wire rst_req,
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// Wishbone
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input wire [ 7:0] wb_addr,
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output reg [31:0] wb_rdata,
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input wire [31:0] wb_wdata,
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input wire wb_we,
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input wire wb_cyc,
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output reg wb_ack,
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// Clock / Reset
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input wire clk,
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input wire rst
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);
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// Signals
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// -------
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// Bus
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wire bus_clr;
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reg bus_we_boot;
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reg bus_we_tick_sel;
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reg [ 1:0] bus_we_pdm_clk;
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reg [ 2:0] bus_we_pdm_e1;
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// Counters
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reg [1:0] tick_e1_sel;
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wire tick_e1_mux;
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wire [15:0] cap_e1;
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wire [31:0] cnt_time;
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// PDM
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reg [12:0] pdm_clk[0:1];
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reg [ 8:0] pdm_e1[0:2];
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// Boot
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reg [1:0] boot_sel;
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reg boot_now;
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// Bus interface
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// -------------
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// Ack
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always @(posedge clk)
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wb_ack <= wb_cyc & ~wb_ack;
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assign bus_clr = ~wb_cyc | wb_ack;
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// Write enables
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always @(posedge clk)
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if (bus_clr | ~wb_we) begin
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bus_we_boot <= 1'b0;
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bus_we_tick_sel <= 1'b0;
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bus_we_pdm_clk[0] <= 1'b0;
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bus_we_pdm_clk[1] <= 1'b0;
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bus_we_pdm_e1[0] <= 1'b0;
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bus_we_pdm_e1[1] <= 1'b0;
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bus_we_pdm_e1[2] <= 1'b0;
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end else begin
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bus_we_boot <= wb_addr == 4'h0;
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bus_we_tick_sel <= wb_addr == 4'h4;
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bus_we_pdm_clk[0] <= wb_addr == 4'h8;
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bus_we_pdm_clk[1] <= wb_addr == 4'h9;
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bus_we_pdm_e1[0] <= wb_addr == 4'ha;
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bus_we_pdm_e1[1] <= wb_addr == 4'hb;
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bus_we_pdm_e1[2] <= wb_addr == 4'hc;
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end
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// Read mux
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always @(posedge clk)
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if (bus_clr)
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wb_rdata <= 32'h00000000;
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else
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case (wb_addr[3:0])
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4'h4: wb_rdata <= { 16'h0000, cap_e1 };
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4'h7: wb_rdata <= cnt_time;
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`ifdef WITH_PDM_READBACK
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4'h8: wb_rdata <= { pdm_clk[0][12], 19'h00000, pdm_clk[0][11:0] };
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4'h9: wb_rdata <= { pdm_clk[1][12], 19'h00000, pdm_clk[1][11:0] };
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4'ha: wb_rdata <= { pdm_e1[0][8], 23'h000000, pdm_e1[0][ 7:0] };
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4'hb: wb_rdata <= { pdm_e1[1][8], 23'h000000, pdm_e1[1][ 7:0] };
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4'hc: wb_rdata <= { pdm_e1[2][8], 23'h000000, pdm_e1[2][ 7:0] };
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`endif
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default: wb_rdata <= 32'hxxxxxxxx;
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endcase
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// Counters
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// --------
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// E1 ticks
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always @(posedge clk)
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if (bus_we_tick_sel)
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tick_e1_sel <= wb_wdata[1:0];
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assign tick_e1_mux = tick_e1[tick_e1_sel];
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capcnt #(
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.W(16)
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) e1_cnt_I (
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.cnt_cur (),
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.cnt_cap (cap_e1),
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.inc (tick_e1_mux),
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.cap (tick_usb_sof),
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.clk (clk),
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.rst (rst)
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);
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// Time
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capcnt #(
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.W(32)
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) time_cnt_I (
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.cnt_cur (cnt_time),
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.cnt_cap (),
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.inc (1'b1),
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.cap (1'b0),
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.clk (clk),
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.rst (rst)
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);
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// PDM outputs
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// -----------
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// Registers
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always @(posedge clk or posedge rst)
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if (rst) begin
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pdm_clk[0] <= 0; // 13'h1800;
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pdm_clk[1] <= 0; // 13'h1800;
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pdm_e1[0] <= 0; // 9'h190;
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pdm_e1[1] <= 0; // 9'h190;
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pdm_e1[2] <= 0; // 9'h190;
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end else begin
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if (bus_we_pdm_clk[0]) pdm_clk[0] <= { wb_wdata[31], wb_wdata[11:0] };
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if (bus_we_pdm_clk[1]) pdm_clk[1] <= { wb_wdata[31], wb_wdata[11:0] };
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if (bus_we_pdm_e1[0]) pdm_e1[0] <= { wb_wdata[31], wb_wdata[ 7:0] };
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if (bus_we_pdm_e1[1]) pdm_e1[1] <= { wb_wdata[31], wb_wdata[ 7:0] };
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if (bus_we_pdm_e1[2]) pdm_e1[2] <= { wb_wdata[31], wb_wdata[ 7:0] };
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end
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// PDM cores
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pdm #(
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.WIDTH(12),
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.PHY("ICE40"),
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.DITHER("YES")
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) pdm_clk_I[1:0] (
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.pdm ({ clk_tune_hi, clk_tune_lo }),
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.cfg_val({ pdm_clk[1][11:0], pdm_clk[0][11:0] }),
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.cfg_oe ({ pdm_clk[1][12], pdm_clk[0][12] }),
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.clk (clk),
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.rst (rst)
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);
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pdm #(
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.WIDTH(8),
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.PHY("ICE40"),
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.DITHER("NO")
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) pdm_e1_I[2:0] (
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.pdm ({ e1_vref_ct_pdm, e1_vref_p_pdm, e1_vref_n_pdm }),
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.cfg_val({ pdm_e1[2][7:0], pdm_e1[1][7:0], pdm_e1[0][7:0] }),
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.cfg_oe ({ pdm_e1[2][8], pdm_e1[1][8], pdm_e1[0][8] }),
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.clk (clk),
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.rst (rst)
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);
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// DFU / Reboot
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// ------------
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always @(posedge clk or posedge rst)
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if (rst) begin
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boot_now <= 1'b0;
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boot_sel <= 2'b00;
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end else if (bus_we_boot) begin
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boot_now <= wb_wdata[2];
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boot_sel <= wb_wdata[1:0];
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end
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dfu_helper #(
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.TIMER_WIDTH(26),
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.BTN_MODE(3),
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.DFU_MODE(0)
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) dfu_I (
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.boot_sel(boot_sel),
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.boot_now(boot_now),
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.btn_pad (btn),
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.btn_val (),
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.rst_req (rst_req),
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.clk (clk),
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.rst (rst)
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);
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endmodule // misc
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